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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D">Looks good, not getting any more failures.<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D"><o:p> </o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D">Thanks a lot!<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D"><o:p> </o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D">Michael<o:p></o:p></span></p>
<p class="MsoNormal"><a name="_MailEndCompose"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D"><o:p> </o:p></span></a></p>
<p class="MsoNormal"><b><span style="font-size:10.0pt;font-family:"Tahoma","sans-serif"">From:</span></b><span style="font-size:10.0pt;font-family:"Tahoma","sans-serif""> chandlerc@google.com [mailto:chandlerc@google.com]
<b>On Behalf Of </b>Chandler Carruth<br>
<b>Sent:</b> Monday, August 04, 2014 02:21<br>
<b>To:</b> Chandler Carruth<br>
<b>Cc:</b> Kuperstein, Michael M; Commit Messages and Patches for LLVM<br>
<b>Subject:</b> Re: [llvm] r214625 - [x86] Teach the target shuffle mask extraction to recognize unary forms<o:p></o:p></span></p>
<p class="MsoNormal"><o:p> </o:p></p>
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<p class="MsoNormal" style="line-height:115%">Fixed in r214673.<o:p></o:p></p>
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<p class="MsoNormal" style="line-height:115%"><o:p> </o:p></p>
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<div>
<p class="MsoNormal" style="line-height:115%">This was an *amazing* find. I can't actually reproduce it in any usefully stable way so I wasn't able to include a useful regression test, but I understand the core cause of the bug and the commit should fix it.
That said, please give the new code a spin and let me know if you see any other failures.<o:p></o:p></p>
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<div>
<p class="MsoNormal" style="line-height:115%"><o:p> </o:p></p>
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<div>
<p class="MsoNormal" style="line-height:115%">Thanks!<o:p></o:p></p>
</div>
<div>
<p class="MsoNormal" style="line-height:115%">-Chandler<o:p></o:p></p>
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<p class="MsoNormal" style="margin-bottom:12.0pt;line-height:115%"><o:p> </o:p></p>
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<p class="MsoNormal" style="line-height:115%">On Sun, Aug 3, 2014 at 2:43 PM, Chandler Carruth <<a href="mailto:chandlerc@gmail.com" target="_blank">chandlerc@gmail.com</a>> wrote:<o:p></o:p></p>
<p>Thanks for the report and test case! Looking into it now.<o:p></o:p></p>
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<div>
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<p class="MsoNormal" style="line-height:115%">On Aug 3, 2014 5:30 AM, "Kuperstein, Michael M" <<a href="mailto:michael.m.kuperstein@intel.com" target="_blank">michael.m.kuperstein@intel.com</a>> wrote:<o:p></o:p></p>
<p class="MsoNormal" style="margin-bottom:12.0pt;line-height:115%">Hi Chandler,<br>
<br>
This broke quite a few internal tests for me, I'm attaching a bugpoint reduced test-case, run it with -mcpu=corei7-avx or above.<br>
It looks like a pshufb is indeed getting formed, but something goes wrong downstream, and we end up with:<br>
<br>
LLVM ERROR: Cannot select: 0x31d95d8: i64 = ConstantPool<<16 x i8> <i8 12, i8 13, i8 14, i8 15, i8 12, i8 13, i8 14, i815, i8 12, i8 13, i8 14, i8 15, i8 12, i8 13, i8 14, i8 15>> 0 [ID=3]<br>
In function: sample_test<br>
Stack dump:<br>
0. Program arguments: llc bugpoint-reduced-simplified.ll -mcpu=corei7-avx -debug<br>
1. Running pass 'Function Pass Manager' on module 'bugpoint-reduced-simplified.ll'.<br>
2. Running pass 'X86 DAG->DAG Instruction Selection' on function '@sample_test'<br>
<br>
Unfortunately, I have no idea how constant pool lowering is supposed to work, so can't say anything useful about how or why that happens.<br>
<br>
Thanks,<br>
Michael<br>
<br>
-----Original Message-----<br>
From: <a href="mailto:llvm-commits-bounces@cs.uiuc.edu" target="_blank">llvm-commits-bounces@cs.uiuc.edu</a> [mailto:<a href="mailto:llvm-commits-bounces@cs.uiuc.edu" target="_blank">llvm-commits-bounces@cs.uiuc.edu</a>] On Behalf Of Chandler Carruth<br>
Sent: Saturday, August 02, 2014 13:28<br>
To: <a href="mailto:llvm-commits@cs.uiuc.edu" target="_blank">llvm-commits@cs.uiuc.edu</a><br>
Subject: [llvm] r214625 - [x86] Teach the target shuffle mask extraction to recognize unary forms<br>
<br>
Author: chandlerc<br>
Date: Sat Aug 2 05:27:38 2014<br>
New Revision: 214625<br>
<br>
URL: <a href="http://llvm.org/viewvc/llvm-project?rev=214625&view=rev" target="_blank">
http://llvm.org/viewvc/llvm-project?rev=214625&view=rev</a><br>
Log:<br>
[x86] Teach the target shuffle mask extraction to recognize unary forms of normally binary shuffle instructions like PUNPCKL and MOVLHPS.<br>
<br>
This detects cases where a single register is used for both operands making the shuffle behave in a unary way. We detect this and adjust the mask to use the unary form which allows the existing DAG combine for shuffle instructions to actually work at all.<br>
<br>
As a consequence, this uncovered a number of obvious bugs in the existing DAG combine which are fixed. It also now canonicalizes several shuffles even with the existing lowering. These typically are trying to match the shuffle to the domain of the input where
before we only really modeled them with the floating point variants. All of the cases which change to an integer shuffle here have something in the integer domain, so there are no more or fewer domain crosses here AFAICT. Technically, it might be better to
go from a GPR directly to the floating point domain, but detecting floating point *outputs* despite integer inputs is a lot more code and seems unlikely to be worthwhile in practice. If folks are seeing domain-crossing regressions here though, let me know
and I can hack something up to fix it.<br>
<br>
Also as a consequence, a bunch of missed opportunities to form pshufb now can be formed. Notably, splats of i8s now form pshufb.<br>
Interestingly, this improves the existing splat lowering too. We go from<br>
3 instructions to 1. Yes, we may tie up a register, but it seems very likely to be worth it, especially if splatting the 0th byte (the common case) as then we can use a zeroed register as the mask.<br>
<br>
Modified:<br>
llvm/trunk/lib/Target/X86/X86ISelLowering.cpp<br>
llvm/trunk/test/CodeGen/X86/avx-basic.ll<br>
llvm/trunk/test/CodeGen/X86/avx-splat.ll<br>
llvm/trunk/test/CodeGen/X86/exedepsfix-broadcast.ll<br>
llvm/trunk/test/CodeGen/X86/vec_splat-3.ll<br>
<br>
Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=214625&r1=214624&r2=214625&view=diff" target="_blank">
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=214625&r1=214624&r2=214625&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)<br>
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Sat Aug 2 05:27:38<br>
+++ 2014<br>
@@ -5133,30 +5133,38 @@ static SDValue getShuffleVectorZeroOrUnd }<br>
<br>
/// getTargetShuffleMask - Calculates the shuffle mask corresponding to the -/// target specific opcode. Returns true if the Mask could be calculated.<br>
-/// Sets IsUnary to true if only uses one source.<br>
+/// target specific opcode. Returns true if the Mask could be<br>
+calculated. Sets /// IsUnary to true if only uses one source. Note that<br>
+this will set IsUnary for /// shuffles which use a single input<br>
+multiple times, and in those cases it will /// adjust the mask to only have indices within that single input.<br>
static bool getTargetShuffleMask(SDNode *N, MVT VT,<br>
SmallVectorImpl<int> &Mask, bool &IsUnary) {<br>
unsigned NumElems = VT.getVectorNumElements();<br>
SDValue ImmN;<br>
<br>
IsUnary = false;<br>
+ bool IsFakeUnary = false;<br>
switch(N->getOpcode()) {<br>
case X86ISD::SHUFP:<br>
ImmN = N->getOperand(N->getNumOperands()-1);<br>
DecodeSHUFPMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);<br>
+ IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);<br>
break;<br>
case X86ISD::UNPCKH:<br>
DecodeUNPCKHMask(VT, Mask);<br>
+ IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);<br>
break;<br>
case X86ISD::UNPCKL:<br>
DecodeUNPCKLMask(VT, Mask);<br>
+ IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);<br>
break;<br>
case X86ISD::MOVHLPS:<br>
DecodeMOVHLPSMask(NumElems, Mask);<br>
+ IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);<br>
break;<br>
case X86ISD::MOVLHPS:<br>
DecodeMOVLHPSMask(NumElems, Mask);<br>
+ IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);<br>
break;<br>
case X86ISD::PALIGNR:<br>
ImmN = N->getOperand(N->getNumOperands()-1);<br>
@@ -5210,6 +5218,14 @@ static bool getTargetShuffleMask(SDNode<br>
default: llvm_unreachable("unknown target shuffle node");<br>
}<br>
<br>
+ // If we have a fake unary shuffle, the shuffle mask is spread across<br>
+ two // inputs that are actually the same node. Re-map the mask to<br>
+ always point // into the first input.<br>
+ if (IsFakeUnary)<br>
+ for (int &M : Mask)<br>
+ if (M >= (int)Mask.size())<br>
+ M -= Mask.size();<br>
+<br>
return true;<br>
}<br>
<br>
@@ -18735,6 +18751,8 @@ static bool combineX86ShuffleChain(SDVal<br>
bool Lo = Mask.equals(0, 0);<br>
unsigned Shuffle = FloatDomain ? (Lo ? X86ISD::MOVLHPS : X86ISD::MOVHLPS)<br>
: (Lo ? X86ISD::UNPCKL : X86ISD::UNPCKH);<br>
+ if (Depth == 1 && Root->getOpcode() == Shuffle)<br>
+ return false; // Nothing to do!<br>
MVT ShuffleVT = FloatDomain ? MVT::v4f32 : MVT::v2i64;<br>
Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);<br>
DCI.AddToWorklist(Op.getNode());<br>
@@ -18757,16 +18775,18 @@ static bool combineX86ShuffleChain(SDVal<br>
Mask.equals(8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15,<br>
15))) {<br>
bool Lo = Mask[0] == 0;<br>
+ unsigned Shuffle = Lo ? X86ISD::UNPCKL : X86ISD::UNPCKH;<br>
+ if (Depth == 1 && Root->getOpcode() == Shuffle)<br>
+ return false; // Nothing to do!<br>
MVT ShuffleVT;<br>
switch (Mask.size()) {<br>
case 4: ShuffleVT = MVT::v4i32; break;<br>
- case 8: ShuffleVT = MVT::v8i32; break;<br>
- case 16: ShuffleVT = MVT::v16i32; break;<br>
+ case 8: ShuffleVT = MVT::v8i16; break;<br>
+ case 16: ShuffleVT = MVT::v16i8; break;<br>
};<br>
Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);<br>
DCI.AddToWorklist(Op.getNode());<br>
- Op = DAG.getNode(Lo ? X86ISD::UNPCKL : X86ISD::UNPCKH, DL, ShuffleVT, Op,<br>
- Op);<br>
+ Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);<br>
DCI.AddToWorklist(Op.getNode());<br>
DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),<br>
/*AddTo*/ true);<br>
<br>
Modified: llvm/trunk/test/CodeGen/X86/avx-basic.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx-basic.ll?rev=214625&r1=214624&r2=214625&view=diff" target="_blank">
http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx-basic.ll?rev=214625&r1=214624&r2=214625&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/X86/avx-basic.ll (original)<br>
+++ llvm/trunk/test/CodeGen/X86/avx-basic.ll Sat Aug 2 05:27:38 2014<br>
@@ -72,9 +72,9 @@ entry:<br>
ret <4 x i64> %shuffle<br>
}<br>
<br>
-; CHECK: movlhps<br>
+; CHECK: vpunpcklqdq<br>
; CHECK-NEXT: vextractf128 $1<br>
-; CHECK-NEXT: movlhps<br>
+; CHECK-NEXT: vpunpcklqdq<br>
; CHECK-NEXT: vinsertf128 $1<br>
define <4 x i64> @C(<4 x i64> %a, <4 x i64> %b) nounwind uwtable readnone ssp {<br>
entry:<br>
<br>
Modified: llvm/trunk/test/CodeGen/X86/avx-splat.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx-splat.ll?rev=214625&r1=214624&r2=214625&view=diff" target="_blank">
http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx-splat.ll?rev=214625&r1=214624&r2=214625&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/X86/avx-splat.ll (original)<br>
+++ llvm/trunk/test/CodeGen/X86/avx-splat.ll Sat Aug 2 05:27:38 2014<br>
@@ -1,9 +1,7 @@<br>
; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=corei7-avx -mattr=+avx | FileCheck %s<br>
<br>
<br>
-; CHECK: vpunpcklbw %xmm<br>
-; CHECK-NEXT: vpunpckhbw %xmm<br>
-; CHECK-NEXT: vpshufd $85<br>
+; CHECK: vpshufb {{.*}} ## xmm0 = xmm0[5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5]<br>
; CHECK-NEXT: vinsertf128 $1<br>
define <32 x i8> @funcA(<32 x i8> %a) nounwind uwtable readnone ssp {<br>
entry:<br>
@@ -21,7 +19,7 @@ entry:<br>
}<br>
<br>
; CHECK: vmovq<br>
-; CHECK-NEXT: vmovlhps %xmm<br>
+; CHECK-NEXT: vpunpcklqdq %xmm<br>
; CHECK-NEXT: vinsertf128 $1<br>
define <4 x i64> @funcC(i64 %q) nounwind uwtable readnone ssp {<br>
entry:<br>
<br>
Modified: llvm/trunk/test/CodeGen/X86/exedepsfix-broadcast.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/exedepsfix-broadcast.ll?rev=214625&r1=214624&r2=214625&view=diff" target="_blank">
http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/exedepsfix-broadcast.ll?rev=214625&r1=214624&r2=214625&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/X86/exedepsfix-broadcast.ll (original)<br>
+++ llvm/trunk/test/CodeGen/X86/exedepsfix-broadcast.ll Sat Aug 2<br>
+++ 05:27:38 2014<br>
@@ -93,10 +93,10 @@ define <4 x double> @ExeDepsFix_broadcas<br>
<br>
<br>
; CHECK-LABEL: ExeDepsFix_broadcastsd_inreg -; ExeDepsFix works top down, thus it coalesces vmovlhps domain with -; vandps and there is nothing more you can do to match vmaxpd.<br>
-; CHECK: vmovlhps<br>
-; CHECK: vandps<br>
+; ExeDepsFix works top down, thus it coalesces vpunpcklqdq domain with<br>
+; vpand and there is nothing more you can do to match vmaxpd.<br>
+; CHECK: vpunpcklqdq<br>
+; CHECK: vpand<br>
; CHECK: vmaxpd<br>
; CHECK: ret<br>
define <2 x double> @ExeDepsFix_broadcastsd_inreg(<2 x double> %arg, <2 x double> %arg2, i64 %broadcastvalue) {<br>
<br>
Modified: llvm/trunk/test/CodeGen/X86/vec_splat-3.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/vec_splat-3.ll?rev=214625&r1=214624&r2=214625&view=diff" target="_blank">
http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/vec_splat-3.ll?rev=214625&r1=214624&r2=214625&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/X86/vec_splat-3.ll (original)<br>
+++ llvm/trunk/test/CodeGen/X86/vec_splat-3.ll Sat Aug 2 05:27:38 2014<br>
@@ -75,9 +75,8 @@ define <16 x i8> @shuf_16i8_8(<16 x i8><br>
ret <16 x i8> %tmp6<br>
<br>
; CHECK-LABEL: shuf_16i8_8:<br>
-; CHECK: punpcklbw<br>
-; CHECK-NEXT: punpcklbw<br>
-; CHECK-NEXT: pshufd $0<br>
+; CHECK: pxor %[[X:xmm[0-9]+]], %[[X]]<br>
+; CHECK-NEXT: pshufb %[[X]], %xmm0<br>
}<br>
<br>
define <16 x i8> @shuf_16i8_9(<16 x i8> %T0, <16 x i8> %T1) nounwind readnone { @@ -85,9 +84,7 @@ define <16 x i8> @shuf_16i8_9(<16 x i8><br>
ret <16 x i8> %tmp6<br>
<br>
; CHECK-LABEL: shuf_16i8_9:<br>
-; CHECK: punpcklbw<br>
-; CHECK-NEXT: punpcklbw<br>
-; CHECK-NEXT: pshufd $85<br>
+; CHECK: pshufb {{.*}} # xmm0 = xmm0[1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1]<br>
}<br>
<br>
define <16 x i8> @shuf_16i8_10(<16 x i8> %T0, <16 x i8> %T1) nounwind readnone { @@ -95,9 +92,7 @@ define <16 x i8> @shuf_16i8_10(<16 x i8><br>
ret <16 x i8> %tmp6<br>
<br>
; CHECK-LABEL: shuf_16i8_10:<br>
-; CHECK: punpcklbw<br>
-; CHECK-NEXT: punpcklbw<br>
-; CHECK-NEXT: pshufd $-86<br>
+; CHECK: pshufb {{.*}} # xmm0 = xmm0[2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2]<br>
}<br>
<br>
define <16 x i8> @shuf_16i8_11(<16 x i8> %T0, <16 x i8> %T1) nounwind readnone { @@ -105,9 +100,7 @@ define <16 x i8> @shuf_16i8_11(<16 x i8><br>
ret <16 x i8> %tmp6<br>
<br>
; CHECK-LABEL: shuf_16i8_11:<br>
-; CHECK: punpcklbw<br>
-; CHECK-NEXT: punpcklbw<br>
-; CHECK-NEXT: pshufd $-1<br>
+; CHECK: pshufb {{.*}} # xmm0 = xmm0[3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3]<br>
}<br>
<br>
<br>
@@ -124,9 +117,7 @@ define <16 x i8> @shuf_16i8_13(<16 x i8><br>
ret <16 x i8> %tmp6<br>
<br>
; CHECK-LABEL: shuf_16i8_13:<br>
-; CHECK: punpcklbw<br>
-; CHECK-NEXT: punpckhbw<br>
-; CHECK-NEXT: pshufd $85<br>
+; CHECK: pshufb {{.*}} # xmm0 = xmm0[5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5]<br>
}<br>
<br>
define <16 x i8> @shuf_16i8_14(<16 x i8> %T0, <16 x i8> %T1) nounwind readnone { @@ -134,9 +125,7 @@ define <16 x i8> @shuf_16i8_14(<16 x i8><br>
ret <16 x i8> %tmp6<br>
<br>
; CHECK-LABEL: shuf_16i8_14:<br>
-; CHECK: punpcklbw<br>
-; CHECK-NEXT: punpckhbw<br>
-; CHECK-NEXT: pshufd $-86<br>
+; CHECK: pshufb {{.*}} # xmm0 = xmm0[6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6]<br>
}<br>
<br>
define <16 x i8> @shuf_16i8_15(<16 x i8> %T0, <16 x i8> %T1) nounwind readnone { @@ -144,9 +133,7 @@ define <16 x i8> @shuf_16i8_15(<16 x i8><br>
ret <16 x i8> %tmp6<br>
<br>
; CHECK-LABEL: shuf_16i8_15:<br>
-; CHECK: punpcklbw<br>
-; CHECK-NEXT: punpckhbw<br>
-; CHECK-NEXT: pshufd $-1<br>
+; CHECK: pshufb {{.*}} # xmm0 = xmm0[7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7]<br>
}<br>
<br>
define <16 x i8> @shuf_16i8_16(<16 x i8> %T0, <16 x i8> %T1) nounwind readnone { @@ -154,9 +141,7 @@ define <16 x i8> @shuf_16i8_16(<16 x i8><br>
ret <16 x i8> %tmp6<br>
<br>
; CHECK-LABEL: shuf_16i8_16:<br>
-; CHECK: punpckhbw<br>
-; CHECK-NEXT: punpcklbw<br>
-; CHECK-NEXT: pshufd $0<br>
+; CHECK: pshufb {{.*}} # xmm0 = xmm0[8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8]<br>
}<br>
<br>
define <16 x i8> @shuf_16i8_17(<16 x i8> %T0, <16 x i8> %T1) nounwind readnone { @@ -164,9 +149,7 @@ define <16 x i8> @shuf_16i8_17(<16 x i8><br>
ret <16 x i8> %tmp6<br>
<br>
; CHECK-LABEL: shuf_16i8_17:<br>
-; CHECK: punpckhbw<br>
-; CHECK-NEXT: punpcklbw<br>
-; CHECK-NEXT: pshufd $85<br>
+; CHECK: pshufb {{.*}} # xmm0 = xmm0[9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9]<br>
}<br>
<br>
define <16 x i8> @shuf_16i8_18(<16 x i8> %T0, <16 x i8> %T1) nounwind readnone { @@ -174,9 +157,7 @@ define <16 x i8> @shuf_16i8_18(<16 x i8><br>
ret <16 x i8> %tmp6<br>
<br>
; CHECK-LABEL: shuf_16i8_18:<br>
-; CHECK: punpckhbw<br>
-; CHECK-NEXT: punpcklbw<br>
-; CHECK-NEXT: pshufd $-86<br>
+; CHECK: pshufb {{.*}} # xmm0 =<br>
+xmm0[10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10]<br>
}<br>
<br>
define <16 x i8> @shuf_16i8_19(<16 x i8> %T0, <16 x i8> %T1) nounwind readnone { @@ -184,9 +165,7 @@ define <16 x i8> @shuf_16i8_19(<16 x i8><br>
ret <16 x i8> %tmp6<br>
<br>
; CHECK-LABEL: shuf_16i8_19:<br>
-; CHECK: punpckhbw<br>
-; CHECK-NEXT: punpcklbw<br>
-; CHECK-NEXT: pshufd $-1<br>
+; CHECK: pshufb {{.*}} # xmm0 =<br>
+xmm0[11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11]<br>
}<br>
<br>
define <16 x i8> @shuf_16i8_20(<16 x i8> %T0, <16 x i8> %T1) nounwind readnone { @@ -194,9 +173,7 @@ define <16 x i8> @shuf_16i8_20(<16 x i8><br>
ret <16 x i8> %tmp6<br>
<br>
; CHECK-LABEL: shuf_16i8_20:<br>
-; CHECK: punpckhbw<br>
-; CHECK-NEXT: punpckhbw<br>
-; CHECK-NEXT: pshufd $0<br>
+; CHECK: pshufb {{.*}} # xmm0 =<br>
+xmm0[12,12,12,12,12,12,12,12,12,12,12,12,12,12,12,12]<br>
}<br>
<br>
define <16 x i8> @shuf_16i8_21(<16 x i8> %T0, <16 x i8> %T1) nounwind readnone { @@ -204,9 +181,7 @@ define <16 x i8> @shuf_16i8_21(<16 x i8><br>
ret <16 x i8> %tmp6<br>
<br>
; CHECK-LABEL: shuf_16i8_21:<br>
-; CHECK: punpckhbw<br>
-; CHECK-NEXT: punpckhbw<br>
-; CHECK-NEXT: pshufd $85<br>
+; CHECK: pshufb {{.*}} # xmm0 =<br>
+xmm0[13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13]<br>
}<br>
<br>
define <16 x i8> @shuf_16i8_22(<16 x i8> %T0, <16 x i8> %T1) nounwind readnone { @@ -214,9 +189,7 @@ define <16 x i8> @shuf_16i8_22(<16 x i8><br>
ret <16 x i8> %tmp6<br>
<br>
; CHECK-LABEL: shuf_16i8_22:<br>
-; CHECK: punpckhbw<br>
-; CHECK-NEXT: punpckhbw<br>
-; CHECK-NEXT: pshufd $-86<br>
+; CHECK: pshufb {{.*}} # xmm0 =<br>
+xmm0[14,14,14,14,14,14,14,14,14,14,14,14,14,14,14,14]<br>
}<br>
<br>
define <16 x i8> @shuf_16i8_23(<16 x i8> %T0, <16 x i8> %T1) nounwind readnone { @@ -224,7 +197,5 @@ define <16 x i8> @shuf_16i8_23(<16 x i8><br>
ret <16 x i8> %tmp6<br>
<br>
; CHECK-LABEL: shuf_16i8_23:<br>
-; CHECK: punpckhbw<br>
-; CHECK-NEXT: punpckhbw<br>
-; CHECK-NEXT: pshufd $-1<br>
+; CHECK: pshufb {{.*}} # xmm0 =<br>
+xmm0[15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15]<br>
}<br>
<br>
<br>
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