<div dir="ltr">Thanks! Fixed in r214785. I'll try hitting llvm-stress myself some... Do you have convenient scripts for fuzzing with it?</div><div class="gmail_extra"><br><br><div class="gmail_quote">On Mon, Aug 4, 2014 at 12:26 AM, Patrik Hägglund H <span dir="ltr"><<a href="mailto:patrik.h.hagglund@ericsson.com" target="_blank">patrik.h.hagglund@ericsson.com</a>></span> wrote:<br>
<blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">Hi Chandler,<br>
<br>
This commit is causing a regression, shown by llvm-stress:<br>
<br>
bin/llvm-stress -size 300 -seed 10891 | bin/llc -march=x86-64 -mcpu=corei7 -o /dev/null<br>
llc: ../include/llvm/CodeGen/SelectionDAG.h:706: llvm::SDValue llvm::SelectionDAG::getSelect(llvm::SDLoc, llvm::EVT, llvm::SDValue, llvm::SDValue, llvm::SDValue): Assertion `LHS.getValueType() == RHS.getValueType() && "Cannot use select on differing types"' failed.<br>
0 llc 0x00000000011ed4e5 llvm::sys::PrintStackTrace(_IO_FILE*) + 37<br>
1 llc 0x00000000011ed923<br>
2 libpthread.so.0 0x00007f7ef96287c0<br>
3 libc.so.6 0x00007f7ef892cb35 gsignal + 53<br>
4 libc.so.6 0x00007f7ef892e111 abort + 385<br>
5 libc.so.6 0x00007f7ef89259f0 __assert_fail + 240<br>
6 llc 0x00000000005fa0e4<br>
7 llc 0x0000000000ffadc8<br>
8 llc 0x0000000000fe0fac<br>
9 llc 0x0000000000fe068e llvm::SelectionDAG::Combine(llvm::CombineLevel, llvm::AliasAnalysis&, llvm::CodeGenOpt::Level) + 1070<br>
10 llc 0x00000000010d666e llvm::SelectionDAGISel::CodeGenAndEmitDAG() + 910<br>
11 llc 0x00000000010d58a8 llvm::SelectionDAGISel::SelectAllBasicBlocks(llvm::Function const&) + 7096<br>
12 llc 0x00000000010d2f54 llvm::SelectionDAGISel::runOnMachineFunction(llvm::MachineFunction&) + 1332<br>
13 llc 0x0000000000ae7b16<br>
14 llc 0x0000000000ceea8c llvm::MachineFunctionPass::runOnFunction(llvm::Function&) + 124<br>
15 llc 0x0000000000eef2ea llvm::FPPassManager::runOnFunction(llvm::Function&) + 362<br>
16 llc 0x0000000000eef57b llvm::FPPassManager::runOnModule(llvm::Module&) + 43<br>
17 llc 0x0000000000eefb17 llvm::legacy::PassManagerImpl::run(llvm::Module&) + 999<br>
18 llc 0x00000000005730bd main + 6749<br>
19 libc.so.6 0x00007f7ef8918c16 __libc_start_main + 230<br>
20 llc 0x0000000000571579<br>
Stack dump:<br>
0. Program arguments: bin/llc -march=x86-64 -mcpu=corei7 -o /dev/null<br>
1. Running pass 'Function Pass Manager' on module '<stdin>'.<br>
2. Running pass 'X86 DAG->DAG Instruction Selection' on function '@autogen_SD10891'<br>
Abort<br>
<span class="HOEnZb"><font color="#888888"><br>
/Patrik Hägglund<br>
</font></span><div class="HOEnZb"><div class="h5"><br>
-----Original Message-----<br>
From: <a href="mailto:llvm-commits-bounces@cs.uiuc.edu">llvm-commits-bounces@cs.uiuc.edu</a> [mailto:<a href="mailto:llvm-commits-bounces@cs.uiuc.edu">llvm-commits-bounces@cs.uiuc.edu</a>] On Behalf Of Chandler Carruth<br>
Sent: den 23 juli 2014 09:09<br>
To: <a href="mailto:llvm-commits@cs.uiuc.edu">llvm-commits@cs.uiuc.edu</a><br>
Subject: [llvm] r213727 - [SDAG] Make the DAGCombine worklist not grow endlessly due to duplicate<br>
<br>
Author: chandlerc<br>
Date: Wed Jul 23 02:08:53 2014<br>
New Revision: 213727<br>
<br>
URL: <a href="http://llvm.org/viewvc/llvm-project?rev=213727&view=rev" target="_blank">http://llvm.org/viewvc/llvm-project?rev=213727&view=rev</a><br>
Log:<br>
[SDAG] Make the DAGCombine worklist not grow endlessly due to duplicate<br>
insertions.<br>
<br>
The old behavior could cause arbitrarily bad memory usage in the DAG<br>
combiner if there was heavy traffic of adding nodes already on the<br>
worklist to it. This commit switches the DAG combine worklist to work<br>
the same way as the instcombine worklist where we null-out removed<br>
entries and only add new entries to the worklist. My measurements of<br>
codegen time shows slight improvement. The memory utilization is<br>
unsurprisingly dominated by other factors (the IR and DAG itself<br>
I suspect).<br>
<br>
This change results in subtle, frustrating churn in the particular order<br>
in which DAG combines are applied which causes a number of minor<br>
regressions where we fail to match a pattern previously matched by<br>
accident. AFAICT, all of these should be using AddToWorklist to directly<br>
or should be written in a less brittle way. None of the changes seem<br>
drastically bad, and a few of the changes seem distinctly better.<br>
<br>
A major change required to make this work is to significantly harden the<br>
way in which the DAG combiner handle nodes which become dead<br>
(zero-uses). Previously, we relied on the ability to "priority-bump"<br>
them on the combine worklist to achieve recursive deletion of these<br>
nodes and ensure that the frontier of remaining live nodes all were<br>
added to the worklist. Instead, I've introduced a routine to just<br>
implement that precise logic with no indirection. It is a significantly<br>
simpler operation than that of the combiner worklist proper. I suspect<br>
this will also fix some other problems with the combiner.<br>
<br>
I think the x86 changes are really minor and uninteresting, but the<br>
avx512 change at least is hiding a "regression" (despite the test case<br>
being just noise, not testing some performance invariant) that might be<br>
looked into. Not sure if any of the others impact specific "important"<br>
code paths, but they didn't look terribly interesting to me, or the<br>
changes were really minor. The consensus in review is to fix any<br>
regressions that show up after the fact here.<br>
<br>
Thanks to the other reviewers for checking the output on other<br>
architectures. There is a specific regression on ARM that Tim already<br>
has a fix prepped to commit.<br>
<br>
Differential Revision: <a href="http://reviews.llvm.org/D4616" target="_blank">http://reviews.llvm.org/D4616</a><br>
<br>
Removed:<br>
llvm/trunk/test/CodeGen/X86/avx512-zext-load-crash.ll<br>
llvm/trunk/test/CodeGen/X86/fold-pcmpeqd-0.ll<br>
Modified:<br>
llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp<br>
llvm/trunk/test/CodeGen/ARM/fold-stack-adjust.ll<br>
llvm/trunk/test/CodeGen/ARM/sxt_rot.ll<br>
llvm/trunk/test/CodeGen/PowerPC/complex-return.ll<br>
llvm/trunk/test/CodeGen/PowerPC/subsumes-pred-regs.ll<br>
llvm/trunk/test/CodeGen/R600/r600-export-fix.ll<br>
llvm/trunk/test/CodeGen/R600/swizzle-export.ll<br>
llvm/trunk/test/CodeGen/Thumb2/thumb2-sxt_rot.ll<br>
llvm/trunk/test/CodeGen/Thumb2/thumb2-uxt_rot.ll<br>
llvm/trunk/test/CodeGen/X86/block-placement.ll<br>
llvm/trunk/test/CodeGen/X86/divide-by-constant.ll<br>
llvm/trunk/test/CodeGen/X86/narrow-shl-load.ll<br>
llvm/trunk/test/CodeGen/X86/store-narrow.ll<br>
llvm/trunk/test/CodeGen/X86/vec_extract-sse4.ll<br>
<br>
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=213727&r1=213726&r2=213727&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=213727&r1=213726&r2=213727&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original)<br>
+++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Wed Jul 23 02:08:53 2014<br>
@@ -18,6 +18,7 @@<br>
<br>
#include "llvm/CodeGen/SelectionDAG.h"<br>
#include "llvm/ADT/SmallPtrSet.h"<br>
+#include "llvm/ADT/SetVector.h"<br>
#include "llvm/ADT/Statistic.h"<br>
#include "llvm/Analysis/AliasAnalysis.h"<br>
#include "llvm/CodeGen/MachineFrameInfo.h"<br>
@@ -87,25 +88,21 @@ namespace {<br>
bool LegalTypes;<br>
bool ForCodeSize;<br>
<br>
- // Worklist of all of the nodes that need to be simplified.<br>
- //<br>
- // This has the semantics that when adding to the worklist,<br>
- // the item added must be next to be processed. It should<br>
- // also only appear once. The naive approach to this takes<br>
- // linear time.<br>
- //<br>
- // To reduce the insert/remove time to logarithmic, we use<br>
- // a set and a vector to maintain our worklist.<br>
- //<br>
- // The set contains the items on the worklist, but does not<br>
- // maintain the order they should be visited.<br>
- //<br>
- // The vector maintains the order nodes should be visited, but may<br>
- // contain duplicate or removed nodes. When choosing a node to<br>
- // visit, we pop off the order stack until we find an item that is<br>
- // also in the contents set. All operations are O(log N).<br>
- SmallPtrSet<SDNode*, 64> WorklistContents;<br>
- SmallVector<SDNode*, 64> WorklistOrder;<br>
+ /// \brief Worklist of all of the nodes that need to be simplified.<br>
+ ///<br>
+ /// This must behave as a stack -- new nodes to process are pushed onto the<br>
+ /// back and when processing we pop off of the back.<br>
+ ///<br>
+ /// The worklist will not contain duplicates but may contain null entries<br>
+ /// due to nodes being deleted from the underlying DAG.<br>
+ SmallVector<SDNode *, 64> Worklist;<br>
+<br>
+ /// \brief Mapping from an SDNode to its position on the worklist.<br>
+ ///<br>
+ /// This is used to find and remove nodes from the worklist (by nulling<br>
+ /// them) when they are deleted from the underlying DAG. It relies on<br>
+ /// stable indices of nodes within the worklist.<br>
+ DenseMap<SDNode *, unsigned> WorklistMap;<br>
<br>
// AA - Used for DAG load/store alias analysis.<br>
AliasAnalysis &AA;<br>
@@ -132,16 +129,24 @@ namespace {<br>
if (N->getOpcode() == ISD::HANDLENODE)<br>
return;<br>
<br>
- WorklistContents.insert(N);<br>
- WorklistOrder.push_back(N);<br>
+ if (WorklistMap.insert(std::make_pair(N, Worklist.size())).second)<br>
+ Worklist.push_back(N);<br>
}<br>
<br>
/// removeFromWorklist - remove all instances of N from the worklist.<br>
///<br>
void removeFromWorklist(SDNode *N) {<br>
- WorklistContents.erase(N);<br>
+ auto It = WorklistMap.find(N);<br>
+ if (It == WorklistMap.end())<br>
+ return; // Not in the worklist.<br>
+<br>
+ // Null out the entry rather than erasing it to avoid a linear operation.<br>
+ Worklist[It->second] = nullptr;<br>
+ WorklistMap.erase(It);<br>
}<br>
<br>
+ bool recursivelyDeleteUnusedNodes(SDNode *N);<br>
+<br>
SDValue CombineTo(SDNode *N, const SDValue *To, unsigned NumTo,<br>
bool AddTo = true);<br>
<br>
@@ -1072,6 +1077,35 @@ bool DAGCombiner::PromoteLoad(SDValue Op<br>
return false;<br>
}<br>
<br>
+/// \brief Recursively delete a node which has no uses and any operands for<br>
+/// which it is the only use.<br>
+///<br>
+/// Note that this both deletes the nodes and removes them from the worklist.<br>
+/// It also adds any nodes who have had a user deleted to the worklist as they<br>
+/// may now have only one use and subject to other combines.<br>
+bool DAGCombiner::recursivelyDeleteUnusedNodes(SDNode *N) {<br>
+ if (!N->use_empty())<br>
+ return false;<br>
+<br>
+ SmallSetVector<SDNode *, 16> Nodes;<br>
+ Nodes.insert(N);<br>
+ do {<br>
+ N = Nodes.pop_back_val();<br>
+ if (!N)<br>
+ continue;<br>
+<br>
+ if (N->use_empty()) {<br>
+ for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)<br>
+ Nodes.insert(N->getOperand(i).getNode());<br>
+<br>
+ removeFromWorklist(N);<br>
+ DAG.DeleteNode(N);<br>
+ } else {<br>
+ AddToWorklist(N);<br>
+ }<br>
+ } while (!Nodes.empty());<br>
+ return true;<br>
+}<br>
<br>
//===----------------------------------------------------------------------===//<br>
// Main DAG Combiner implementation<br>
@@ -1099,27 +1133,25 @@ void DAGCombiner::Run(CombineLevel AtLev<br>
<br>
// while the worklist isn't empty, find a node and<br>
// try and combine it.<br>
- while (!WorklistContents.empty()) {<br>
+ while (!WorklistMap.empty()) {<br>
SDNode *N;<br>
- // The WorklistOrder holds the SDNodes in order, but it may contain<br>
- // duplicates.<br>
- // In order to avoid a linear scan, we use a set (O(log N)) to hold what the<br>
- // worklist *should* contain, and check the node we want to visit is should<br>
- // actually be visited.<br>
+ // The Worklist holds the SDNodes in order, but it may contain null entries.<br>
do {<br>
- N = WorklistOrder.pop_back_val();<br>
- } while (!WorklistContents.erase(N));<br>
+ N = Worklist.pop_back_val();<br>
+ } while (!N);<br>
+<br>
+ bool GoodWorklistEntry = WorklistMap.erase(N);<br>
+ (void)GoodWorklistEntry;<br>
+ assert(GoodWorklistEntry &&<br>
+ "Found a worklist entry without a corresponding map entry!");<br>
<br>
// If N has no uses, it is dead. Make sure to revisit all N's operands once<br>
// N is deleted from the DAG, since they too may now be dead or may have a<br>
// reduced number of uses, allowing other xforms.<br>
- if (N->use_empty()) {<br>
- for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)<br>
- AddToWorklist(N->getOperand(i).getNode());<br>
-<br>
- DAG.DeleteNode(N);<br>
+ if (recursivelyDeleteUnusedNodes(N))<br>
continue;<br>
- }<br>
+<br>
+ WorklistRemover DeadNodes(*this);<br>
<br>
SDValue RV = combine(N);<br>
<br>
@@ -1147,7 +1179,6 @@ void DAGCombiner::Run(CombineLevel AtLev<br>
<br>
// Transfer debug value.<br>
DAG.TransferDbgValues(SDValue(N, 0), RV);<br>
- WorklistRemover DeadNodes(*this);<br>
if (N->getNumValues() == RV.getNode()->getNumValues())<br>
DAG.ReplaceAllUsesWith(N, RV.getNode());<br>
else {<br>
@@ -1161,23 +1192,11 @@ void DAGCombiner::Run(CombineLevel AtLev<br>
AddToWorklist(RV.getNode());<br>
AddUsersToWorklist(RV.getNode());<br>
<br>
- // Add any uses of the old node to the worklist in case this node is the<br>
- // last one that uses them. They may become dead after this node is<br>
- // deleted.<br>
- for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)<br>
- AddToWorklist(N->getOperand(i).getNode());<br>
-<br>
// Finally, if the node is now dead, remove it from the graph. The node<br>
// may not be dead if the replacement process recursively simplified to<br>
- // something else needing this node.<br>
- if (N->use_empty()) {<br>
- // Nodes can be reintroduced into the worklist. Make sure we do not<br>
- // process a node that has been replaced.<br>
- removeFromWorklist(N);<br>
-<br>
- // Finally, since the node is now dead, remove it from the graph.<br>
- DAG.DeleteNode(N);<br>
- }<br>
+ // something else needing this node. This will also take care of adding any<br>
+ // operands which have lost a user to the worklist.<br>
+ recursivelyDeleteUnusedNodes(N);<br>
}<br>
<br>
// If the root changed (e.g. it was a dead load, update the root).<br>
<br>
Modified: llvm/trunk/test/CodeGen/ARM/fold-stack-adjust.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/fold-stack-adjust.ll?rev=213727&r1=213726&r2=213727&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/fold-stack-adjust.ll?rev=213727&r1=213726&r2=213727&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/ARM/fold-stack-adjust.ll (original)<br>
+++ llvm/trunk/test/CodeGen/ARM/fold-stack-adjust.ll Wed Jul 23 02:08:53 2014<br>
@@ -167,9 +167,9 @@ end:<br>
define void @test_varsize(...) minsize {<br>
; CHECK-T1-LABEL: test_varsize:<br>
; CHECK-T1: sub sp, #16<br>
-; CHECK-T1: push {r2, r3, r4, r5, r7, lr}<br>
+; CHECK-T1: push {r5, r6, r7, lr}<br>
; ...<br>
-; CHECK-T1: pop {r2, r3, r4, r5, r7}<br>
+; CHECK-T1: pop {r2, r3, r7}<br>
; CHECK-T1: pop {r3}<br>
; CHECK-T1: add sp, #16<br>
; CHECK-T1: bx r3<br>
<br>
Modified: llvm/trunk/test/CodeGen/ARM/sxt_rot.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/sxt_rot.ll?rev=213727&r1=213726&r2=213727&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/sxt_rot.ll?rev=213727&r1=213726&r2=213727&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/ARM/sxt_rot.ll (original)<br>
+++ llvm/trunk/test/CodeGen/ARM/sxt_rot.ll Wed Jul 23 02:08:53 2014<br>
@@ -9,7 +9,8 @@ define i32 @test0(i8 %A) {<br>
<br>
define signext i8 @test1(i32 %A) {<br>
; CHECK: test1<br>
-; CHECK: sxtb r0, r0, ror #8<br>
+; CHECK: lsr r0, r0, #8<br>
+; CHECK: sxtb r0, r0<br>
%B = lshr i32 %A, 8<br>
%C = shl i32 %A, 24<br>
%D = or i32 %B, %C<br>
<br>
Modified: llvm/trunk/test/CodeGen/PowerPC/complex-return.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/complex-return.ll?rev=213727&r1=213726&r2=213727&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/complex-return.ll?rev=213727&r1=213726&r2=213727&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/PowerPC/complex-return.ll (original)<br>
+++ llvm/trunk/test/CodeGen/PowerPC/complex-return.ll Wed Jul 23 02:08:53 2014<br>
@@ -24,10 +24,10 @@ entry:<br>
}<br>
<br>
; CHECK-LABEL: foo:<br>
-; CHECK: lfd 3<br>
-; CHECK: lfd 4<br>
; CHECK: lfd 1<br>
; CHECK: lfd 2<br>
+; CHECK: lfd 3<br>
+; CHECK: lfd 4<br>
<br>
define { float, float } @oof() nounwind {<br>
entry:<br>
<br>
Modified: llvm/trunk/test/CodeGen/PowerPC/subsumes-pred-regs.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/subsumes-pred-regs.ll?rev=213727&r1=213726&r2=213727&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/subsumes-pred-regs.ll?rev=213727&r1=213726&r2=213727&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/PowerPC/subsumes-pred-regs.ll (original)<br>
+++ llvm/trunk/test/CodeGen/PowerPC/subsumes-pred-regs.ll Wed Jul 23 02:08:53 2014<br>
@@ -35,7 +35,7 @@ if.then9.i39:<br>
br i1 %lnot.i.i16.i23, label %return, label %lor.rhs.i.i49<br>
<br>
; CHECK: .LBB0_7:<br>
-; CHECK: beq 1, .LBB0_10<br>
+; CHECK: bne 1, .LBB0_10<br>
; CHECK: beq 0, .LBB0_10<br>
; CHECK: .LBB0_9:<br>
<br>
<br>
Modified: llvm/trunk/test/CodeGen/R600/r600-export-fix.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/r600-export-fix.ll?rev=213727&r1=213726&r2=213727&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/r600-export-fix.ll?rev=213727&r1=213726&r2=213727&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/R600/r600-export-fix.ll (original)<br>
+++ llvm/trunk/test/CodeGen/R600/r600-export-fix.ll Wed Jul 23 02:08:53 2014<br>
@@ -3,9 +3,9 @@<br>
;CHECK: EXPORT T{{[0-9]}}.XYZW<br>
;CHECK: EXPORT T{{[0-9]}}.0000<br>
;CHECK: EXPORT T{{[0-9]}}.0000<br>
-;CHECK: EXPORT T{{[0-9]}}.0XZW<br>
+;CHECK: EXPORT T{{[0-9]}}.0XYZ<br>
;CHECK: EXPORT T{{[0-9]}}.XYZW<br>
-;CHECK: EXPORT T{{[0-9]}}.YX00<br>
+;CHECK: EXPORT T{{[0-9]}}.YZ00<br>
;CHECK: EXPORT T{{[0-9]}}.0000<br>
;CHECK: EXPORT T{{[0-9]}}.0000<br>
<br>
<br>
Modified: llvm/trunk/test/CodeGen/R600/swizzle-export.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/swizzle-export.ll?rev=213727&r1=213726&r2=213727&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/swizzle-export.ll?rev=213727&r1=213726&r2=213727&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/R600/swizzle-export.ll (original)<br>
+++ llvm/trunk/test/CodeGen/R600/swizzle-export.ll Wed Jul 23 02:08:53 2014<br>
@@ -94,7 +94,7 @@ main_body:<br>
<br>
; EG-CHECK: @main2<br>
; EG-CHECK: T{{[0-9]+}}.XY__<br>
-; EG-CHECK: T{{[0-9]+}}.YXZ0<br>
+; EG-CHECK: T{{[0-9]+}}.ZXY0<br>
<br>
define void @main2(<4 x float> inreg %reg0, <4 x float> inreg %reg1) #0 {<br>
main_body:<br>
<br>
Modified: llvm/trunk/test/CodeGen/Thumb2/thumb2-sxt_rot.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/thumb2-sxt_rot.ll?rev=213727&r1=213726&r2=213727&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/thumb2-sxt_rot.ll?rev=213727&r1=213726&r2=213727&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/Thumb2/thumb2-sxt_rot.ll (original)<br>
+++ llvm/trunk/test/CodeGen/Thumb2/thumb2-sxt_rot.ll Wed Jul 23 02:08:53 2014<br>
@@ -10,7 +10,8 @@ define i32 @test0(i8 %A) {<br>
<br>
define signext i8 @test1(i32 %A) {<br>
; CHECK: test1<br>
-; CHECK: sxtb.w r0, r0, ror #8<br>
+; CHECK: lsrs r0, r0, #8<br>
+; CHECK: sxtb r0, r0<br>
%B = lshr i32 %A, 8<br>
%C = shl i32 %A, 24<br>
%D = or i32 %B, %C<br>
<br>
Modified: llvm/trunk/test/CodeGen/Thumb2/thumb2-uxt_rot.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/thumb2-uxt_rot.ll?rev=213727&r1=213726&r2=213727&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/thumb2-uxt_rot.ll?rev=213727&r1=213726&r2=213727&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/Thumb2/thumb2-uxt_rot.ll (original)<br>
+++ llvm/trunk/test/CodeGen/Thumb2/thumb2-uxt_rot.ll Wed Jul 23 02:08:53 2014<br>
@@ -25,7 +25,7 @@ define zeroext i32 @test2(i32 %A.u, i32<br>
<br>
define zeroext i32 @test3(i32 %A.u) {<br>
; A8: test3<br>
-; A8: uxth.w r0, r0, ror #8<br>
+; A8: ubfx r0, r0, #8, #16<br>
%B.u = lshr i32 %A.u, 8<br>
%C.u = shl i32 %A.u, 24<br>
%D.u = or i32 %B.u, %C.u<br>
<br>
Removed: llvm/trunk/test/CodeGen/X86/avx512-zext-load-crash.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx512-zext-load-crash.ll?rev=213726&view=auto" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx512-zext-load-crash.ll?rev=213726&view=auto</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/X86/avx512-zext-load-crash.ll (original)<br>
+++ llvm/trunk/test/CodeGen/X86/avx512-zext-load-crash.ll (removed)<br>
@@ -1,14 +0,0 @@<br>
-; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=knl | FileCheck %s<br>
-<br>
-define <8 x i16> @test_zext_load() {<br>
- ; CHECK: vmovq<br>
-entry:<br>
- %0 = load <2 x i16> ** undef, align 8<br>
- %1 = getelementptr inbounds <2 x i16>* %0, i64 1<br>
- %2 = load <2 x i16>* %0, align 1<br>
- %3 = shufflevector <2 x i16> %2, <2 x i16> undef, <8 x i32> <i32 0, i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef><br>
- %4 = load <2 x i16>* %1, align 1<br>
- %5 = shufflevector <2 x i16> %4, <2 x i16> undef, <8 x i32> <i32 0, i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef><br>
- %6 = shufflevector <8 x i16> %3, <8 x i16> %5, <8 x i32> <i32 0, i32 1, i32 8, i32 9, i32 undef, i32 undef, i32 undef, i32 undef><br>
- ret <8 x i16> %6<br>
-}<br>
<br>
Modified: llvm/trunk/test/CodeGen/X86/block-placement.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/block-placement.ll?rev=213727&r1=213726&r2=213727&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/block-placement.ll?rev=213727&r1=213726&r2=213727&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/X86/block-placement.ll (original)<br>
+++ llvm/trunk/test/CodeGen/X86/block-placement.ll Wed Jul 23 02:08:53 2014<br>
@@ -237,44 +237,6 @@ exit:<br>
ret i32 %base<br>
}<br>
<br>
-define void @test_loop_rotate_reversed_blocks() {<br>
-; This test case (greatly reduced from an Olden bencmark) ensures that the loop<br>
-; rotate implementation doesn't assume that loops are laid out in a particular<br>
-; order. The first loop will get split into two basic blocks, with the loop<br>
-; header coming after the loop latch.<br>
-;<br>
-; CHECK: test_loop_rotate_reversed_blocks<br>
-; CHECK: %entry<br>
-; Look for a jump into the middle of the loop, and no branches mid-way.<br>
-; CHECK: jmp<br>
-; CHECK: %loop1<br>
-; CHECK-NOT: j{{\w*}} .LBB{{.*}}<br>
-; CHECK: %loop1<br>
-; CHECK: je<br>
-<br>
-entry:<br>
- %cond1 = load volatile i1* undef<br>
- br i1 %cond1, label %loop2.preheader, label %loop1<br>
-<br>
-loop1:<br>
- call i32 @f()<br>
- %cond2 = load volatile i1* undef<br>
- br i1 %cond2, label %loop2.preheader, label %loop1<br>
-<br>
-loop2.preheader:<br>
- call i32 @f()<br>
- %cond3 = load volatile i1* undef<br>
- br i1 %cond3, label %exit, label %loop2<br>
-<br>
-loop2:<br>
- call i32 @f()<br>
- %cond4 = load volatile i1* undef<br>
- br i1 %cond4, label %exit, label %loop2<br>
-<br>
-exit:<br>
- ret void<br>
-}<br>
-<br>
define i32 @test_loop_align(i32 %i, i32* %a) {<br>
; Check that we provide basic loop body alignment with the block placement<br>
; pass.<br>
<br>
Modified: llvm/trunk/test/CodeGen/X86/divide-by-constant.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/divide-by-constant.ll?rev=213727&r1=213726&r2=213727&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/divide-by-constant.ll?rev=213727&r1=213726&r2=213727&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/X86/divide-by-constant.ll (original)<br>
+++ llvm/trunk/test/CodeGen/X86/divide-by-constant.ll Wed Jul 23 02:08:53 2014<br>
@@ -31,6 +31,7 @@ entry:<br>
; CHECK-LABEL: test3:<br>
; CHECK: movzbl 8(%esp), %eax<br>
; CHECK-NEXT: imull $171, %eax<br>
+; CHECK-NEXT: andl $65024, %eax<br>
; CHECK-NEXT: shrl $9, %eax<br>
; CHECK-NEXT: ret<br>
}<br>
@@ -56,9 +57,10 @@ entry:<br>
%div = sdiv i16 %x, 10<br>
ret i16 %div<br>
; CHECK-LABEL: test6:<br>
-; CHECK: imull $26215, %eax, %ecx<br>
-; CHECK: sarl $18, %ecx<br>
-; CHECK: shrl $15, %eax<br>
+; CHECK: imull $26215, %eax<br>
+; CHECK: movl %eax, %ecx<br>
+; CHECK: shrl $31, %ecx<br>
+; CHECK: sarl $18, %eax<br>
}<br>
<br>
define i32 @test7(i32 %x) nounwind {<br>
<br>
Removed: llvm/trunk/test/CodeGen/X86/fold-pcmpeqd-0.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/fold-pcmpeqd-0.ll?rev=213726&view=auto" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/fold-pcmpeqd-0.ll?rev=213726&view=auto</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/X86/fold-pcmpeqd-0.ll (original)<br>
+++ llvm/trunk/test/CodeGen/X86/fold-pcmpeqd-0.ll (removed)<br>
@@ -1,117 +0,0 @@<br>
-; RUN: llc < %s -mtriple=x86_64-apple-darwin | FileCheck --check-prefix=X86-64 %s<br>
-; DISABLED: llc < %s -mtriple=i386-apple-darwin -mcpu=yonah -regalloc=linearscan | FileCheck --check-prefix=I386 %s<br>
-<br>
-; i386 test has been disabled when scheduler 2-addr hack is disabled.<br>
-<br>
-; This testcase shouldn't need to spill the -1 value,<br>
-; so it should just use pcmpeqd to materialize an all-ones vector.<br>
-; For i386, cp load of -1 are folded.<br>
-<br>
-; With -regalloc=greedy, the live range is split before spilling, so the first<br>
-; pcmpeq doesn't get folded as a constant pool load.<br>
-<br>
-; I386-NOT: pcmpeqd<br>
-; I386: orps LCPI0_2, %xmm<br>
-; I386-NOT: pcmpeqd<br>
-; I386: orps LCPI0_2, %xmm<br>
-<br>
-; X86-64: pcmpeqd<br>
-; X86-64-NOT: pcmpeqd<br>
-<br>
- %struct.__ImageExecInfo = type <{ <4 x i32>, <4 x float>, <2 x i64>, i8*, i8*, i8*, i32, i32, i32, i32, i32 }><br>
- %struct._cl_image_format_t = type <{ i32, i32, i32 }><br>
- %struct._image2d_t = type <{ i8*, %struct._cl_image_format_t, i32, i32, i32, i32, i32, i32 }><br>
-<br>
-define void @program_1(%struct._image2d_t* %dest, %struct._image2d_t* %t0, <4 x float> %p0, <4 x float> %p1, <4 x float> %p4, <4 x float> %p5, <4 x float> %p6) nounwind {<br>
-entry:<br>
- %tmp3.i = load i32* null ; <i32> [#uses=1]<br>
- %cmp = icmp sgt i32 %tmp3.i, 200 ; <i1> [#uses=1]<br>
- br i1 %cmp, label %forcond, label %ifthen<br>
-<br>
-ifthen: ; preds = %entry<br>
- ret void<br>
-<br>
-forcond: ; preds = %entry<br>
- %tmp3.i536 = load i32* null ; <i32> [#uses=1]<br>
- %cmp12 = icmp slt i32 0, %tmp3.i536 ; <i1> [#uses=1]<br>
- br i1 %cmp12, label %forbody, label %afterfor<br>
-<br>
-forbody: ; preds = %forcond<br>
- %bitcast204.i313 = bitcast <4 x i32> zeroinitializer to <4 x float> ; <<4 x float>> [#uses=1]<br>
- %mul233 = fmul <4 x float> %bitcast204.i313, zeroinitializer ; <<4 x float>> [#uses=1]<br>
- %mul257 = fmul <4 x float> %mul233, zeroinitializer ; <<4 x float>> [#uses=1]<br>
- %mul275 = fmul <4 x float> %mul257, zeroinitializer ; <<4 x float>> [#uses=1]<br>
- %tmp51 = call <4 x float> @<a href="http://llvm.x86.sse.max.ps" target="_blank">llvm.x86.sse.max.ps</a>(<4 x float> %mul275, <4 x float> zeroinitializer) nounwind ; <<4 x float>> [#uses=1]<br>
- %bitcast198.i182 = bitcast <4 x float> zeroinitializer to <4 x i32> ; <<4 x i32>> [#uses=0]<br>
- %bitcast204.i185 = bitcast <4 x i32> zeroinitializer to <4 x float> ; <<4 x float>> [#uses=1]<br>
- %tmp69 = call <4 x i32> @llvm.x86.sse2.cvttps2dq(<4 x float> zeroinitializer) nounwind ; <<4 x i32>> [#uses=1]<br>
- %tmp70 = call <4 x float> @llvm.x86.sse2.cvtdq2ps(<4 x i32> %tmp69) nounwind ; <<4 x float>> [#uses=1]<br>
- %sub140.i78 = fsub <4 x float> zeroinitializer, %tmp70 ; <<4 x float>> [#uses=2]<br>
- %mul166.i86 = fmul <4 x float> zeroinitializer, %sub140.i78 ; <<4 x float>> [#uses=1]<br>
- %add167.i87 = fadd <4 x float> %mul166.i86, < float 0x3FE62ACB60000000, float 0x3FE62ACB60000000, float 0x3FE62ACB60000000, float 0x3FE62ACB60000000 > ; <<4 x float>> [#uses=1]<br>
- %mul171.i88 = fmul <4 x float> %add167.i87, %sub140.i78 ; <<4 x float>> [#uses=1]<br>
- %add172.i89 = fadd <4 x float> %mul171.i88, < float 0x3FF0000A40000000, float 0x3FF0000A40000000, float 0x3FF0000A40000000, float 0x3FF0000A40000000 > ; <<4 x float>> [#uses=1]<br>
- %bitcast176.i90 = bitcast <4 x float> %add172.i89 to <4 x i32> ; <<4 x i32>> [#uses=1]<br>
- %andnps178.i92 = and <4 x i32> %bitcast176.i90, zeroinitializer ; <<4 x i32>> [#uses=1]<br>
- %bitcast179.i93 = bitcast <4 x i32> %andnps178.i92 to <4 x float> ; <<4 x float>> [#uses=1]<br>
- %mul186.i96 = fmul <4 x float> %bitcast179.i93, zeroinitializer ; <<4 x float>> [#uses=1]<br>
- %bitcast190.i98 = bitcast <4 x float> %mul186.i96 to <4 x i32> ; <<4 x i32>> [#uses=1]<br>
- %andnps192.i100 = and <4 x i32> %bitcast190.i98, zeroinitializer ; <<4 x i32>> [#uses=1]<br>
- %xorps.i102 = xor <4 x i32> zeroinitializer, < i32 -1, i32 -1, i32 -1, i32 -1 > ; <<4 x i32>> [#uses=1]<br>
- %orps203.i103 = or <4 x i32> %andnps192.i100, %xorps.i102 ; <<4 x i32>> [#uses=1]<br>
- %bitcast204.i104 = bitcast <4 x i32> %orps203.i103 to <4 x float> ; <<4 x float>> [#uses=1]<br>
- %cmple.i = call <4 x float> @<a href="http://llvm.x86.sse.cmp.ps" target="_blank">llvm.x86.sse.cmp.ps</a>(<4 x float> zeroinitializer, <4 x float> %tmp51, i8 2) nounwind ; <<4 x float>> [#uses=1]<br>
- %tmp80 = call <4 x float> @llvm.x86.sse2.cvtdq2ps(<4 x i32> zeroinitializer) nounwind ; <<4 x float>> [#uses=1]<br>
- %sub140.i = fsub <4 x float> zeroinitializer, %tmp80 ; <<4 x float>> [#uses=1]<br>
- %bitcast148.i = bitcast <4 x float> zeroinitializer to <4 x i32> ; <<4 x i32>> [#uses=1]<br>
- %andnps150.i = and <4 x i32> %bitcast148.i, < i32 -2139095041, i32 -2139095041, i32 -2139095041, i32 -2139095041 > ; <<4 x i32>> [#uses=0]<br>
- %mul171.i = fmul <4 x float> zeroinitializer, %sub140.i ; <<4 x float>> [#uses=1]<br>
- %add172.i = fadd <4 x float> %mul171.i, < float 0x3FF0000A40000000, float 0x3FF0000A40000000, float 0x3FF0000A40000000, float 0x3FF0000A40000000 > ; <<4 x float>> [#uses=1]<br>
- %bitcast176.i = bitcast <4 x float> %add172.i to <4 x i32> ; <<4 x i32>> [#uses=1]<br>
- %andnps178.i = and <4 x i32> %bitcast176.i, zeroinitializer ; <<4 x i32>> [#uses=1]<br>
- %bitcast179.i = bitcast <4 x i32> %andnps178.i to <4 x float> ; <<4 x float>> [#uses=1]<br>
- %mul186.i = fmul <4 x float> %bitcast179.i, zeroinitializer ; <<4 x float>> [#uses=1]<br>
- %bitcast189.i = bitcast <4 x float> zeroinitializer to <4 x i32> ; <<4 x i32>> [#uses=0]<br>
- %bitcast190.i = bitcast <4 x float> %mul186.i to <4 x i32> ; <<4 x i32>> [#uses=1]<br>
- %andnps192.i = and <4 x i32> %bitcast190.i, zeroinitializer ; <<4 x i32>> [#uses=1]<br>
- %bitcast198.i = bitcast <4 x float> %cmple.i to <4 x i32> ; <<4 x i32>> [#uses=1]<br>
- %xorps.i = xor <4 x i32> %bitcast198.i, < i32 -1, i32 -1, i32 -1, i32 -1 > ; <<4 x i32>> [#uses=1]<br>
- %orps203.i = or <4 x i32> %andnps192.i, %xorps.i ; <<4 x i32>> [#uses=1]<br>
- %bitcast204.i = bitcast <4 x i32> %orps203.i to <4 x float> ; <<4 x float>> [#uses=1]<br>
- %mul307 = fmul <4 x float> %bitcast204.i185, zeroinitializer ; <<4 x float>> [#uses=1]<br>
- %mul310 = fmul <4 x float> %bitcast204.i104, zeroinitializer ; <<4 x float>> [#uses=2]<br>
- %mul313 = fmul <4 x float> %bitcast204.i, zeroinitializer ; <<4 x float>> [#uses=1]<br>
- %tmp82 = call <4 x float> @<a href="http://llvm.x86.sse.min.ps" target="_blank">llvm.x86.sse.min.ps</a>(<4 x float> %mul307, <4 x float> zeroinitializer) nounwind ; <<4 x float>> [#uses=1]<br>
- %bitcast11.i15 = bitcast <4 x float> %tmp82 to <4 x i32> ; <<4 x i32>> [#uses=1]<br>
- %andnps.i17 = and <4 x i32> %bitcast11.i15, zeroinitializer ; <<4 x i32>> [#uses=1]<br>
- %orps.i18 = or <4 x i32> %andnps.i17, zeroinitializer ; <<4 x i32>> [#uses=1]<br>
- %bitcast17.i19 = bitcast <4 x i32> %orps.i18 to <4 x float> ; <<4 x float>> [#uses=1]<br>
- %tmp83 = call <4 x float> @<a href="http://llvm.x86.sse.min.ps" target="_blank">llvm.x86.sse.min.ps</a>(<4 x float> %mul310, <4 x float> zeroinitializer) nounwind ; <<4 x float>> [#uses=1]<br>
- %bitcast.i3 = bitcast <4 x float> %mul310 to <4 x i32> ; <<4 x i32>> [#uses=1]<br>
- %bitcast6.i4 = bitcast <4 x float> zeroinitializer to <4 x i32> ; <<4 x i32>> [#uses=2]<br>
- %andps.i5 = and <4 x i32> %bitcast.i3, %bitcast6.i4 ; <<4 x i32>> [#uses=1]<br>
- %bitcast11.i6 = bitcast <4 x float> %tmp83 to <4 x i32> ; <<4 x i32>> [#uses=1]<br>
- %not.i7 = xor <4 x i32> %bitcast6.i4, < i32 -1, i32 -1, i32 -1, i32 -1 > ; <<4 x i32>> [#uses=1]<br>
- %andnps.i8 = and <4 x i32> %bitcast11.i6, %not.i7 ; <<4 x i32>> [#uses=1]<br>
- %orps.i9 = or <4 x i32> %andnps.i8, %andps.i5 ; <<4 x i32>> [#uses=1]<br>
- %bitcast17.i10 = bitcast <4 x i32> %orps.i9 to <4 x float> ; <<4 x float>> [#uses=1]<br>
- %bitcast.i = bitcast <4 x float> %mul313 to <4 x i32> ; <<4 x i32>> [#uses=1]<br>
- %andps.i = and <4 x i32> %bitcast.i, zeroinitializer ; <<4 x i32>> [#uses=1]<br>
- %orps.i = or <4 x i32> zeroinitializer, %andps.i ; <<4 x i32>> [#uses=1]<br>
- %bitcast17.i = bitcast <4 x i32> %orps.i to <4 x float> ; <<4 x float>> [#uses=1]<br>
- call void null(<4 x float> %bitcast17.i19, <4 x float> %bitcast17.i10, <4 x float> %bitcast17.i, <4 x float> zeroinitializer, %struct.__ImageExecInfo* null, <4 x i32> zeroinitializer) nounwind<br>
- unreachable<br>
-<br>
-afterfor: ; preds = %forcond<br>
- ret void<br>
-}<br>
-<br>
-declare <4 x float> @<a href="http://llvm.x86.sse.cmp.ps" target="_blank">llvm.x86.sse.cmp.ps</a>(<4 x float>, <4 x float>, i8) nounwind readnone<br>
-<br>
-declare <4 x float> @llvm.x86.sse2.cvtdq2ps(<4 x i32>) nounwind readnone<br>
-<br>
-declare <4 x i32> @llvm.x86.sse2.cvttps2dq(<4 x float>) nounwind readnone<br>
-<br>
-declare <4 x float> @<a href="http://llvm.x86.sse.max.ps" target="_blank">llvm.x86.sse.max.ps</a>(<4 x float>, <4 x float>) nounwind readnone<br>
-<br>
-declare <4 x float> @<a href="http://llvm.x86.sse.min.ps" target="_blank">llvm.x86.sse.min.ps</a>(<4 x float>, <4 x float>) nounwind readnone<br>
<br>
Modified: llvm/trunk/test/CodeGen/X86/narrow-shl-load.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/narrow-shl-load.ll?rev=213727&r1=213726&r2=213727&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/narrow-shl-load.ll?rev=213727&r1=213726&r2=213727&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/X86/narrow-shl-load.ll (original)<br>
+++ llvm/trunk/test/CodeGen/X86/narrow-shl-load.ll Wed Jul 23 02:08:53 2014<br>
@@ -30,40 +30,6 @@ while.end:<br>
ret void<br>
}<br>
<br>
-<br>
-; DAGCombiner shouldn't fold the sdiv (ashr) away.<br>
-; rdar://8636812<br>
-; CHECK-LABEL: test2:<br>
-; CHECK: sarl<br>
-<br>
-define i32 @test2() nounwind {<br>
-entry:<br>
- %i = alloca i32, align 4<br>
- %j = alloca i8, align 1<br>
- store i32 127, i32* %i, align 4<br>
- store i8 0, i8* %j, align 1<br>
- %tmp3 = load i32* %i, align 4<br>
- %mul = mul nsw i32 %tmp3, 2<br>
- %conv4 = trunc i32 %mul to i8<br>
- %conv5 = sext i8 %conv4 to i32<br>
- %div6 = sdiv i32 %conv5, 2<br>
- %conv7 = trunc i32 %div6 to i8<br>
- %conv9 = sext i8 %conv7 to i32<br>
- %cmp = icmp eq i32 %conv9, -1<br>
- br i1 %cmp, label %if.then, label %if.end<br>
-<br>
-if.then: ; preds = %entry<br>
- ret i32 0<br>
-<br>
-if.end: ; preds = %entry<br>
- call void @abort() noreturn<br>
- unreachable<br>
-}<br>
-<br>
-declare void @abort() noreturn<br>
-<br>
-declare void @exit(i32) noreturn<br>
-<br>
; DAG Combiner can't fold this into a load of the 1'th byte.<br>
; PR8757<br>
define i32 @test3(i32 *%P) nounwind ssp {<br>
<br>
Modified: llvm/trunk/test/CodeGen/X86/store-narrow.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/store-narrow.ll?rev=213727&r1=213726&r2=213727&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/store-narrow.ll?rev=213727&r1=213726&r2=213727&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/X86/store-narrow.ll (original)<br>
+++ llvm/trunk/test/CodeGen/X86/store-narrow.ll Wed Jul 23 02:08:53 2014<br>
@@ -34,8 +34,8 @@ entry:<br>
; X64: movb %sil, 1(%rdi)<br>
<br>
; X32-LABEL: test2:<br>
-; X32: movb 8(%esp), %[[REG:[abcd]l]]<br>
-; X32: movb %[[REG]], 1(%{{.*}})<br>
+; X32: movzbl 8(%esp), %e[[REG:[abcd]]]x<br>
+; X32: movb %[[REG]]l, 1(%{{.*}})<br>
}<br>
<br>
define void @test3(i32* nocapture %a0, i16 zeroext %a1) nounwind ssp {<br>
<br>
Modified: llvm/trunk/test/CodeGen/X86/vec_extract-sse4.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/vec_extract-sse4.ll?rev=213727&r1=213726&r2=213727&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/vec_extract-sse4.ll?rev=213727&r1=213726&r2=213727&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/X86/vec_extract-sse4.ll (original)<br>
+++ llvm/trunk/test/CodeGen/X86/vec_extract-sse4.ll Wed Jul 23 02:08:53 2014<br>
@@ -4,8 +4,8 @@ define void @t1(float* %R, <4 x float>*<br>
; CHECK-LABEL: @t1<br>
; CHECK: movl 4(%esp), %[[R0:e[abcd]x]]<br>
; CHECK-NEXT: movl 8(%esp), %[[R1:e[abcd]x]]<br>
-; CHECK-NEXT: movl 12(%[[R1]]), %[[R2:e[abcd]x]]<br>
-; CHECK-NEXT: movl %[[R2]], (%[[R0]])<br>
+; CHECK-NEXT: movss 12(%[[R1]]), %[[R2:xmm.*]]<br>
+; CHECK-NEXT: movss %[[R2]], (%[[R0]])<br>
; CHECK-NEXT: retl<br>
<br>
%X = load <4 x float>* %P1<br>
<br>
<br>
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</div></div></blockquote></div><br></div>