<div dir="ltr"><div class="gmail_extra"><div class="gmail_quote">On Wed, Jul 30, 2014 at 10:41 AM, Tom Stellard <span dir="ltr"><<a href="mailto:tom@stellard.net" target="_blank">tom@stellard.net</a>></span> wrote:<br>
<blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">On Wed, Jul 30, 2014 at 10:23:47AM -0400, Justin Holewinski wrote:<br>
> Ping?<br>
><br>
<br>
It looks like Bill is letting developers commit changes directly to<br>
the 3.5 branch once they have code owner approval. See:<br>
<a href="http://lists.cs.uiuc.edu/pipermail/llvmdev/2014-July/075191.html" target="_blank">http://lists.cs.uiuc.edu/pipermail/llvmdev/2014-July/075191.html</a></blockquote><div><br></div><div>Awesome, thanks!</div><div> </div>
<blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"><br>
<span class="HOEnZb"><font color="#888888"><br>
-Tom<br>
</font></span><div class="HOEnZb"><div class="h5"><br>
><br>
> On Fri, Jul 25, 2014 at 3:55 PM, Justin Holewinski <<br>
> <a href="mailto:justin.holewinski@gmail.com">justin.holewinski@gmail.com</a>> wrote:<br>
><br>
> > Ping. Can this and 213793 (fix a gcc compiler warning related to this<br>
> > change) be merged into the 3.5 branch? This is a regression that affects<br>
> > -O0 compilation. Thanks!<br>
> ><br>
> ><br>
> > On Wed, Jul 23, 2014 at 2:11 PM, Justin Holewinski <<a href="mailto:jholewinski@nvidia.com">jholewinski@nvidia.com</a><br>
> > > wrote:<br>
> ><br>
> >> Bill, can you please merge this into the 3.5 release branch?<br>
> >><br>
> >> On Wed, 2014-07-23 at 10:40 -0700, Justin Holewinski wrote:<br>
> >> > Author: jholewinski<br>
> >> > Date: Wed Jul 23 12:40:45 2014<br>
> >> > New Revision: 213773<br>
> >> ><br>
> >> > URL: <a href="http://llvm.org/viewvc/llvm-project?rev=213773&view=rev" target="_blank">http://llvm.org/viewvc/llvm-project?rev=213773&view=rev</a><br>
> >> > Log:<br>
> >> > [NVPTX] Make sure we do not generate MULWIDE ISD nodes when<br>
> >> optimizations are disabled<br>
> >> ><br>
> >> > With optimizations disabled, we disable the isel patterns for mul.wide;<br>
> >> but we<br>
> >> > were still generating MULWIDE ISD nodes. Now, we only try to generate<br>
> >> MULWIDE<br>
> >> > ISD nodes in DAGCombine if the optimization level is not zero.<br>
> >> ><br>
> >> > Modified:<br>
> >> > llvm/trunk/lib/Target/NVPTX/NVPTXISelLowering.cpp<br>
> >> > llvm/trunk/test/CodeGen/NVPTX/mulwide.ll<br>
> >> ><br>
> >> > Modified: llvm/trunk/lib/Target/NVPTX/NVPTXISelLowering.cpp<br>
> >> > URL:<br>
> >> <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/NVPTX/NVPTXISelLowering.cpp?rev=213773&r1=213772&r2=213773&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/NVPTX/NVPTXISelLowering.cpp?rev=213773&r1=213772&r2=213773&view=diff</a><br>
> >> ><br>
> >> ==============================================================================<br>
> >> > --- llvm/trunk/lib/Target/NVPTX/NVPTXISelLowering.cpp (original)<br>
> >> > +++ llvm/trunk/lib/Target/NVPTX/NVPTXISelLowering.cpp Wed Jul 23<br>
> >> 12:40:45 2014<br>
> >> > @@ -4213,8 +4213,7 @@ static SDValue PerformSHLCombine(SDNode<br>
> >> ><br>
> >> > SDValue NVPTXTargetLowering::PerformDAGCombine(SDNode *N,<br>
> >> > DAGCombinerInfo &DCI)<br>
> >> const {<br>
> >> > - // FIXME: Get this from the DAG somehow<br>
> >> > - CodeGenOpt::Level OptLevel = CodeGenOpt::Aggressive;<br>
> >> > + CodeGenOpt::Level OptLevel = getTargetMachine().getOptLevel();<br>
> >> > switch (N->getOpcode()) {<br>
> >> > default: break;<br>
> >> > case ISD::ADD:<br>
> >> ><br>
> >> > Modified: llvm/trunk/test/CodeGen/NVPTX/mulwide.ll<br>
> >> > URL:<br>
> >> <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/NVPTX/mulwide.ll?rev=213773&r1=213772&r2=213773&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/NVPTX/mulwide.ll?rev=213773&r1=213772&r2=213773&view=diff</a><br>
> >> ><br>
> >> ==============================================================================<br>
> >> > --- llvm/trunk/test/CodeGen/NVPTX/mulwide.ll (original)<br>
> >> > +++ llvm/trunk/test/CodeGen/NVPTX/mulwide.ll Wed Jul 23 12:40:45 2014<br>
> >> > @@ -1,35 +1,44 @@<br>
> >> > -; RUN: llc < %s -march=nvptx -mcpu=sm_20 | FileCheck %s<br>
> >> > +; RUN: llc < %s -march=nvptx -mcpu=sm_20 -O3 | FileCheck %s<br>
> >> --check-prefix=OPT<br>
> >> > +; RUN: llc < %s -march=nvptx -mcpu=sm_20 -O0 | FileCheck %s<br>
> >> --check-prefix=NOOPT<br>
> >> ><br>
> >> > -; CHECK: mulwide16<br>
> >> > +; OPT-LABEL: @mulwide16<br>
> >> > +; NOOPT-LABEL: @mulwide16<br>
> >> > define i32 @mulwide16(i16 %a, i16 %b) {<br>
> >> > -; CHECK: mul.wide.s16<br>
> >> > +; OPT: mul.wide.s16<br>
> >> > +; NOOPT: mul.lo.s32<br>
> >> > %val0 = sext i16 %a to i32<br>
> >> > %val1 = sext i16 %b to i32<br>
> >> > %val2 = mul i32 %val0, %val1<br>
> >> > ret i32 %val2<br>
> >> > }<br>
> >> ><br>
> >> > -; CHECK: mulwideu16<br>
> >> > +; OPT-LABEL: @mulwideu16<br>
> >> > +; NOOPT-LABEL: @mulwideu16<br>
> >> > define i32 @mulwideu16(i16 %a, i16 %b) {<br>
> >> > -; CHECK: mul.wide.u16<br>
> >> > +; OPT: mul.wide.u16<br>
> >> > +; NOOPT: mul.lo.s32<br>
> >> > %val0 = zext i16 %a to i32<br>
> >> > %val1 = zext i16 %b to i32<br>
> >> > %val2 = mul i32 %val0, %val1<br>
> >> > ret i32 %val2<br>
> >> > }<br>
> >> ><br>
> >> > -; CHECK: mulwide32<br>
> >> > +; OPT-LABEL: @mulwide32<br>
> >> > +; NOOPT-LABEL: @mulwide32<br>
> >> > define i64 @mulwide32(i32 %a, i32 %b) {<br>
> >> > -; CHECK: mul.wide.s32<br>
> >> > +; OPT: mul.wide.s32<br>
> >> > +; NOOPT: mul.lo.s64<br>
> >> > %val0 = sext i32 %a to i64<br>
> >> > %val1 = sext i32 %b to i64<br>
> >> > %val2 = mul i64 %val0, %val1<br>
> >> > ret i64 %val2<br>
> >> > }<br>
> >> ><br>
> >> > -; CHECK: mulwideu32<br>
> >> > +; OPT-LABEL: @mulwideu32<br>
> >> > +; NOOPT-LABEL: @mulwideu32<br>
> >> > define i64 @mulwideu32(i32 %a, i32 %b) {<br>
> >> > -; CHECK: mul.wide.u32<br>
> >> > +; OPT: mul.wide.u32<br>
> >> > +; NOOPT: mul.lo.s64<br>
> >> > %val0 = zext i32 %a to i64<br>
> >> > %val1 = zext i32 %b to i64<br>
> >> > %val2 = mul i64 %val0, %val1<br>
> >> ><br>
> >> ><br>
> >> > _______________________________________________<br>
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> >> > <a href="mailto:llvm-commits@cs.uiuc.edu">llvm-commits@cs.uiuc.edu</a><br>
> >> > <a href="http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits" target="_blank">http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits</a><br>
> >><br>
> >><br>
> >><br>
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> >><br>
> ><br>
> ><br>
> ><br>
> > --<br>
> ><br>
> > Thanks,<br>
> ><br>
> > Justin Holewinski<br>
> ><br>
><br>
><br>
><br>
> --<br>
><br>
> Thanks,<br>
><br>
> Justin Holewinski<br>
<br>
> _______________________________________________<br>
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<br>
</div></div></blockquote></div><br><br clear="all"><div><br></div>-- <br><br><div>Thanks,</div><div><br></div><div>Justin Holewinski</div>
</div></div>