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<div class="moz-cite-prefix">On 07/29/2014 10:41 AM, Vincent Lejeune
wrote:<br>
</div>
<blockquote
cite="mid:1406655698.53943.YahooMailNeo@web161504.mail.bf1.yahoo.com"
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font-family:HelveticaNeue, Helvetica Neue, Helvetica, Arial,
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font-family: HelveticaNeue,Helvetica
Neue,Helvetica,Arial,Lucida Grande,sans-serif;
background-color: transparent; font-style: normal;">I'm trying
to implement a machine scheduler for SI but I have a lot of
test failures because of range check.<br>
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background-color: transparent; font-style: normal;">Vincent<br>
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<br>
Do you have a branch with this scheduler work posted somewhere? I'm
looking at trying to fix scheduling of loads and stores, and my
biggest problem seems to be the default scheduler doesn't try to
cluster loads that are on different chains, even if they have the
same base pointer.<br>
<br>
Also, have you seen
cgit.freedesktop.org/~tstellar/llvm/log/?h=si-scheduler-v2 ?<br>
<br>
<br>
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<div dir="ltr"> <font size="2" face="Arial"> Le Mercredi
2 juillet 2014 23h07, Tom Stellard
<a class="moz-txt-link-rfc2396E" href="mailto:thomas.stellard@amd.com"><thomas.stellard@amd.com></a> a écrit :<br>
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<br>
<div class="y_msg_container">Author: tstellar<br>
Date: Wed Jul 2 15:53:48 2014<br>
New Revision: 212215<br>
<br>
URL: <a moz-do-not-send="true"
href="http://llvm.org/viewvc/llvm-project?rev=212215&view=rev"
target="_blank">http://llvm.org/viewvc/llvm-project?rev=212215&view=rev</a><br>
Log:<br>
R600/SI: Adjsut SGPR live ranges before register
allocation<br>
<br>
SGPRs are written by instructions that sometimes will
ignore control flow,<br>
which means if you have code like:<br>
<br>
if (VGPR0) {<br>
SGPR0 = S_MOV_B32 0<br>
} else {<br>
SGPR0 = S_MOV_B32 1<br>
}<br>
<br>
The value of SGPR0 will 1 no matter what the condition
is.<br>
<br>
In order to deal with this situation correctly, we
need to view the<br>
program as if it were a single basic block when we
calculate the<br>
live ranges for the SGPRs. They way we actually
update the live<br>
range is by iterating over all of the segments in each
LiveRange<br>
object and setting the end of each segment equal to
the start of<br>
the next segment. So a live range like:<br>
<br>
[3888r,9312r:0)[10032B,10384B:0) <a
moz-do-not-send="true" ymailto="mailto:0@3888r"
href="mailto:0@3888r">0@3888r</a><br>
<br>
will become:<br>
<br>
[3888r,10032B:0)[10032B,10384B:0) <a
moz-do-not-send="true" ymailto="mailto:0@3888r"
href="mailto:0@3888r">0@3888r</a><br>
<br>
This change will allow us to use SALU instructions
within branches.<br>
<br>
Added:<br>
llvm/trunk/lib/Target/R600/SIFixSGPRLiveRanges.cpp<br>
Modified:<br>
llvm/trunk/lib/Target/R600/AMDGPU.h<br>
llvm/trunk/lib/Target/R600/AMDGPUTargetMachine.cpp<br>
llvm/trunk/lib/Target/R600/CMakeLists.txt<br>
<br>
Modified: llvm/trunk/lib/Target/R600/AMDGPU.h<br>
URL: <a moz-do-not-send="true"
href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/R600/AMDGPU.h?rev=212215&r1=212214&r2=212215&view=diff"
target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/R600/AMDGPU.h?rev=212215&r1=212214&r2=212215&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/R600/AMDGPU.h (original)<br>
+++ llvm/trunk/lib/Target/R600/AMDGPU.h Wed Jul 2
15:53:48 2014<br>
@@ -41,6 +41,7 @@ FunctionPass
*createSIAnnotateControlFlo<br>
FunctionPass *createSILowerI1CopiesPass();<br>
FunctionPass
*createSILowerControlFlowPass(TargetMachine &tm);<br>
FunctionPass *createSIFixSGPRCopiesPass(TargetMachine
&tm);<br>
+FunctionPass *createSIFixSGPRLiveRangesPass();<br>
FunctionPass
*createSICodeEmitterPass(formatted_raw_ostream
&OS);<br>
FunctionPass *createSIInsertWaits(TargetMachine
&tm);<br>
<br>
@@ -56,6 +57,10 @@ FunctionPass
*createAMDGPUISelDag(Target<br>
ImmutablePass *<br>
createAMDGPUTargetTransformInfoPass(const
AMDGPUTargetMachine *TM);<br>
<br>
+void
initializeSIFixSGPRLiveRangesPass(PassRegistry&);<br>
+extern char &SIFixSGPRLiveRangesID;<br>
+<br>
+<br>
extern Target TheAMDGPUTarget;<br>
<br>
} // End namespace llvm<br>
<br>
Modified:
llvm/trunk/lib/Target/R600/AMDGPUTargetMachine.cpp<br>
URL: <a moz-do-not-send="true"
href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/R600/AMDGPUTargetMachine.cpp?rev=212215&r1=212214&r2=212215&view=diff"
target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/R600/AMDGPUTargetMachine.cpp?rev=212215&r1=212214&r2=212215&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/R600/AMDGPUTargetMachine.cpp
(original)<br>
+++ llvm/trunk/lib/Target/R600/AMDGPUTargetMachine.cpp
Wed Jul 2 15:53:48 2014<br>
@@ -174,6 +174,8 @@ bool
AMDGPUPassConfig::addPreRegAlloc()<br>
// SIFixSGPRCopies can generate a lot of duplicate
instructions,<br>
// so we need to run MachineCSE afterwards.<br>
addPass(&MachineCSEID);<br>
+
initializeSIFixSGPRLiveRangesPass(*PassRegistry::getPassRegistry());<br>
+ insertPass(&RegisterCoalescerID,
&SIFixSGPRLiveRangesID);<br>
}<br>
return false;<br>
}<br>
<br>
Modified: llvm/trunk/lib/Target/R600/CMakeLists.txt<br>
URL: <a moz-do-not-send="true"
href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/R600/CMakeLists.txt?rev=212215&r1=212214&r2=212215&view=diff"
target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/R600/CMakeLists.txt?rev=212215&r1=212214&r2=212215&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/R600/CMakeLists.txt
(original)<br>
+++ llvm/trunk/lib/Target/R600/CMakeLists.txt Wed Jul
2 15:53:48 2014<br>
@@ -40,6 +40,7 @@ add_llvm_target(R600CodeGen<br>
R600TextureIntrinsicsReplacer.cpp<br>
SIAnnotateControlFlow.cpp<br>
SIFixSGPRCopies.cpp<br>
+ SIFixSGPRLiveRanges.cpp<br>
SIInsertWaits.cpp<br>
SIInstrInfo.cpp<br>
SIISelLowering.cpp<br>
<br>
Added:
llvm/trunk/lib/Target/R600/SIFixSGPRLiveRanges.cpp<br>
URL: <a moz-do-not-send="true"
href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/R600/SIFixSGPRLiveRanges.cpp?rev=212215&view=auto"
target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/R600/SIFixSGPRLiveRanges.cpp?rev=212215&view=auto</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/R600/SIFixSGPRLiveRanges.cpp
(added)<br>
+++ llvm/trunk/lib/Target/R600/SIFixSGPRLiveRanges.cpp
Wed Jul 2 15:53:48 2014<br>
@@ -0,0 +1,110 @@<br>
+//===-- SIFixSGPRLiveRanges.cpp - Fix SGPR live
ranges ----------------------===//<br>
+//<br>
+// The LLVM Compiler
Infrastructure<br>
+//<br>
+// This file is distributed under the University of
Illinois Open Source<br>
+// License. See LICENSE.TXT for details.<br>
+//<br>
+//===----------------------------------------------------------------------===//<br>
+//<br>
+/// \file<br>
+/// SALU instructions ignore control flow, so we need
to modify the live ranges<br>
+/// of the registers they define.<br>
+///<br>
+/// The strategy is to view the entire program as if
it were a single basic<br>
+/// block and calculate the intervals accordingly.
We implement this<br>
+/// by walking this list of segments for each
LiveRange and setting the<br>
+/// end of each segment equal to the start of the
segment that immediately<br>
+/// follows it.<br>
+<br>
+#include "AMDGPU.h"<br>
+#include "SIRegisterInfo.h"<br>
+#include "llvm/CodeGen/LiveIntervalAnalysis.h"<br>
+#include "llvm/CodeGen/MachineFunctionPass.h"<br>
+#include "llvm/CodeGen/MachineRegisterInfo.h"<br>
+#include "llvm/Support/Debug.h"<br>
+#include "llvm/Target/TargetMachine.h"<br>
+<br>
+using namespace llvm;<br>
+<br>
+#define DEBUG_TYPE "si-fix-sgpr-live-ranges"<br>
+<br>
+namespace {<br>
+<br>
+class SIFixSGPRLiveRanges : public
MachineFunctionPass {<br>
+public:<br>
+ static char ID;<br>
+<br>
+public:<br>
+ SIFixSGPRLiveRanges() : MachineFunctionPass(ID) {<br>
+
initializeSIFixSGPRLiveRangesPass(*PassRegistry::getPassRegistry());<br>
+ }<br>
+<br>
+ virtual bool runOnMachineFunction(MachineFunction
&MF) override;<br>
+<br>
+ virtual const char *getPassName() const override {<br>
+ return "SI Fix SGPR live ranges";<br>
+ }<br>
+<br>
+ virtual void getAnalysisUsage(AnalysisUsage
&AU) const override {<br>
+ AU.addRequired<LiveIntervals>();<br>
+ AU.addPreserved<LiveIntervals>();<br>
+ AU.addPreserved<SlotIndexes>();<br>
+ AU.setPreservesCFG();<br>
+ MachineFunctionPass::getAnalysisUsage(AU);<br>
+ }<br>
+};<br>
+<br>
+} // End anonymous namespace.<br>
+<br>
+INITIALIZE_PASS_BEGIN(SIFixSGPRLiveRanges,
DEBUG_TYPE,<br>
+ "SI Fix SGPR Live Ranges",
false, false)<br>
+INITIALIZE_PASS_DEPENDENCY(LiveIntervals)<br>
+INITIALIZE_PASS_END(SIFixSGPRLiveRanges, DEBUG_TYPE,<br>
+ "SI Fix SGPR Live Ranges", false,
false)<br>
+<br>
+char SIFixSGPRLiveRanges::ID = 0;<br>
+<br>
+char &llvm::SIFixSGPRLiveRangesID =
SIFixSGPRLiveRanges::ID;<br>
+<br>
+FunctionPass *llvm::createSIFixSGPRLiveRangesPass() {<br>
+ return new SIFixSGPRLiveRanges();<br>
+}<br>
+<br>
+bool
SIFixSGPRLiveRanges::runOnMachineFunction(MachineFunction
&MF) {<br>
+ MachineRegisterInfo &MRI = MF.getRegInfo();<br>
+ const SIRegisterInfo *TRI = static_cast<const
SIRegisterInfo *>(<br>
+ MF.getTarget().getRegisterInfo());<br>
+ LiveIntervals *LIS =
&getAnalysis<LiveIntervals>();<br>
+<br>
+ for (MachineFunction::iterator BI = MF.begin(), BE
= MF.end();<br>
+ BI
!= BE; ++BI) {<br>
+<br>
+ MachineBasicBlock &MBB = *BI;<br>
+ for (MachineBasicBlock::iterator I = MBB.begin(),
E = MBB.end();<br>
+
I != E; ++I) {<br>
+ MachineInstr &MI = *I;<br>
+ MachineOperand *ExecUse =
MI.findRegisterUseOperand(AMDGPU::EXEC);<br>
+ if (ExecUse)<br>
+ continue;<br>
+<br>
+ for (const MachineOperand &Def :
MI.operands()) {<br>
+ if (!Def.isReg() || !Def.isDef()
||!TargetRegisterInfo::isVirtualRegister(Def.getReg()))<br>
+ continue;<br>
+<br>
+ const TargetRegisterClass *RC =
MRI.getRegClass(Def.getReg());<br>
+<br>
+ if (!TRI->isSGPRClass(RC))<br>
+ continue;<br>
+ LiveInterval &LI =
LIS->getInterval(Def.getReg());<br>
+ for (unsigned i = 0, e = LI.size() - 1; i !=
e; ++i) {<br>
+ LiveRange::Segment &Seg =
LI.segments[i];<br>
+ LiveRange::Segment &Next =
LI.segments[i + 1];<br>
+ Seg.end = Next.start;<br>
+ }<br>
+ }<br>
+ }<br>
+ }<br>
+<br>
+ return false;<br>
+}<br>
<br>
<br>
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