llvm[3]: Building X86.td register info implementation with tblgen
llvm[3]: Building X86.td instruction information with tblgen
1. NumTPNAlloc: 84347, NumTPNRel: 20190
1. NumTPAlloc: 13441, NumTPRel: 9215
2. NumTPNAlloc: 84347, NumTPNRel: 83879
2. NumTPAlloc: 13441, NumTPRel: 13271
468 TPNs remain, 170 TPs remain
Release done
3. NumTPNAlloc: 84347, NumTPNRel: 84347
3. NumTPAlloc: 13441, NumTPRel: 13441
llvm[3]: Building X86.td assembly writer with tblgen
llvm[3]: Building X86.td assembly matcher with tblgen
llvm[3]: Building X86.td assembly writer #1 with tblgen
llvm[3]: Building X86.td DAG instruction selector implementation with tblgen
1. NumTPNAlloc: 135380, NumTPNRel: 71223
1. NumTPAlloc: 13441, NumTPRel: 9215
2. NumTPNAlloc: 135380, NumTPNRel: 134912
2. NumTPAlloc: 13441, NumTPRel: 13271
468 TPNs remain, 170 TPs remain
Release done
3. NumTPNAlloc: 135380, NumTPNRel: 135380
3. NumTPAlloc: 13441, NumTPRel: 13441
llvm[3]: Building X86.td disassembly tables with tblgen
llvm[3]: Building X86.td "fast" instruction selector implementation with tblgen
1. NumTPNAlloc: 84347, NumTPNRel: 20190
1. NumTPAlloc: 13441, NumTPRel: 9215
2. NumTPNAlloc: 84347, NumTPNRel: 83879
2. NumTPAlloc: 13441, NumTPRel: 13271
468 TPNs remain, 170 TPs remain
Release done
3. NumTPNAlloc: 84347, NumTPNRel: 84347
3. NumTPAlloc: 13441, NumTPRel: 13441
llvm[3]: Building X86.td calling convention information with tblgen
llvm[3]: Building X86.td subtarget information with tblgen

make[3]: Entering directory `/sources/new/build_llvm/lib/Target/Sparc'
llvm[3]: Building Sparc.td register info implementation with tblgen
llvm[3]: Building Sparc.td instruction information with tblgen
1. NumTPNAlloc: 4092, NumTPNRel: 990
1. NumTPAlloc: 889, NumTPRel: 502
2. NumTPNAlloc: 4092, NumTPNRel: 3707
2. NumTPAlloc: 889, NumTPRel: 758
385 TPNs remain, 131 TPs remain
Release done
3. NumTPNAlloc: 4092, NumTPNRel: 4092
3. NumTPAlloc: 889, NumTPRel: 889
llvm[3]: Building Sparc.td assembly writer with tblgen
llvm[3]: Building Sparc.td assembly matcher with tblgen
llvm[3]: Building Sparc.td DAG instruction selector implementation with tblgen
1. NumTPNAlloc: 5934, NumTPNRel: 2832
1. NumTPAlloc: 889, NumTPRel: 502
2. NumTPNAlloc: 5934, NumTPNRel: 5549
2. NumTPAlloc: 889, NumTPRel: 758
385 TPNs remain, 131 TPs remain
Release done
3. NumTPNAlloc: 5934, NumTPNRel: 5934
3. NumTPAlloc: 889, NumTPRel: 889
llvm[3]: Building Sparc.td disassembly tables with tblgen
llvm[3]: Building Sparc.td subtarget information with tblgen
llvm[3]: Building Sparc.td calling convention information with tblgen
llvm[3]: Building Sparc.td code emitter with tblgen
llvm[3]: Building Sparc.td MC code emitter with tblgen

make[3]: Entering directory `/sources/new/build_llvm/lib/Target/PowerPC'
llvm[3]: Building PPC.td register info implementation with tblgen
llvm[3]: Building PPC.td assembly matcher with tblgen
llvm[3]: Building PPC.td assembly writer with tblgen
llvm[3]: Building PPC.td code emitter with tblgen
llvm[3]: Building PPC.td instruction information with tblgen
1. NumTPNAlloc: 18695, NumTPNRel: 4287
1. NumTPAlloc: 3471, NumTPRel: 2672
2. NumTPNAlloc: 18695, NumTPNRel: 18206
2. NumTPAlloc: 3471, NumTPRel: 3301
489 TPNs remain, 170 TPs remain
Release done
3. NumTPNAlloc: 18695, NumTPNRel: 18695
3. NumTPAlloc: 3471, NumTPRel: 3471
llvm[3]: Building PPC.td DAG instruction selector implementation with tblgen
1. NumTPNAlloc: 28649, NumTPNRel: 14241
1. NumTPAlloc: 3471, NumTPRel: 2672
2. NumTPNAlloc: 28649, NumTPNRel: 28160
2. NumTPAlloc: 3471, NumTPRel: 3301
489 TPNs remain, 170 TPs remain
Release done
3. NumTPNAlloc: 28649, NumTPNRel: 28649
3. NumTPAlloc: 3471, NumTPRel: 3471
llvm[3]: Building PPC.td subtarget information with tblgen
llvm[3]: Building PPC.td calling convention information with tblgen
llvm[3]: Building PPC.td MC code emitter with tblgen
llvm[3]: Building PPC.td "fast" instruction selector implementation with tblgen
1. NumTPNAlloc: 18695, NumTPNRel: 4287
1. NumTPAlloc: 3471, NumTPRel: 2672
2. NumTPNAlloc: 18695, NumTPNRel: 18206
2. NumTPAlloc: 3471, NumTPRel: 3301
489 TPNs remain, 170 TPs remain
Release done
3. NumTPNAlloc: 18695, NumTPNRel: 18695
3. NumTPAlloc: 3471, NumTPRel: 3471
llvm[3]: Building PPC.td disassembly tables with tblgen

make[3]: Entering directory `/sources/new/build_llvm/lib/Target/ARM'
llvm[3]: Building ARM.td register info implementation with tblgen
llvm[3]: Building ARM.td instruction information with tblgen
1. NumTPNAlloc: 29237, NumTPNRel: 6102
1. NumTPAlloc: 4963, NumTPRel: 3206
2. NumTPNAlloc: 29237, NumTPNRel: 28695
2. NumTPAlloc: 4963, NumTPRel: 4744
542 TPNs remain, 219 TPs remain
Release done
3. NumTPNAlloc: 29237, NumTPNRel: 29237
3. NumTPAlloc: 4963, NumTPRel: 4963
llvm[3]: Building ARM.td assembly writer with tblgen
llvm[3]: Building ARM.td assembly matcher with tblgen
llvm[3]: Building ARM.td DAG instruction selector implementation with tblgen
1. NumTPNAlloc: 49397, NumTPNRel: 26262
1. NumTPAlloc: 4963, NumTPRel: 3206
2. NumTPNAlloc: 49397, NumTPNRel: 48855
2. NumTPAlloc: 4963, NumTPRel: 4744
542 TPNs remain, 219 TPs remain
Release done
3. NumTPNAlloc: 49397, NumTPNRel: 49397
3. NumTPAlloc: 4963, NumTPRel: 4963
llvm[3]: Building ARM.td subtarget information with tblgen
llvm[3]: Building ARM.td code emitter with tblgen
llvm[3]: Building ARM.td calling convention information with tblgen
llvm[3]: Building ARM.td "fast" instruction selector implementation with tblgen
1. NumTPNAlloc: 29237, NumTPNRel: 6102
1. NumTPAlloc: 4963, NumTPRel: 3206
2. NumTPNAlloc: 29237, NumTPNRel: 28695
2. NumTPAlloc: 4963, NumTPRel: 4744
542 TPNs remain, 219 TPs remain
Release done
3. NumTPNAlloc: 29237, NumTPNRel: 29237
3. NumTPAlloc: 4963, NumTPRel: 4963
llvm[3]: Building ARM.td MC code emitter with tblgen
llvm[3]: Building ARM.td MC Pseudo instruction expander with tblgen
llvm[3]: Building ARM.td disassembly tables with tblgen

make[3]: Entering directory `/sources/new/build_llvm/lib/Target/AArch64'
llvm[3]: Building AArch64.td register info implementation with tblgen
llvm[3]: Building AArch64.td instruction information with tblgen
1. NumTPNAlloc: 43312, NumTPNRel: 10165
1. NumTPAlloc: 7426, NumTPRel: 5569
2. NumTPNAlloc: 43312, NumTPNRel: 42738
2. NumTPAlloc: 7426, NumTPRel: 7206
574 TPNs remain, 220 TPs remain
Release done
3. NumTPNAlloc: 43312, NumTPNRel: 43312
3. NumTPAlloc: 7426, NumTPRel: 7426
llvm[3]: Building AArch64.td assembly writer with tblgen
llvm[3]: Building AArch64.td assembly writer #1 with tblgen
llvm[3]: Building AArch64.td DAG instruction selector implementation with tblgen
1. NumTPNAlloc: 71948, NumTPNRel: 38801
1. NumTPAlloc: 7426, NumTPRel: 5569
2. NumTPNAlloc: 71948, NumTPNRel: 71374
2. NumTPAlloc: 7426, NumTPRel: 7206
574 TPNs remain, 220 TPs remain
Release done
3. NumTPNAlloc: 71948, NumTPNRel: 71948
3. NumTPAlloc: 7426, NumTPRel: 7426
llvm[3]: Building AArch64.td calling convention information with tblgen
llvm[3]: Building AArch64.td assembly matcher with tblgen
llvm[3]: Building AArch64.td subtarget information with tblgen
llvm[3]: Building AArch64.td MC code emitter with tblgen
llvm[3]: Building AArch64.td "fast" instruction selector implementation with tblgen
1. NumTPNAlloc: 43312, NumTPNRel: 10165
1. NumTPAlloc: 7426, NumTPRel: 5569
2. NumTPNAlloc: 43312, NumTPNRel: 42738
2. NumTPAlloc: 7426, NumTPRel: 7206
574 TPNs remain, 220 TPs remain
Release done
3. NumTPNAlloc: 43312, NumTPNRel: 43312
3. NumTPAlloc: 7426, NumTPRel: 7426
llvm[3]: Building AArch64.td disassembly tables with tblgen
llvm[3]: Building AArch64.td MC Pseudo instruction expander with tblgen

make[3]: Entering directory `/sources/new/build_llvm/lib/Target/Mips'
llvm[3]: Building Mips.td register info implementation with tblgen
llvm[3]: Building Mips.td instruction information with tblgen
1. NumTPNAlloc: 22810, NumTPNRel: 5017
1. NumTPAlloc: 3996, NumTPRel: 2729
2. NumTPNAlloc: 22810, NumTPNRel: 22405
2. NumTPAlloc: 3996, NumTPRel: 3846
405 TPNs remain, 150 TPs remain
Release done
3. NumTPNAlloc: 22810, NumTPNRel: 22810
3. NumTPAlloc: 3996, NumTPRel: 3996
llvm[3]: Building Mips.td assembly writer with tblgen
llvm[3]: Building Mips.td "fast" instruction selector implementation with tblgen
1. NumTPNAlloc: 22810, NumTPNRel: 5017
1. NumTPAlloc: 3996, NumTPRel: 2729
2. NumTPNAlloc: 22810, NumTPNRel: 22405
2. NumTPAlloc: 3996, NumTPRel: 3846
405 TPNs remain, 150 TPs remain
Release done
3. NumTPNAlloc: 22810, NumTPNRel: 22810
3. NumTPAlloc: 3996, NumTPRel: 3996
llvm[3]: Building Mips.td code emitter with tblgen
llvm[3]: Building Mips.td DAG instruction selector implementation with tblgen
1. NumTPNAlloc: 35532, NumTPNRel: 17739
1. NumTPAlloc: 3996, NumTPRel: 2729
2. NumTPNAlloc: 35532, NumTPNRel: 35127
2. NumTPAlloc: 3996, NumTPRel: 3846
405 TPNs remain, 150 TPs remain
Release done
3. NumTPNAlloc: 35532, NumTPNRel: 35532
3. NumTPAlloc: 3996, NumTPRel: 3996
llvm[3]: Building Mips.td calling convention information with tblgen
llvm[3]: Building Mips.td subtarget information with tblgen
llvm[3]: Building Mips.td MC code emitter with tblgen
llvm[3]: Building Mips.td disassembly tables with tblgen
llvm[3]: Building Mips.td MC Pseudo instruction expander with tblgen
llvm[3]: Building Mips.td assembly matcher with tblgen

make[3]: Entering directory `/sources/new/build_llvm/lib/Target/XCore'
llvm[3]: Building XCore.td register info implementation with tblgen
llvm[3]: Building XCore.td instruction information with tblgen
1. NumTPNAlloc: 2858, NumTPNRel: 762
1. NumTPAlloc: 611, NumTPRel: 330
2. NumTPNAlloc: 2858, NumTPNRel: 2467
2. NumTPAlloc: 611, NumTPRel: 474
391 TPNs remain, 137 TPs remain
Release done
3. NumTPNAlloc: 2858, NumTPNRel: 2858
3. NumTPAlloc: 611, NumTPRel: 611
llvm[3]: Building XCore.td assembly writer with tblgen
llvm[3]: Building XCore.td DAG instruction selector implementation with tblgen
1. NumTPNAlloc: 4305, NumTPNRel: 2209
1. NumTPAlloc: 611, NumTPRel: 330
2. NumTPNAlloc: 4305, NumTPNRel: 3914
2. NumTPAlloc: 611, NumTPRel: 474
391 TPNs remain, 137 TPs remain
Release done
3. NumTPNAlloc: 4305, NumTPNRel: 4305
3. NumTPAlloc: 611, NumTPRel: 611
llvm[3]: Building XCore.td calling convention information with tblgen
llvm[3]: Building XCore.td disassembly tables with tblgen
llvm[3]: Building XCore.td subtarget information with tblgen

make[3]: Entering directory `/sources/new/build_llvm/lib/Target/MSP430'
llvm[3]: Building MSP430.td register info implementation with tblgen
llvm[3]: Building MSP430.td instruction information with tblgen
1. NumTPNAlloc: 3653, NumTPNRel: 1110
1. NumTPAlloc: 574, NumTPRel: 266
2. NumTPNAlloc: 3653, NumTPNRel: 3269
2. NumTPAlloc: 574, NumTPRel: 446
384 TPNs remain, 128 TPs remain
Release done
3. NumTPNAlloc: 3653, NumTPNRel: 3653
3. NumTPAlloc: 574, NumTPRel: 574
llvm[3]: Building MSP430.td assembly writer with tblgen
llvm[3]: Building MSP430.td DAG instruction selector implementation with tblgen
1. NumTPNAlloc: 5823, NumTPNRel: 3280
1. NumTPAlloc: 574, NumTPRel: 266
2. NumTPNAlloc: 5823, NumTPNRel: 5439
2. NumTPAlloc: 574, NumTPRel: 446
384 TPNs remain, 128 TPs remain
Release done
3. NumTPNAlloc: 5823, NumTPNRel: 5823
3. NumTPAlloc: 574, NumTPRel: 574
llvm[3]: Building MSP430.td calling convention information with tblgen
llvm[3]: Building MSP430.td subtarget information with tblgen

make[3]: Entering directory `/sources/new/build_llvm/lib/Target/NVPTX'
llvm[3]: Building NVPTX.td assembly writer with tblgen
llvm[3]: Building NVPTX.td DAG instruction selector implementation with tblgen
1. NumTPNAlloc: 42384, NumTPNRel: 22502
1. NumTPAlloc: 5216, NumTPRel: 3934
2. NumTPNAlloc: 42384, NumTPNRel: 41752
2. NumTPAlloc: 5216, NumTPRel: 5003
632 TPNs remain, 213 TPs remain
Release done
3. NumTPNAlloc: 42384, NumTPNRel: 42384
3. NumTPAlloc: 5216, NumTPRel: 5216
llvm[3]: Building NVPTX.td instruction information with tblgen
1. NumTPNAlloc: 27572, NumTPNRel: 7690
1. NumTPAlloc: 5216, NumTPRel: 3934
2. NumTPNAlloc: 27572, NumTPNRel: 26940
2. NumTPAlloc: 5216, NumTPRel: 5003
632 TPNs remain, 213 TPs remain
Release done
3. NumTPNAlloc: 27572, NumTPNRel: 27572
3. NumTPAlloc: 5216, NumTPRel: 5216
llvm[3]: Building NVPTX.td register info implementation with tblgen
llvm[3]: Building NVPTX.td subtarget information with tblgen

make[3]: Entering directory `/sources/new/build_llvm/lib/Target/Hexagon'
llvm[3]: Building Hexagon.td register info implementation with tblgen
llvm[3]: Building Hexagon.td instruction information with tblgen
1. NumTPNAlloc: 26209, NumTPNRel: 6164
1. NumTPAlloc: 3787, NumTPRel: 2508
2. NumTPNAlloc: 26209, NumTPNRel: 25754
2. NumTPAlloc: 3787, NumTPRel: 3587
455 TPNs remain, 200 TPs remain
Release done
3. NumTPNAlloc: 26209, NumTPNRel: 26209
3. NumTPAlloc: 3787, NumTPRel: 3787
llvm[3]: Building Hexagon.td assembly writer with tblgen
llvm[3]: Building Hexagon.td DAG instruction selector implementation with tblgen
1. NumTPNAlloc: 42433, NumTPNRel: 22388
1. NumTPAlloc: 3787, NumTPRel: 2508
2. NumTPNAlloc: 42433, NumTPNRel: 41978
2. NumTPAlloc: 3787, NumTPRel: 3587
455 TPNs remain, 200 TPs remain
Release done
3. NumTPNAlloc: 42433, NumTPNRel: 42433
3. NumTPAlloc: 3787, NumTPRel: 3787
llvm[3]: Building Hexagon.td subtarget information with tblgen
llvm[3]: Building Hexagon.td calling convention information with tblgen
llvm[3]: Building Hexagon.td DFA packetizer tables with tblgen

make[3]: Entering directory `/sources/new/build_llvm/lib/Target/SystemZ'
llvm[3]: Building SystemZ.td register info implementation with tblgen
llvm[3]: Building SystemZ.td assembly writer with tblgen
llvm[3]: Building SystemZ.td assembly matcher with tblgen
llvm[3]: Building SystemZ.td code emitter with tblgen
llvm[3]: Building SystemZ.td disassembly tables with tblgen
llvm[3]: Building SystemZ.td instruction information with tblgen
1. NumTPNAlloc: 11964, NumTPNRel: 3738
1. NumTPAlloc: 1852, NumTPRel: 1076
2. NumTPNAlloc: 11964, NumTPNRel: 11435
2. NumTPAlloc: 1852, NumTPRel: 1654
529 TPNs remain, 198 TPs remain
Release done
3. NumTPNAlloc: 11964, NumTPNRel: 11964
3. NumTPAlloc: 1852, NumTPRel: 1852
llvm[3]: Building SystemZ.td DAG instruction selector implementation with tblgen
1. NumTPNAlloc: 19037, NumTPNRel: 10811
1. NumTPAlloc: 1852, NumTPRel: 1076
2. NumTPNAlloc: 19037, NumTPNRel: 18508
2. NumTPAlloc: 1852, NumTPRel: 1654
529 TPNs remain, 198 TPs remain
Release done
3. NumTPNAlloc: 19037, NumTPNRel: 19037
3. NumTPAlloc: 1852, NumTPRel: 1852
llvm[3]: Building SystemZ.td subtarget information with tblgen
llvm[3]: Building SystemZ.td calling convention information with tblgen
llvm[3]: Building SystemZ.td MC code emitter with tblgen

make[3]: Entering directory `/sources/new/build_llvm/lib/Target/R600'
llvm[3]: Building AMDGPU.td register info implementation with tblgen
llvm[3]: Building AMDGPU.td instruction information with tblgen
1. NumTPNAlloc: 22288, NumTPNRel: 3635
1. NumTPAlloc: 3421, NumTPRel: 2846
2. NumTPNAlloc: 22288, NumTPNRel: 21743
2. NumTPAlloc: 3421, NumTPRel: 3207
545 TPNs remain, 214 TPs remain
Release done
3. NumTPNAlloc: 22288, NumTPNRel: 22288
3. NumTPAlloc: 3421, NumTPRel: 3421
llvm[3]: Building AMDGPU.td DAG instruction selector implementation with tblgen
1. NumTPNAlloc: 36974, NumTPNRel: 18321
1. NumTPAlloc: 3421, NumTPRel: 2846
2. NumTPNAlloc: 36974, NumTPNRel: 36429
2. NumTPAlloc: 3421, NumTPRel: 3207
545 TPNs remain, 214 TPs remain
Release done
3. NumTPNAlloc: 36974, NumTPNRel: 36974
3. NumTPAlloc: 3421, NumTPRel: 3421
llvm[3]: Building AMDGPU.td subtarget information with tblgen
llvm[3]: Building AMDGPU.td MC code emitter with tblgen
llvm[3]: Building AMDGPU.td calling convention information with tblgen
llvm[3]: Building AMDGPU.td intrinsics information with tblgen
llvm[3]: Building AMDGPU.td DFA packetizer tables with tblgen
llvm[3]: Building AMDGPU.td assembly writer with tblgen
