<div dir="ltr"><div>Oh, sorry... I fixed it in rev213774<br></div><div><br></div><div>Thanks, Adam!</div></div><div class="gmail_extra"><br><br><div class="gmail_quote">2014-07-23 21:34 GMT+04:00 Adam Nemet <span dir="ltr"><<a href="mailto:anemet@apple.com" target="_blank">anemet@apple.com</a>></span>:<br>
<blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"><div class="HOEnZb"><div class="h5"><br>
On Jul 23, 2014, at 7:49 AM, Robert Khasanov <<a href="mailto:rob.khasanov@gmail.com">rob.khasanov@gmail.com</a>> wrote:<br>
<br>
> Author: rkhasanov<br>
> Date: Wed Jul 23 09:49:42 2014<br>
> New Revision: 213757<br>
><br>
> URL: <a href="http://llvm.org/viewvc/llvm-project?rev=213757&view=rev" target="_blank">http://llvm.org/viewvc/llvm-project?rev=213757&view=rev</a><br>
> Log:<br>
> [SKX] Enabling mask instructions: encoding, lowering<br>
> KMOVB, KMOVW, KMOVD, KMOVQ, KNOTB, KNOTW, KNOTD, KNOTQ<br>
><br>
> Reviewed by Elena Demikhovsky <<a href="mailto:elena.demikhovsky@intel.com">elena.demikhovsky@intel.com</a>><br>
><br>
> Modified:<br>
> llvm/trunk/lib/Target/X86/X86ISelLowering.cpp<br>
> llvm/trunk/lib/Target/X86/X86InstrAVX512.td<br>
> llvm/trunk/lib/Target/X86/X86InstrInfo.cpp<br>
> llvm/trunk/test/CodeGen/X86/avx512-mask-op.ll<br>
> llvm/trunk/test/MC/X86/avx512-encodings.s<br>
> llvm/trunk/utils/TableGen/X86RecognizableInstr.cpp<br>
><br>
> Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp<br>
> URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=213757&r1=213756&r2=213757&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=213757&r1=213756&r2=213757&view=diff</a><br>
> ==============================================================================<br>
> --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)<br>
> +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Wed Jul 23 09:49:42 2014<br>
> @@ -1505,6 +1505,11 @@ void X86TargetLowering::resetOperationAc<br>
> }<br>
> }// has AVX-512<br>
><br>
> + if (!TM.Options.UseSoftFloat && Subtarget->hasBWI()) {<br>
> + addRegisterClass(MVT::v32i1, &X86::VK32RegClass);<br>
> + addRegisterClass(MVT::v64i1, &X86::VK64RegClass);<br>
> + }<br>
> +<br>
> // SIGN_EXTEND_INREGs are evaluated by the extend type. Handle the expansion<br>
> // of this type with custom code.<br>
> for (int VT = MVT::FIRST_VECTOR_VALUETYPE;<br>
> @@ -2312,6 +2317,10 @@ X86TargetLowering::LowerFormalArguments(<br>
> RC = &X86::VK8RegClass;<br>
> else if (RegVT == MVT::v16i1)<br>
> RC = &X86::VK16RegClass;<br>
> + else if (RegVT == MVT::v32i1)<br>
> + RC = &X86::VK32RegClass;<br>
> + else if (RegVT == MVT::v64i1)<br>
> + RC = &X86::VK64RegClass;<br>
> else<br>
> llvm_unreachable("Unknown argument type!");<br>
><br>
><br>
> Modified: llvm/trunk/lib/Target/X86/X86InstrAVX512.td<br>
> URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrAVX512.td?rev=213757&r1=213756&r2=213757&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrAVX512.td?rev=213757&r1=213756&r2=213757&view=diff</a><br>
> ==============================================================================<br>
> --- llvm/trunk/lib/Target/X86/X86InstrAVX512.td (original)<br>
> +++ llvm/trunk/lib/Target/X86/X86InstrAVX512.td Wed Jul 23 09:49:42 2014<br>
> @@ -1031,14 +1031,14 @@ def : Pat<(i8 (int_x86_avx512_mask_cmp_p<br>
> //<br>
> multiclass avx512_mask_mov<bits<8> opc_kk, bits<8> opc_km, bits<8> opc_mk,<br>
> string OpcodeStr, RegisterClass KRC,<br>
> - ValueType vt, X86MemOperand x86memop> {<br>
> + ValueType vvt, ValueType ivt, X86MemOperand x86memop> {<br>
> let hasSideEffects = 0 in {<br>
> def kk : I<opc_kk, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src),<br>
> !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"), []>;<br>
> let mayLoad = 1 in<br>
> def km : I<opc_km, MRMSrcMem, (outs KRC:$dst), (ins x86memop:$src),<br>
> !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),<br>
> - [(set KRC:$dst, (vt (load addr:$src)))]>;<br>
> + [(set KRC:$dst, (vvt (bitconvert (ivt (load addr:$src)))))]>;<br>
> let mayStore = 1 in<br>
> def mk : I<opc_mk, MRMDestMem, (outs), (ins x86memop:$dst, KRC:$src),<br>
> !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"), []>;<br>
> @@ -1056,33 +1056,79 @@ multiclass avx512_mask_mov_gpr<bits<8> o<br>
> }<br>
> }<br>
><br>
> -let Predicates = [HasAVX512] in {<br>
> - defm KMOVW : avx512_mask_mov<0x90, 0x90, 0x91, "kmovw", VK16, v16i1, i16mem>,<br>
> - VEX, PS;<br>
> - defm KMOVW : avx512_mask_mov_gpr<0x92, 0x93, "kmovw", VK16, GR32>,<br>
> +let Predicates = [HasDQI] in<br>
> + defm KMOVB : avx512_mask_mov<0x90, 0x90, 0x91, "kmovb", VK8, v8i1, i8,<br>
> + i8mem>,<br>
> + avx512_mask_mov_gpr<0x92, 0x93, "kmovb", VK8, GR32>,<br>
> + VEX, PD;<br>
> +<br>
> +let Predicates = [HasAVX512] in<br>
> + defm KMOVW : avx512_mask_mov<0x90, 0x90, 0x91, "kmovw", VK16, v16i1, i16,<br>
> + i16mem>,<br>
> + avx512_mask_mov_gpr<0x92, 0x93, "kmovw", VK16, GR32>,<br>
> VEX, PS;<br>
> +<br>
> +let Predicates = [HasBWI] in {<br>
> + defm KMOVD : avx512_mask_mov<0x90, 0x90, 0x91, "kmovd", VK32, v32i1, i32,<br>
> + i32mem>, VEX, PD, VEX_W;<br>
> + defm KMOVD : avx512_mask_mov_gpr<0x92, 0x93, "kmovd", VK32, GR32>,<br>
> + VEX, XD;<br>
> +}<br>
> +<br>
> +let Predicates = [HasBWI] in {<br>
> + defm KMOVQ : avx512_mask_mov<0x90, 0x90, 0x91, "kmovq", VK64, v64i1, i64,<br>
> + i64mem>, VEX, PS, VEX_W;<br>
> + defm KMOVQ : avx512_mask_mov_gpr<0x92, 0x93, "kmovq", VK64, GR64>,<br>
> + VEX, XD, VEX_W;<br>
> }<br>
><br>
> +// GR from/to mask register<br>
> +let Predicates = [HasDQI] in {<br>
> + def : Pat<(v8i1 (bitconvert (i8 GR8:$src))),<br>
> + (KMOVBkr (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit))>;<br>
> + def : Pat<(i8 (bitconvert (v8i1 VK8:$src))),<br>
> + (EXTRACT_SUBREG (KMOVBrk VK8:$src), sub_8bit)>;<br>
> +}<br>
> let Predicates = [HasAVX512] in {<br>
> - // GR16 from/to 16-bit mask<br>
> def : Pat<(v16i1 (bitconvert (i16 GR16:$src))),<br>
> (KMOVWkr (SUBREG_TO_REG (i32 0), GR16:$src, sub_16bit))>;<br>
> def : Pat<(i16 (bitconvert (v16i1 VK16:$src))),<br>
> (EXTRACT_SUBREG (KMOVWrk VK16:$src), sub_16bit)>;<br>
> +}<br>
> +let Predicates = [HasBWI] in {<br>
> + def : Pat<(v32i1 (bitconvert (i32 GR32:$src))), (KMOVDkr GR32:$src)>;<br>
> + def : Pat<(i32 (bitconvert (v32i1 VK32:$src))), (KMOVDrk VK32:$src)>;<br>
> +}<br>
> +let Predicates = [HasBWI] in {<br>
> + def : Pat<(v64i1 (bitconvert (i64 GR64:$src))), (KMOVQkr GR64:$src)>;<br>
> + def : Pat<(i64 (bitconvert (v64i1 VK64:$src))), (KMOVQrk VK64:$src)>;<br>
> +}<br>
><br>
> - // Store kreg in memory<br>
> - def : Pat<(store (v16i1 VK16:$src), addr:$dst),<br>
> +// Load/store kreg<br>
> +let Predicates = [HasDQI] in {<br>
> + def : Pat<(store (i8 (bitconvert (v8i1 VK8:$src))), addr:$dst),<br>
> + (KMOVBmk addr:$dst, VK8:$src)>;<br>
> +}<br>
> +let Predicates = [HasAVX512] in {<br>
> + def : Pat<(store (i16 (bitconvert (v16i1 VK16:$src))), addr:$dst),<br>
> (KMOVWmk addr:$dst, VK16:$src)>;<br>
> -<br>
> - def : Pat<(store VK8:$src, addr:$dst),<br>
> + def : Pat<(store (i8 (bitconvert (v8i1 VK8:$src))), addr:$dst),<br>
> (KMOVWmk addr:$dst, (COPY_TO_REGCLASS VK8:$src, VK16))>;<br>
> -<br>
> def : Pat<(i1 (load addr:$src)),<br>
> (COPY_TO_REGCLASS (KMOVWkm addr:$src), VK1)>;<br>
> -<br>
> - def : Pat<(v8i1 (load addr:$src)),<br>
> + def : Pat<(v8i1 (bitconvert (i8 (load addr:$src)))),<br>
> (COPY_TO_REGCLASS (KMOVWkm addr:$src), VK8)>;<br>
> +}<br>
> +let Predicates = [HasBWI] in {<br>
> + def : Pat<(store (i32 (bitconvert (v32i1 VK32:$src))), addr:$dst),<br>
> + (KMOVDmk addr:$dst, VK32:$src)>;<br>
> +}<br>
> +let Predicates = [HasBWI] in {<br>
> + def : Pat<(store (i64 (bitconvert (v64i1 VK64:$src))), addr:$dst),<br>
> + (KMOVQmk addr:$dst, VK64:$src)>;<br>
> +}<br>
><br>
> +let Predicates = [HasAVX512] in {<br>
> def : Pat<(i1 (trunc (i32 GR32:$src))),<br>
> (COPY_TO_REGCLASS (KMOVWkr (AND32ri $src, (i32 1))), VK1)>;<br>
><br>
> @@ -1094,7 +1140,7 @@ let Predicates = [HasAVX512] in {<br>
> (COPY_TO_REGCLASS<br>
> (KMOVWkr (AND32ri (SUBREG_TO_REG (i32 0), $src, sub_16bit), (i32 1))),<br>
> VK1)>;<br>
> -<br>
> +<br>
> def : Pat<(i32 (zext VK1:$src)),<br>
> (AND32ri (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), (i32 1))>;<br>
> def : Pat<(i8 (zext VK1:$src)),<br>
> @@ -1113,6 +1159,14 @@ let Predicates = [HasAVX512] in {<br>
> def : Pat<(v8i1 (scalar_to_vector VK1:$src)),<br>
> (COPY_TO_REGCLASS VK1:$src, VK8)>;<br>
> }<br>
> +let Predicates = [HasBWI] in {<br>
> + def : Pat<(v32i1 (scalar_to_vector VK1:$src)),<br>
> + (COPY_TO_REGCLASS VK1:$src, VK32)>;<br>
> + def : Pat<(v64i1 (scalar_to_vector VK1:$src)),<br>
> + (COPY_TO_REGCLASS VK1:$src, VK64)>;<br>
> +}<br>
> +<br>
> +<br>
> // With AVX-512 only, 8-bit mask is promoted to 16-bit mask.<br>
> let Predicates = [HasAVX512] in {<br>
> // GR from/to 8-bit mask without native support<br>
> @@ -1129,26 +1183,38 @@ let Predicates = [HasAVX512] in {<br>
> (COPY_TO_REGCLASS VK16:$src, VK1)>;<br>
> def : Pat<(i1 (X86Vextract VK8:$src, (iPTR 0))),<br>
> (COPY_TO_REGCLASS VK8:$src, VK1)>;<br>
> -<br>
> +}<br>
> +let Predicates = [HasBWI] in {<br>
> + def : Pat<(i1 (X86Vextract VK32:$src, (iPTR 0))),<br>
> + (COPY_TO_REGCLASS VK32:$src, VK1)>;<br>
> + def : Pat<(i1 (X86Vextract VK64:$src, (iPTR 0))),<br>
> + (COPY_TO_REGCLASS VK64:$src, VK1)>;<br>
> }<br>
><br>
> // Mask unary operation<br>
> // - KNOT<br>
> multiclass avx512_mask_unop<bits<8> opc, string OpcodeStr,<br>
> - RegisterClass KRC, SDPatternOperator OpNode> {<br>
> - let Predicates = [HasAVX512] in<br>
> + RegisterClass KRC, SDPatternOperator OpNode,<br>
> + Predicate prd> {<br>
> + let Predicates = [prd] in<br>
> def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src),<br>
> !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),<br>
> [(set KRC:$dst, (OpNode KRC:$src))]>;<br>
> }<br>
><br>
> -multiclass avx512_mask_unop_w<bits<8> opc, string OpcodeStr,<br>
> - SDPatternOperator OpNode> {<br>
> - defm W : avx512_mask_unop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode>,<br>
> - VEX, PS;<br>
> +multiclass avx512_mask_unop_all<bits<8> opc, string OpcodeStr,<br>
> + SDPatternOperator OpNode> {<br>
> + defm B : avx512_mask_unop<opc, !strconcat(OpcodeStr, "b"), VK8, OpNode,<br>
> + HasDQI>, VEX, PD;<br>
> + defm W : avx512_mask_unop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode,<br>
> + HasAVX512>, VEX, PS;<br>
> + defm D : avx512_mask_unop<opc, !strconcat(OpcodeStr, "d"), VK32, OpNode,<br>
> + HasBWI>, VEX, PD, VEX_W;<br>
> + defm Q : avx512_mask_unop<opc, !strconcat(OpcodeStr, "q"), VK64, OpNode,<br>
> + HasBWI>, VEX, PS, VEX_W;<br>
> }<br>
><br>
> -defm KNOT : avx512_mask_unop_w<0x44, "knot", not>;<br>
> +defm KNOT : avx512_mask_unop_all<0x44, "knot", not>;<br>
><br>
> multiclass avx512_mask_unop_int<string IntName, string InstName> {<br>
> let Predicates = [HasAVX512] in<br>
> @@ -1159,14 +1225,24 @@ multiclass avx512_mask_unop_int<string I<br>
> }<br>
> defm : avx512_mask_unop_int<"knot", "KNOT">;<br>
><br>
> +let Predicates = [HasDQI] in<br>
> +def : Pat<(xor VK8:$src1, (v8i1 immAllOnesV)), (KNOTBrr VK8:$src1)>;<br>
> +let Predicates = [HasAVX512] in<br>
> def : Pat<(xor VK16:$src1, (v16i1 immAllOnesV)), (KNOTWrr VK16:$src1)>;<br>
> +let Predicates = [HasBWI] in<br>
> +def : Pat<(xor VK32:$src1, (v32i1 immAllOnesV)), (KNOTDrr VK32:$src1)>;<br>
> +let Predicates = [HasBWI] in<br>
> +def : Pat<(xor VK64:$src1, (v64i1 immAllOnesV)), (KNOTQrr VK64:$src1)>;<br>
> +<br>
> +// KNL does not support KMOVB, 8-bit mask is promoted to 16-bit<br>
> +let Predicates = [HasAVX512] in {<br>
> def : Pat<(xor VK8:$src1, (v8i1 immAllOnesV)),<br>
> (COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK8:$src1, VK16)), VK8)>;<br>
><br>
> -// With AVX-512, 8-bit mask is promoted to 16-bit mask.<br>
> def : Pat<(not VK8:$src),<br>
> (COPY_TO_REGCLASS<br>
> (KNOTWrr (COPY_TO_REGCLASS VK8:$src, VK16)), VK8)>;<br>
> +}<br>
><br>
> // Mask binary operation<br>
> // - KAND, KANDN, KOR, KXNOR, KXOR<br>
><br>
> Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.cpp<br>
> URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.cpp?rev=213757&r1=213756&r2=213757&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.cpp?rev=213757&r1=213756&r2=213757&view=diff</a><br>
> ==============================================================================<br>
> --- llvm/trunk/lib/Target/X86/X86InstrInfo.cpp (original)<br>
> +++ llvm/trunk/lib/Target/X86/X86InstrInfo.cpp Wed Jul 23 09:49:42 2014<br>
> @@ -3067,6 +3067,8 @@ static unsigned CopyToFromAsymmetricReg(<br>
> inline static bool MaskRegClassContains(unsigned Reg) {<br>
> return X86::VK8RegClass.contains(Reg) ||<br>
> X86::VK16RegClass.contains(Reg) ||<br>
> + X86::VK32RegClass.contains(Reg) ||<br>
> + X86::VK64RegClass.contains(Reg) ||<br>
> X86::VK1RegClass.contains(Reg);<br>
> }<br>
> static<br>
><br>
> Modified: llvm/trunk/test/CodeGen/X86/avx512-mask-op.ll<br>
> URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx512-mask-op.ll?rev=213757&r1=213756&r2=213757&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx512-mask-op.ll?rev=213757&r1=213756&r2=213757&view=diff</a><br>
> ==============================================================================<br>
> --- llvm/trunk/test/CodeGen/X86/avx512-mask-op.ll (original)<br>
> +++ llvm/trunk/test/CodeGen/X86/avx512-mask-op.ll Wed Jul 23 09:49:42 2014<br>
> @@ -5,8 +5,10 @@ define i16 @mask16(i16 %x) {<br>
> %m1 = xor <16 x i1> %m0, <i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1><br>
> %ret = bitcast <16 x i1> %m1 to i16<br>
> ret i16 %ret<br>
> -; CHECK: mask16<br>
> -; CHECK: knotw<br>
> +; CHECK-LABEL: mask16<br>
> +; CHECK: kmovw<br>
> +; CHECK-NEXT: knotw<br>
> +; CHECK-NEXT: kmovw<br>
> ; CHECK: ret<br>
> }<br>
><br>
> @@ -15,8 +17,38 @@ define i8 @mask8(i8 %x) {<br>
> %m1 = xor <8 x i1> %m0, <i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1><br>
> %ret = bitcast <8 x i1> %m1 to i8<br>
> ret i8 %ret<br>
> -; CHECK: mask8<br>
> -; CHECK: knotw<br>
> +; CHECK-LABEL: mask8<br>
> +; CHECK: kmovw<br>
> +; CHECK-NEXT: knotw<br>
> +; CHECK-NEXT: kmovw<br>
> +; CHECK: ret<br>
> +}<br>
> +<br>
> +define void @mask16_mem(i16* %ptr) {<br>
> + %x = load i16* %ptr, align 4<br>
> + %m0 = bitcast i16 %x to <16 x i1><br>
> + %m1 = xor <16 x i1> %m0, <i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1><br>
> + %ret = bitcast <16 x i1> %m1 to i16<br>
> + store i16 %ret, i16* %ptr, align 4<br>
> + ret void<br>
> +; CHECK-LABEL: mask16_mem<br>
> +; CHECK: kmovw (%rdi), %k{{[0-7]}}<br>
> +; CHECK-NEXT: knotw<br>
> +; CHECK-NEXT: kmovw %k{{[0-7]}}, (%rdi)<br>
> +; CHECK: ret<br>
> +}<br>
> +<br>
> +define void @mask8_mem(i8* %ptr) {<br>
> + %x = load i8* %ptr, align 4<br>
> + %m0 = bitcast i8 %x to <8 x i1><br>
> + %m1 = xor <8 x i1> %m0, <i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1><br>
> + %ret = bitcast <8 x i1> %m1 to i8<br>
> + store i8 %ret, i8* %ptr, align 4<br>
> + ret void<br>
> +; CHECK-LABEL: mask8_mem<br>
> +; CHECK: kmovw (%rdi), %k{{[0-7]}}<br>
> +; CHECK-NEXT: knotw<br>
> +; CHECK-NEXT: kmovw %k{{[0-7]}}, (%rdi)<br>
> ; CHECK: ret<br>
> }<br>
><br>
><br>
> Modified: llvm/trunk/test/MC/X86/avx512-encodings.s<br>
> URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/X86/avx512-encodings.s?rev=213757&r1=213756&r2=213757&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/X86/avx512-encodings.s?rev=213757&r1=213756&r2=213757&view=diff</a><br>
> ==============================================================================<br>
> --- llvm/trunk/test/MC/X86/avx512-encodings.s (original)<br>
> +++ llvm/trunk/test/MC/X86/avx512-encodings.s Wed Jul 23 09:49:42 2014<br>
> @@ -2489,6 +2489,54 @@<br>
> // CHECK: encoding: [0x62,0x71,0x24,0x50,0x5c,0xb2,0xfc,0xfd,0xff,0xff]<br>
> vsubps -516(%rdx){1to16}, %zmm27, %zmm14<br>
><br>
> +// CHECK: knotw %k6, %k3<br>
> +// CHECK: encoding: [0xc5,0xf8,0x44,0xde]<br>
> + knotw %k6, %k3<br>
> +<br>
> +// check: kmovw %k5, %k4<br>
> +// check: encoding: [0xc5,0xf8,0x90,0xe5]<br>
> + kmovw %k5, %k4<br>
> +<br>
> +// check: kmovw (%rcx), %k4<br>
> +// check: encoding: [0xc5,0xf8,0x90,0x21]<br>
> + kmovw (%rcx), %k4<br>
> +<br>
> +// check: kmovw 291(%rax,%r14,8), %k4<br>
> +// check: encoding: [0xc4,0xa1,0x78,0x90,0xa4,0xf0,0x23,0x01,0x00,0x00]<br>
> + kmovw 291(%rax,%r14,8), %k4<br>
> +<br>
> +// check: kmovw %k4, (%rcx)<br>
> +// check: encoding: [0xc5,0xf8,0x91,0x21]<br>
> + kmovw %k4, (%rcx)<br>
> +<br>
> +// check: kmovw %k4, 291(%rax,%r14,8)<br>
> +// check: encoding: [0xc4,0xa1,0x78,0x91,0xa4,0xf0,0x23,0x01,0x00,0x00]<br>
> + kmovw %k4, 291(%rax,%r14,8)<br>
> +<br>
> +// check: kmovw %eax, %k3<br>
> +// check: encoding: [0xc5,0xf8,0x92,0xd8]<br>
> + kmovw %eax, %k3<br>
> +<br>
> +// check: kmovw %ebp, %k3<br>
> +// check: encoding: [0xc5,0xf8,0x92,0xdd]<br>
> + kmovw %ebp, %k3<br>
> +<br>
> +// check: kmovw %r13d, %k3<br>
> +// check: encoding: [0xc4,0xc1,0x78,0x92,0xdd]<br>
> + kmovw %r13d, %k3<br>
> +<br>
> +// check: kmovw %k2, %eax<br>
> +// check: encoding: [0xc5,0xf8,0x93,0xc2]<br>
> + kmovw %k2, %eax<br>
> +<br>
> +// check: kmovw %k2, %ebp<br>
> +// check: encoding: [0xc5,0xf8,0x93,0xea]<br>
> + kmovw %k2, %ebp<br>
> +<br>
> +// check: kmovw %k2, %r13d<br>
> +// check: encoding: [0xc5,0x78,0x93,0xea]<br>
> + kmovw %k2, %r13d<br>
<br>
<br>
</div></div>Hi Robert,<br>
<br>
I don’t think lowercase check: works as uppercase CHECK:.<br>
<span class="HOEnZb"><font color="#888888"><br>
Adam<br>
</font></span><div class="HOEnZb"><div class="h5"><br>
> +<br>
> // CHECK: vpmovqb %zmm2, %xmm3<br>
> // CHECK: encoding: [0x62,0xf2,0x7e,0x48,0x32,0xd3]<br>
> vpmovqb %zmm2, %xmm3<br>
><br>
> Modified: llvm/trunk/utils/TableGen/X86RecognizableInstr.cpp<br>
> URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/X86RecognizableInstr.cpp?rev=213757&r1=213756&r2=213757&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/X86RecognizableInstr.cpp?rev=213757&r1=213756&r2=213757&view=diff</a><br>
> ==============================================================================<br>
> --- llvm/trunk/utils/TableGen/X86RecognizableInstr.cpp (original)<br>
> +++ llvm/trunk/utils/TableGen/X86RecognizableInstr.cpp Wed Jul 23 09:49:42 2014<br>
> @@ -1059,6 +1059,8 @@ RecognizableInstr::rmRegisterEncodingFro<br>
> ENCODING("VK1", ENCODING_RM)<br>
> ENCODING("VK8", ENCODING_RM)<br>
> ENCODING("VK16", ENCODING_RM)<br>
> + ENCODING("VK32", ENCODING_RM)<br>
> + ENCODING("VK64", ENCODING_RM)<br>
> errs() << "Unhandled R/M register encoding " << s << "\n";<br>
> llvm_unreachable("Unhandled R/M register encoding");<br>
> }<br>
> @@ -1087,6 +1089,8 @@ RecognizableInstr::roRegisterEncodingFro<br>
> ENCODING("VK1", ENCODING_REG)<br>
> ENCODING("VK8", ENCODING_REG)<br>
> ENCODING("VK16", ENCODING_REG)<br>
> + ENCODING("VK32", ENCODING_REG)<br>
> + ENCODING("VK64", ENCODING_REG)<br>
> ENCODING("VK1WM", ENCODING_REG)<br>
> ENCODING("VK8WM", ENCODING_REG)<br>
> ENCODING("VK16WM", ENCODING_REG)<br>
><br>
><br>
> _______________________________________________<br>
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> <a href="mailto:llvm-commits@cs.uiuc.edu">llvm-commits@cs.uiuc.edu</a><br>
> <a href="http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits" target="_blank">http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits</a><br>
<br>
</div></div></blockquote></div><br></div>