Hi Adam,<div><br></div><div>Thanks for noticing.<span></span></div><div>Yes, I have tests for embedded broadcasting {1to2} and {1to4}. They will be in one patch with new instructions (from AVX512VL subset). I will provide them soon.</div>
<div><br><br>понедельник, 21 июля 2014 г. пользователь Adam Nemet написал:<br>
<blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">On Jul 21, 2014, at 7:54 AM, Robert Khasanov <<a>rob.khasanov@gmail.com</a>> wrote:<br>
<br>
> Author: rkhasanov<br>
> Date: Mon Jul 21 09:54:21 2014<br>
> New Revision: 213545<br>
><br>
> URL: <a href="http://llvm.org/viewvc/llvm-project?rev=213545&view=rev" target="_blank">http://llvm.org/viewvc/llvm-project?rev=213545&view=rev</a><br>
> Log:<br>
> [SKX] Enabling SKX target and AVX512BW, AVX512DQ, AVX512VL features.<br>
><br>
> Enabling HasAVX512{DQ,BW,VL} predicates.<br>
> Adding VK2, VK4, VK32, VK64 masked register classes.<br>
> Adding new types (v64i8, v32i16) to VR512.<br>
> Extending calling conventions for new types (v64i8, v32i16)<br>
><br>
> Patch by Zinovy Nis <<a>zinovy.y.nis@intel.com</a>><br>
> Reviewed by Elena Demikhovsky <<a>elena.demikhovsky@intel.com</a>><br>
><br>
> Modified:<br>
> llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp<br>
> llvm/trunk/lib/Target/X86/Disassembler/X86DisassemblerDecoderCommon.h<br>
> llvm/trunk/lib/Target/X86/X86.td<br>
> llvm/trunk/lib/Target/X86/X86CallingConv.td<br>
> llvm/trunk/lib/Target/X86/X86InstrAVX512.td<br>
> llvm/trunk/lib/Target/X86/X86InstrFormats.td<br>
> llvm/trunk/lib/Target/X86/X86InstrInfo.td<br>
> llvm/trunk/lib/Target/X86/X86RegisterInfo.td<br>
> llvm/trunk/lib/Target/X86/X86Subtarget.cpp<br>
> llvm/trunk/lib/Target/X86/X86Subtarget.h<br>
> llvm/trunk/utils/TableGen/X86RecognizableInstr.cpp<br>
><br>
> Modified: llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp<br>
> URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp?rev=213545&r1=213544&r2=213545&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp?rev=213545&r1=213544&r2=213545&view=diff</a><br>
> ==============================================================================<br>
> --- llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp (original)<br>
> +++ llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp Mon Jul 21 09:54:21 2014<br>
> @@ -1666,6 +1666,8 @@ bool X86AsmParser::HandleAVX512Operand(O<br>
> // Recognize only reasonable suffixes.<br>
> const char *BroadcastPrimitive =<br>
> StringSwitch<const char*>(getLexer().getTok().getIdentifier())<br>
> + .Case("to2", "{1to2}")<br>
> + .Case("to4", "{1to4}")<br>
> .Case("to8", "{1to8}")<br>
> .Case("to16", "{1to16}")<br>
> .Default(nullptr);<br>
<br>
Hi Robert,<br>
<br>
Thanks for committing these in small chunks!<br>
<br>
I am assuming that you will have tests for the new broadcast types later but it would be good to pair the feature and the test in the same patch. (E.g. add a sample instruction that supports 1to4 with all the necessary infrastructure along with a test.)<br>
<br>
Adam<br>
<br>
> Modified: llvm/trunk/lib/Target/X86/Disassembler/X86DisassemblerDecoderCommon.h<br>
> URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/Disassembler/X86DisassemblerDecoderCommon.h?rev=213545&r1=213544&r2=213545&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/Disassembler/X86DisassemblerDecoderCommon.h?rev=213545&r1=213544&r2=213545&view=diff</a><br>
> ==============================================================================<br>
> --- llvm/trunk/lib/Target/X86/Disassembler/X86DisassemblerDecoderCommon.h (original)<br>
> +++ llvm/trunk/lib/Target/X86/Disassembler/X86DisassemblerDecoderCommon.h Mon Jul 21 09:54:21 2014<br>
> @@ -265,7 +265,7 @@ enum attributeBits {<br>
> ENUM_ENTRY(IC_EVEX_L2_W_KZ, 3, "requires EVEX_KZ, L2 and W") \<br>
> ENUM_ENTRY(IC_EVEX_L2_W_XS_KZ, 4, "requires EVEX_KZ, L2, W and XS prefix") \<br>
> ENUM_ENTRY(IC_EVEX_L2_W_XD_KZ, 4, "requires EVEX_KZ, L2, W and XD prefix") \<br>
> - ENUM_ENTRY(IC_EVEX_L2_W_OPSIZE_KZ, 4, "requires EVEX_KZ, L2, W and OpSize")<br>
> + ENUM_ENTRY(IC_EVEX_L2_W_OPSIZE_KZ, 4, "requires EVEX_KZ, L2, W and OpSize")<br>
><br>
> #define ENUM_ENTRY(n, r, d) n,<br>
> enum InstructionContext {<br>
> @@ -453,8 +453,12 @@ enum OperandEncoding {<br>
> ENUM_ENTRY(TYPE_XMM256, "32-byte") \<br>
> ENUM_ENTRY(TYPE_XMM512, "64-byte") \<br>
> ENUM_ENTRY(TYPE_VK1, "1-bit") \<br>
> + ENUM_ENTRY(TYPE_VK2, "2-bit") \<br>
> + ENUM_ENTRY(TYPE_VK4, "4-bit") \<br>
> ENUM_ENTRY(TYPE_VK8, "8-bit") \<br>
> ENUM_ENTRY(TYPE_VK16, "16-bit") \<br>
> + ENUM_ENTRY(TYPE_VK32, "32-bit") \<br>
> + ENUM_ENTRY(TYPE_VK64, "64-bit") \<br>
> ENUM_ENTRY(TYPE_XMM0, "Implicit use of XMM0") \<br>
> ENUM_ENTRY(TYPE_SEGMENTREG, "Segment register operand") \<br>
> ENUM_ENTRY(TYPE_DEBUGREG, "Debug register operand") \<br>
><br>
> Modified: llvm/trunk/lib/Target/X86/X86.td<br>
> URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86.td?rev=213545&r1=213544&r2=213545&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86.td?rev=213545&r1=213544&r2=213545&view=diff</a><br>
> ==============================================================================<br>
> --- llvm/trunk/lib/Target/X86/X86.td (original)<br>
> +++ llvm/trunk/lib/Target/X86/X86.td Mon Jul 21 09:54:21 2014<br>
> @@ -104,7 +104,15 @@ def FeatureCDI : SubtargetFeature<"<br>
> def FeaturePFI : SubtargetFeature<"avx512pf", "HasPFI", "true",<br>
> "Enable AVX-512 PreFetch Instructions",<br>
> [FeatureAVX512]>;<br>
> -<br>
> +def FeatureDQI : SubtargetFeature<"avx512dq", "HasDQI", "true",<br>
> + "Enable AVX-512 Doubleword and Quadword Instructions",<br>
> + [FeatureAVX512]>;<br>
> +def FeatureBWI : SubtargetFeature<"avx512bw", "HasBWI", "true",<br>
> + "Enable AVX-512 Byte and Word Instructions",<br>
> + [FeatureAVX512]>;<br>
> +def FeatureVLX : SubtargetFeature<"avx512vl", "HasVLX", "true",<br>
> + "Enable AVX-512 Vector Length eXtensions",<br>
> + [FeatureAVX512]>;<br>
> def FeaturePCLMUL : SubtargetFeature<"pclmul", "HasPCLMUL", "true",<br>
> "Enable packed carry-less multiplication instructions",<br>
> [FeatureSSE2]>;<br>
> @@ -273,6 +281,17 @@ def : ProcessorModel<"knl", HaswellModel<br>
> FeatureCMPXCHG16B, FeatureFastUAMem, FeaturePOPCNT,<br>
> FeatureAES, FeaturePCLMUL, FeatureRDRAND, FeatureF16C,<br>
> FeatureFSGSBase, FeatureMOVBE, FeatureLZCNT, FeatureBMI,<br>
> + FeatureBMI2, FeatureFMA, FeatureRTM, FeatureHLE,<br>
> + FeatureSlowIncDec]>;<br>
> +<br>
> +// SKX<br>
> +// FIXME: define SKX model<br>
> +def : ProcessorModel<"skx", HaswellModel,<br>
> + [FeatureAVX512, FeatureCDI,<br>
> + FeatureDQI, FeatureBWI, FeatureVLX,<br>
> + FeatureCMPXCHG16B, FeatureFastUAMem, FeaturePOPCNT,<br>
> + FeatureAES, FeaturePCLMUL, FeatureRDRAND, FeatureF16C,<br>
> + FeatureFSGSBase, FeatureMOVBE, FeatureLZCNT, FeatureBMI,<br>
> FeatureBMI2, FeatureFMA, FeatureRTM, FeatureHLE,<br>
> FeatureSlowIncDec]>;<br>
><br>
><br>
> Modified: llvm/trunk/lib/Target/X86/X86CallingConv.td<br>
> URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86CallingConv.td?rev=213545&r1=213544&r2=213545&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86CallingConv.td?rev=213545&r1=213544&r2=213545&view=diff</a><br>
> ==============================================================================<br>
> --- llvm/trunk/lib/Target/X86/X86CallingConv.td (original)<br>
> +++ llvm/trunk/lib/Target/X86/X86CallingConv.td Mon Jul 21 09:54:21 2014<br>
> @@ -52,7 +52,7 @@ def RetCC_X86Common : CallingConv<[<br>
> // 512-bit vectors are returned in ZMM0 and ZMM1, when they fit. ZMM2 and ZMM3<br>
> // can only be used by ABI non-compliant code. This vector type is only<br>
> // supported while using the AVX-512 target feature.<br>
> - CCIfType<[v16i32, v8i64, v16f32, v8f64],<br>
> + CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],<br>
> CCAssignToReg<[ZMM0,ZMM1,ZMM2,ZMM3]>>,<br>
><br>
> // MMX vector types are always returned in MM0. If the target doesn't have<br>
> @@ -252,7 +252,7 @@ def CC_X86_64_C : CallingConv<[<br>
> YMM4, YMM5, YMM6, YMM7]>>>>,<br>
><br>
> // The first 8 512-bit vector arguments are passed in ZMM registers.<br>
> - CCIfNotVarArg<CCIfType<[v16i32, v8i64, v16f32, v8f64],<br>
> + CCIfNotVarArg<CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],<br>
> CCIfSubtarget<"hasAVX512()",<br>
> CCAssignToReg<[ZMM0, ZMM1, ZMM2, ZMM3, ZMM4, ZMM5, ZMM6, ZMM7]>>>>,<br>
><br>
><br>
> Modified: llvm/trunk/lib/Target/X86/X86InstrAVX512.td<br>
> URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrAVX512.td?rev=213545&r1=213544&r2=213545&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrAVX512.td?rev=213545&r1=213544&r2=213545&view=diff</a><br>
> ==============================================================================<br>
> --- llvm/trunk/lib/Target/X86/X86InstrAVX512.td (original)<br>
> +++ llvm/trunk/lib/Target/X86/X86InstrAVX512.td Mon Jul 21 09:54:21 2014<br>
> @@ -1,19 +1,36 @@<br>
> // Bitcasts between 512-bit vector types. Return the original type since<br>
> // no instruction is needed for the conversion<br>
> let Predicates = [HasAVX512] in {<br>
> - def : Pat<(v8f64 (bitconvert (v16f32 VR512:$src))), (v8f64 VR512:$src)>;<br>
> - def : Pat<(v8f64 (bitconvert (v16i32 VR512:$src))), (v8f64 VR512:$src)>;<br>
> def : Pat<(v8f64 (bitconvert (v8i64 VR512:$src))), (v8f64 VR512:$src)>;<br>
> - def : Pat<(v16f32 (bitconvert (v16i32 VR512:$src))), (v16f32 VR512:$src)>;<br>
> + def : Pat<(v8f64 (bitconvert (v16i32 VR512:$src))), (v8f64 VR512:$src)>;<br>
> + def : Pat<(v8f64 (bitconvert (v32i16 VR512:$src))), (v8f64 VR512:$src)>;<br>
> + def : Pat<(v8f64 (bitconvert (v64i8 VR512:$src))), (v8f64 VR512:$src)>;<br>
> + def : Pat<(v8f64 (bitconvert (v16f32 VR512:$src))), (v8f64 VR512:$src)>;<br>
> def : Pat<(v16f32 (bitconvert (v8i64 VR512:$src))), (v16f32 VR512:$src)>;<br>
> + def : Pat<(v16f32 (bitconvert (v16i32 VR512:$src))), (v16f32 VR512:$src)>;<br>
> + def : Pat<(v16f32 (bitconvert (v32i16 VR512:$src))), (v16f32 VR512:$src)>;<br>
> + def : Pat<(v16f32 (bitconvert (v64i8 VR512:$src))), (v16f32 VR512:$src)>;<br>
> def : Pat<(v16f32 (bitconvert (v8f64 VR512:$src))), (v16f32 VR512:$src)>;<br>
> - def : Pat<(v8i64 (bitconvert (v16f32 VR512:$src))), (v8i64 VR512:$src)>;<br>
> def : Pat<(v8i64 (bitconvert (v16i32 VR512:$src))), (v8i64 VR512:$src)>;<br>
> + def : Pat<(v8i64 (bitconvert (v32i16 VR512:$src))), (v8i64 VR512:$src)>;<br>
> + def : Pat<(v8i64 (bitconvert (v64i8 VR512:$src))), (v8i64 VR512:$src)>;<br>
> def : Pat<(v8i64 (bitconvert (v8f64 VR512:$src))), (v8i64 VR512:$src)>;<br>
> - def : Pat<(v16i32 (bitconvert (v16f32 VR512:$src))), (v16i32 VR512:$src)>;<br>
> - def : Pat<(v16i32 (bitconvert (v8i64 VR512:$src))), (v16i32 VR512:$src)>;<br>
> + def : Pat<(v8i64 (bitconvert (v16f32 VR512:$src))), (v8i64 VR512:$src)>;<br>
> + def : Pat<(v16i32 (bitconvert (v8i64 VR512:$src))), (v16i32 VR512:$src)>;<br>
> + def : Pat<(v16i32 (bitconvert (v32i16 VR512:$src))), (v16i32 VR512:$src)>;<br>
> + def : Pat<(v16i32 (bitconvert (v64i8 VR512:$src))), (v16i32 VR512:$src)>;<br>
> def : Pat<(v16i32 (bitconvert (v8f64 VR512:$src))), (v16i32 VR512:$src)>;<br>
> - def : Pat<(v8f64 (bitconvert (v8i64 VR512:$src))), (v8f64 VR512:$src)>;<br>
> + def : Pat<(v32i16 (bitconvert (v8i64 VR512:$src))), (v32i16 VR512:$src)>;<br>
> + def : Pat<(v32i16 (bitconvert (v16i32 VR512:$src))), (v32i16 VR512:$src)>;<br>
> + def : Pat<(v32i16 (bitconvert (v64i8 VR512:$src))), (v32i16 VR512:$src)>;<br>
> + def : Pat<(v32i16 (bitconvert (v8f64 VR512:$src))), (v32i16 VR512:$src)>;<br>
> + def : Pat<(v32i16 (bitconvert (v16f32 VR512:$src))), (v32i16 VR512:$src)>;<br>
> + def : Pat<(v32i16 (bitconvert (v16f32 VR512:$src))), (v32i16 VR512:$src)>;<br>
> + def : Pat<(v64i8 (bitconvert (v8i64 VR512:$src))), (v64i8 VR512:$src)>;<br>
> + def : Pat<(v64i8 (bitconvert (v16i32 VR512:$src))), (v64i8 VR512:$src)>;<br>
> + def : Pat<(v64i8 (bitconvert (v32i16 VR512:$src))), (v64i8 VR512:$src)>;<br>
> + def : Pat<(v64i8 (bitconvert (v8f64 VR512:$src))), (v64i8 VR512:$src)>;<br>
> + def : Pat<(v64i8 (bitconvert (v16f32 VR512:$src))), (v64i8 VR512:$src)>;<br>
><br>
> def : Pat<(v2i64 (bitconvert (v4i32 VR128X:$src))), (v2i64 VR128X:$src)>;<br>
> def : Pat<(v2i64 (bitconvert (v8i16 VR128X:$src))), (v2i64 VR128X:$src)>;<br>
> @@ -135,7 +152,6 @@ def VINSERTI32x4rm : AVX512AIi8<0x38, MR<br>
> (ins VR512:$src1, i128mem:$src2, i8imm:$src3),<br>
> "vinserti32x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",<br>
> []>, EVEX_4V, EVEX_V512, EVEX_CD8<32, CD8VT4>;<br>
> -<br>
> }<br>
><br>
> let hasSideEffects = 0 in {<br>
><br>
> Modified: llvm/trunk/lib/Target/X86/X86InstrFormats.td<br>
> URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrFormats.td?rev=213545&r1=213544&r2=213545&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrFormats.td?rev=213545&r1=213544&r2=213545&view=diff</a><br>
> ==============================================================================<br>
> --- llvm/trunk/lib/Target/X86/X86InstrFormats.td (original)<br>
> +++ llvm/trunk/lib/Target/X86/X86InstrFormats.td Mon Jul 21 09:54:21 2014<br>
> @@ -184,6 +184,8 @@ class EVEX_KZ : EVEX_K { bit hasEVEX_Z =<br>
> class EVEX_B { bit hasEVEX_B = 1; }<br>
> class EVEX_RC { bit hasEVEX_RC = 1; }<br>
> class EVEX_V512 { bit hasEVEX_L2 = 1; bit hasVEX_L = 0; }<br>
> +class EVEX_V256 { bit hasEVEX_L2 = 0; bit hasVEX_L = 1; }<br>
> +class EVEX_V128 { bit hasEVEX_L2 = 0; bit hasVEX_L = 0; }<br>
><br>
> // Specify AVX512 8-bit compressed displacement encoding based on the vector<br>
> // element size in bits (8, 16, 32, 64) and the CDisp8 form.<br>
><br>
> Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.td<br>
> URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.td?rev=213545&r1=213544&r2=213545&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.td?rev=213545&r1=213544&r2=213545&view=diff</a><br>
> ==============================================================================<br>
> --- llvm/trunk/lib/Target/X86/X86InstrInfo.td (original)<br>
> +++ llvm/trunk/lib/Target/X86/X86InstrInfo.td Mon Jul 21 09:54:21 2014<br>
> @@ -719,10 +719,14 @@ def HasAVX512 : Predicate<"Subtarget-<br>
> AssemblerPredicate<"FeatureAVX512", "AVX-512 ISA">;<br>
> def UseAVX : Predicate<"Subtarget->hasAVX() && !Subtarget->hasAVX512()">;<br>
> def UseAVX2 : Predicate<"Subtarget->hasAVX2() && !Subtarget->hasAVX512()">;<br>
> -def NoAVX512 : Predicate<"!Subtarget->hasAVX512()">;<br>
> +def NoAVX512 : Predicate<"!Subtarget->hasAVX512()">;<br>
> def HasCDI : Predicate<"Subtarget->hasCDI()">;<br>
> def HasPFI : Predicate<"Subtarget->hasPFI()">;<br>
> def HasERI : Predicate<"Subtarget->hasERI()">;<br>
> +def HasDQI : Predicate<"Subtarget->hasDQI()">;<br>
> +def HasBWI : Predicate<"Subtarget->hasBWI()">;<br>
> +def HasVLX : Predicate<"Subtarget->hasVLX()">,<br>
> + AssemblerPredicate<"FeatureVLX", "AVX-512 VLX ISA">;<br>
><br>
> def HasPOPCNT : Predicate<"Subtarget->hasPOPCNT()">;<br>
> def HasAES : Predicate<"Subtarget->hasAES()">;<br>
><br>
> Modified: llvm/trunk/lib/Target/X86/X86RegisterInfo.td<br>
> URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86RegisterInfo.td?rev=213545&r1=213544&r2=213545&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86RegisterInfo.td?rev=213545&r1=213544&r2=213545&view=diff</a><br>
> ==============================================================================<br>
> --- llvm/trunk/lib/Target/X86/X86RegisterInfo.td (original)<br>
> +++ llvm/trunk/lib/Target/X86/X86RegisterInfo.td Mon Jul 21 09:54:21 2014<br>
> @@ -449,7 +449,7 @@ def FPCCR : RegisterClass<"X86", [i16],<br>
> }<br>
><br>
> // AVX-512 vector/mask registers.<br>
> -def VR512 : RegisterClass<"X86", [v16f32, v8f64, v16i32, v8i64], 512,<br>
> +def VR512 : RegisterClass<"X86", [v16f32, v8f64, v64i8, v32i16, v16i32, v8i64], 512,<br>
> (sequence "ZMM%u", 0, 31)>;<br>
><br>
> // Scalar AVX-512 floating point registers.<br>
> @@ -463,13 +463,19 @@ def VR128X : RegisterClass<"X86", [v16i8<br>
> def VR256X : RegisterClass<"X86", [v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],<br>
> 256, (sequence "YMM%u", 0, 31)>;<br>
><br>
> -// The size of the all masked registers is 16 bit because we have only one<br>
> -// KMOVW istruction that can store this register in memory, and it writes 2 bytes<br>
> -def VK1 : RegisterClass<"X86", [i1], 16, (sequence "K%u", 0, 7)>;<br>
> -def VK8 : RegisterClass<"X86", [v8i1], 16, (add VK1)> {let Size = 16;}<br>
> +// Mask registers<br>
> +def VK1 : RegisterClass<"X86", [i1], 16, (sequence "K%u", 0, 7)> {let Size = 16;}<br>
> +def VK2 : RegisterClass<"X86", [v2i1], 16, (add VK1)> {let Size = 16;}<br>
> +def VK4 : RegisterClass<"X86", [v4i1], 16, (add VK2)> {let Size = 16;}<br>
> +def VK8 : RegisterClass<"X86", [v8i1], 16, (add VK4)> {let Size = 16;}<br>
> def VK16 : RegisterClass<"X86", [v16i1], 16, (add VK8)> {let Size = 16;}<br>
> +def VK32 : RegisterClass<"X86", [v32i1], 32, (add VK16)> {let Size = 32;}<br>
> +def VK64 : RegisterClass<"X86", [v64i1], 64, (add VK32)> {let Size = 64;}<br>
><br>
> def VK1WM : RegisterClass<"X86", [i1], 16, (sub VK1, K0)> {let Size = 16;}<br>
> +def VK2WM : RegisterClass<"X86", [v2i1], 16, (sub VK2, K0)> {let Size = 16;}<br>
> +def VK4WM : RegisterClass<"X86", [v4i1], 16, (sub VK4, K0)> {let Size = 16;}<br>
> def VK8WM : RegisterClass<"X86", [v8i1], 16, (sub VK8, K0)> {let Size = 16;}<br>
> -def VK16WM : RegisterClass<"X86", [v16i1], 16, (add VK8WM)>;<br>
> -<br>
> +def VK16WM : RegisterClass<"X86", [v16i1], 16, (add VK8WM)> {let Size = 16;}<br>
> +def VK32WM : RegisterClass<"X86", [v32i1], 32, (add VK16WM)> {let Size = 32;}<br>
> +def VK64WM : RegisterClass<"X86", [v64i1], 64, (add VK32WM)> {let Size = 64;}<br>
><br>
> Modified: llvm/trunk/lib/Target/X86/X86Subtarget.cpp<br>
> URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86Subtarget.cpp?rev=213545&r1=213544&r2=213545&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86Subtarget.cpp?rev=213545&r1=213544&r2=213545&view=diff</a><br>
> ==============================================================================<br>
> --- llvm/trunk/lib/Target/X86/X86Subtarget.cpp (original)<br>
> +++ llvm/trunk/lib/Target/X86/X86Subtarget.cpp Mon Jul 21 09:54:21 2014<br>
> @@ -272,6 +272,9 @@ void X86Subtarget::initializeEnvironment<br>
> HasERI = false;<br>
> HasCDI = false;<br>
> HasPFI = false;<br>
> + HasDQI = false;<br>
> + HasBWI = false;<br>
> + HasVLX = false;<br>
> HasADX = false;<br>
> HasSHA = false;<br>
> HasPRFCHW = false;<br>
><br>
> Modified: llvm/trunk/lib/Target/X86/X86Subtarget.h<br>
> URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86Subtarget.h?rev=213545&r1=213544&r2=213545&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86Subtarget.h?rev=213545&r1=213544&r2=213545&view=diff</a><br>
> ==============================================================================<br>
> --- llvm/trunk/lib/Target/X86/X86Subtarget.h (original)<br>
> +++ llvm/trunk/lib/Target/X86/X86Subtarget.h Mon Jul 21 09:54:21 2014<br>
> @@ -189,13 +189,22 @@ protected:<br>
><br>
> /// Processor has AVX-512 PreFetch Instructions<br>
> bool HasPFI;<br>
> -<br>
> +<br>
> /// Processor has AVX-512 Exponential and Reciprocal Instructions<br>
> bool HasERI;<br>
> -<br>
> +<br>
> /// Processor has AVX-512 Conflict Detection Instructions<br>
> bool HasCDI;<br>
> -<br>
> +<br>
> + /// Processor has AVX-512 Doubleword and Quadword instructions<br>
> + bool HasDQI;<br>
> +<br>
> + /// Processor has AVX-512 Byte and Word instructions<br>
> + bool HasBWI;<br>
> +<br>
> + /// Processor has AVX-512 Vector Length eXtenstions<br>
> + bool HasVLX;<br>
> +<br>
> /// stackAlignment - The minimum alignment known to hold of the stack frame on<br>
> /// entry to the function and which must be maintained by every function.<br>
> unsigned stackAlignment;<br>
> @@ -349,6 +358,9 @@ public:<br>
> bool hasCDI() const { return HasCDI; }<br>
> bool hasPFI() const { return HasPFI; }<br>
> bool hasERI() const { return HasERI; }<br>
> + bool hasDQI() const { return HasDQI; }<br>
> + bool hasBWI() const { return HasBWI; }<br>
> + bool hasVLX() const { return HasVLX; }<br>
><br>
> bool isAtom() const { return X86ProcFamily == IntelAtom; }<br>
> bool isSLM() const { return X86ProcFamily == IntelSLM; }<br>
><br>
> Modified: llvm/trunk/utils/TableGen/X86RecognizableInstr.cpp<br>
> URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/X86RecognizableInstr.cpp?rev=213545&r1=213544&r2=213545&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/X86RecognizableInstr.cpp?rev=213545&r1=213544&r2=213545&view=diff</a><br>
> ==============================================================================<br>
> --- llvm/trunk/utils/TableGen/X86RecognizableInstr.cpp (original)<br>
> +++ llvm/trunk/utils/TableGen/X86RecognizableInstr.cpp Mon Jul 21 09:54:21 2014<br>
> @@ -975,10 +975,18 @@ OperandType RecognizableInstr::typeFromS<br>
> TYPE("VR512", TYPE_XMM512)<br>
> TYPE("VK1", TYPE_VK1)<br>
> TYPE("VK1WM", TYPE_VK1)<br>
> + TYPE("VK2", TYPE_VK2)<br>
> + TYPE("VK2WM", TYPE_VK2)<br>
> + TYPE("VK4", TYPE_VK4)<br>
> + TYPE("VK4WM", TYPE_VK4)<br>
> TYPE("VK8", TYPE_VK8)<br>
> TYPE("VK8WM", TYPE_VK8)<br>
> TYPE("VK16", TYPE_VK16)<br>
> TYPE("VK16WM", TYPE_VK16)<br>
> + TYPE("VK32", TYPE_VK32)<br>
> + TYPE("VK32WM", TYPE_VK32)<br>
> + TYPE("VK64", TYPE_VK64)<br>
> + TYPE("VK64WM", TYPE_VK64)<br>
> TYPE("GR16_NOAX", TYPE_Rv)<br>
> TYPE("GR32_NOAX", TYPE_Rv)<br>
> TYPE("GR64_NOAX", TYPE_R64)<br>
> @@ -1101,6 +1109,8 @@ RecognizableInstr::vvvvRegisterEncodingF<br>
> ENCODING("VR256X", ENCODING_VVVV)<br>
> ENCODING("VR512", ENCODING_VVVV)<br>
> ENCODING("VK1", ENCODING_VVVV)<br>
> + ENCODING("VK2", ENCODING_VVVV)<br>
> + ENCODING("VK4", ENCODING_VVVV)<br>
> ENCODING("VK8", ENCODING_VVVV)<br>
> ENCODING("VK16", ENCODING_VVVV)<br>
> errs() << "Unhandled VEX.vvvv register encoding " << s << "\n";<br>
> @@ -1111,8 +1121,12 @@ OperandEncoding<br>
> RecognizableInstr::writemaskRegisterEncodingFromString(const std::string &s,<br>
> uint8_t OpSize) {<br>
> ENCODING("VK1WM", ENCODING_WRITEMASK)<br>
> + ENCODING("VK2WM", ENCODING_WRITEMASK)<br>
> + ENCODING("VK4WM", ENCODING_WRITEMASK)<br>
> ENCODING("VK8WM", ENCODING_WRITEMASK)<br>
> ENCODING("VK16WM", ENCODING_WRITEMASK)<br>
> + ENCODING("VK32WM", ENCODING_WRITEMASK)<br>
> + ENCODING("VK64WM", ENCODING_WRITEMASK)<br>
> errs() << "Unhandled mask register encoding " << s << "\n";<br>
> llvm_unreachable("Unhandled mask register encoding");<br>
> }<br>
><br>
><br>
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<br>
</blockquote></div>