<html><head></head><body>Yes, please do.<br><br><div class="gmail_quote">On 19. Juli 2014 20:04:07 MESZ, Matt Arsenault <arsenm2@gmail.com> wrote:<blockquote class="gmail_quote" style="margin: 0pt 0pt 0pt 0.8ex; border-left: 1px solid rgb(204, 204, 204); padding-left: 1ex;">
<pre class="k9mail"><br />On Jul 19, 2014, at 6:16 AM, Grigori Goronzy <greg@chown.ath.cx> wrote:<br /><br /><blockquote class="gmail_quote" style="margin: 0pt 0pt 1ex 0.8ex; border-left: 1px solid #729fcf; padding-left: 1ex;"> These instructions can only take a limited input range, and return<br /> the constant value 1 out of range. We should do range reduction to<br /> be able to process arbitrary values. Use a FRACT instruction after<br /> normalization to achieve this. Also add a test for constant folding<br /> with the lowered code with unsafe-fp-math enabled.<br /> <br /> v2: use DAG lowering instead of intrinsic, adapt test<br /> v3: calculate constant, fold pattern into instruction definition<br /> v4: misc style fixes, add sin-fold testcase, cosmetics<br /> ---<br /> lib/Target/R600/<a href="http://AMDGPUInstrInfo.td">AMDGPUInstrInfo.td</a> | 3 +++<br /> lib/Target/R600/SIISelLowering.cpp | 23 +++++++++++++++++++++++<br /> lib/Target/R600/SIISelLowering.h |!
1 +<br
/> lib/Target/R600/<a href="http://SIInstructions.td">SIInstructions.td</a> | 18 ++++++------------<br /> test/CodeGen/R600/llvm.sin.ll | 22 ++++++++++++++++++++--<br /> 5 files changed, 53 insertions(+), 14 deletions(-)<br /> <br /> diff --git a/lib/Target/R600/<a href="http://AMDGPUInstrInfo.td">AMDGPUInstrInfo.td</a> b/lib/Target/R600/<a href="http://AMDGPUInstrInfo.td">AMDGPUInstrInfo.td</a><br /> index 934d59d..820f1a8 100644<br /> --- a/lib/Target/R600/<a href="http://AMDGPUInstrInfo.td">AMDGPUInstrInfo.td</a><br /> +++ b/lib/Target/R600/<a href="http://AMDGPUInstrInfo.td">AMDGPUInstrInfo.td</a><br /> @@ -34,6 +34,9 @@ def AMDGPUDivScaleOp : SDTypeProfile<2, 3,<br /> // This argument to this node is a dword address.<br /> def AMDGPUdwordaddr : SDNode<"AMDGPUISD::DWORDADDR", SDTIntUnaryOp>;<br /> <br /> +def AMDGPUcos : SDNode<"AMDGPUISD::COS_HW", SDTFPUnaryOp>;<br /> +def AMDGPUsin : SDNode<"AMDGPUISD::SIN_HW", SDTFPUnaryOp>;<br /> +<br /> //!
out = a
- floor(a)<br /> def AMDGPUfract : SDNode<"AMDGPUISD::FRACT", SDTFPUnaryOp>;<br /> <br /> diff --git a/lib/Target/R600/SIISelLowering.cpp b/lib/Target/R600/SIISelLowering.cpp<br /> index b3429b9..86997c8 100644<br /> --- a/lib/Target/R600/SIISelLowering.cpp<br /> +++ b/lib/Target/R600/SIISelLowering.cpp<br /> @@ -80,6 +80,9 @@ SITargetLowering::SITargetLowering(TargetMachine &TM) :<br /> setOperationAction(ISD::SUBC, MVT::i32, Legal);<br /> setOperationAction(ISD::SUBE, MVT::i32, Legal);<br /> <br /> + setOperationAction(ISD::FSIN, MVT::f32, Custom);<br /> + setOperationAction(ISD::FCOS, MVT::f32, Custom);<br /> +<br /> // We need to custom lower vector stores from local memory<br /> setOperationAction(ISD::LOAD, MVT::v2i32, Custom);<br /> setOperationAction(ISD::LOAD, MVT::v4i32, Custom);<br /> @@ -637,6 +640,9 @@ SDValue SITargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {<br /> }<br /> }<br /> <br /> + case ISD::FSIN:<br!
/> +
case ISD::FCOS:<br /> + return LowerTrig(Op, DAG);<br /> case ISD::SELECT: return LowerSELECT(Op, DAG);<br /> case ISD::FDIV: return LowerFDIV(Op, DAG);<br /> case ISD::STORE: return LowerSTORE(Op, DAG);<br /> @@ -1116,6 +1122,23 @@ SDValue SITargetLowering::LowerSTORE(SDValue Op, SelectionDAG &DAG) const {<br /> return Chain;<br /> }<br /> <br /> +SDValue SITargetLowering::LowerTrig(SDValue Op, SelectionDAG &DAG) const {<br /> + EVT VT = Op.getValueType();<br /> + SDValue Arg = Op.getOperand(0);<br /> + SDValue FractPart = DAG.getNode(AMDGPUISD::FRACT, SDLoc(Op), VT,<br /> + DAG.getNode(ISD::FMUL, SDLoc(Op), VT, Arg,<br /> + DAG.getConstantFP(0.5 / M_PI, VT)));<br /> +<br /> + switch (Op.getOpcode()) {<br /> + case ISD::FCOS:<br /> + return DAG.getNode(AMDGPUISD::COS_HW, SDLoc(Op), VT, FractPart);<br /> + case ISD::FSIN:<br /> + return DAG.getNode(AMDGPUISD::SIN_HW, SDLoc(Op), VT, FractPart);<br /> + default:<br /> +
llvm_unreachable("Wrong trig opcode");<br /> + }<br /> +}<br /> +<br /> //<hr />//<br /> // Custom DAG optimizations<br /> //<hr />//<br /> diff --git a/lib/Target/R600/SIISelLowering.h b/lib/Target/R600/SIISelLowering.h<br /> index 9e9a0b0..b3343ee 100644<br /> --- a/lib/Target/R600/SIISelLowering.h<br /> +++ b/lib/Target/R600/SIISelLowering.h<br /> @@ -32,6 +32,7 @@ class SITargetLowering : public AMDGPUTargetLowering {<br /> SDValue LowerFDIV64(SDValue Op, SelectionDAG &DAG) const;<br /> SDValue LowerFDIV(SDValue Op, SelectionDAG &DAG) const;<br /> SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const;<br /> + SDValue LowerTrig(SDValue Op, SelectionDAG &DAG) const;<br /> SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const;<br /> <br /> bool foldImm(SDValue &Operand, int32_t &Immediate,<br /> diff --git a/lib/Target/R600/<a href="http://SIInstructions.td">SIInstructions.td</a> b/lib/Target/R600/<a
href="http://SIInstructions.td">SIInstructions.td</a><br /> index a4920db..bd5be32 100644<br /> --- a/lib/Target/R600/<a href="http://SIInstructions.td">SIInstructions.td</a><br /> +++ b/lib/Target/R600/<a href="http://SIInstructions.td">SIInstructions.td</a><br /> @@ -1167,8 +1167,12 @@ defm V_SQRT_F32 : VOP1_32 <0x00000033, "V_SQRT_F32",<br /> defm V_SQRT_F64 : VOP1_64 <0x00000034, "V_SQRT_F64",<br /> [(set f64:$dst, (fsqrt f64:$src0))]<br /><blockquote class="gmail_quote" style="margin: 0pt 0pt 1ex 0.8ex; border-left: 1px solid #ad7fa8; padding-left: 1ex;"> ;<br /></blockquote> -defm V_SIN_F32 : VOP1_32 <0x00000035, "V_SIN_F32", []>;<br /> -defm V_COS_F32 : VOP1_32 <0x00000036, "V_COS_F32", []>;<br /> +defm V_SIN_F32 : VOP1_32 <0x00000035, "V_SIN_F32",<br /> + [(set f32:$dst, (AMDGPUsin f32:$src0))]<br /> +>;<br /> +defm V_COS_F32 : VOP1_32 <0x00000036, "V_COS_F32",<br /> + [(set f32:$dst, (AMDGPUcos f32:$src0))]<br /> +>;<br /> defm V_NO!
T_B32 :
VOP1_32 <0x00000037, "V_NOT_B32", []>;<br /> defm V_BFREV_B32 : VOP1_32 <0x00000038, "V_BFREV_B32", []>;<br /> defm V_FFBH_U32 : VOP1_32 <0x00000039, "V_FFBH_U32", []>;<br /> @@ -2343,16 +2347,6 @@ def : Pat<<br /><blockquote class="gmail_quote" style="margin: 0pt 0pt 1ex 0.8ex; border-left: 1px solid #ad7fa8; padding-left: 1ex;"> ;<br /></blockquote> <br /> def : Pat <<br /> - (fcos f32:$src0),<br /> - (V_COS_F32_e32 (V_MUL_F32_e32 $src0, (V_MOV_B32_e32 CONST.TWO_PI_INV)))<br /> ->;<br /> -<br /> -def : Pat <<br /> - (fsin f32:$src0),<br /> - (V_SIN_F32_e32 (V_MUL_F32_e32 $src0, (V_MOV_B32_e32 CONST.TWO_PI_INV)))<br /> ->;<br /> -<br /> -def : Pat <<br /> (int_AMDGPU_cube v4f32:$src),<br /> (INSERT_SUBREG (INSERT_SUBREG (INSERT_SUBREG (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)),<br /> (V_CUBETC_F32 (EXTRACT_SUBREG $src, sub0),<br /> diff --git a/test/CodeGen/R600/llvm.sin.ll b/test/CodeGen/R600/llvm.sin.ll<br /> index 41c363c..53006!
ba
100644<br /> --- a/test/CodeGen/R600/llvm.sin.ll<br /> +++ b/test/CodeGen/R600/llvm.sin.ll<br /> @@ -1,5 +1,6 @@<br /> -;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s -check-prefix=EG -check-prefix=FUNC<br /> -;RUN: llc < %s -march=r600 -mcpu=SI | FileCheck %s -check-prefix=SI -check-prefix=FUNC<br /> +;RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s<br /> +;RUN: llc -march=r600 -mcpu=SI < %s | FileCheck -check-prefix=SI -check-prefix=SI-SAFE -check-prefix=FUNC %s<br /> +;RUN: llc -march=r600 -mcpu=SI -enable-unsafe-fp-math < %s | FileCheck -check-prefix=SI -check-prefix=SI-UNSAFE -check-prefix=FUNC %s<br /> <br /> ;FUNC-LABEL: test<br /> ;EG: MULADD_IEEE *<br /> @@ -8,6 +9,7 @@<br /> ;EG: SIN * T{{[0-9]+\.[XYZW], PV\.[XYZW]}}<br /> ;EG-NOT: SIN<br /> ;SI: V_MUL_F32<br /> +;SI: V_FRACT_F32<br /> ;SI: V_SIN_F32<br /> ;SI-NOT: V_SIN_F32<br /> <br /> @@ -17,6 +19,22 @@ define void @test(float addrspace(1)* %out,!
float
%x) #1 {<br /> ret void<br /> }<br /> <br /> +;FUNC-LABEL: testf<br /> +;SI-UNSAFE: 4.774<br /> +;SI-UNSAFE: V_MUL_F32<br /> +;SI-SAFE: V_MUL_F32<br /> +;SI-SAFE: V_MUL_F32<br /> +;SI: V_FRACT_F32<br /> +;SI: V_SIN_F32<br /> +;SI-NOT: V_SIN_F32<br /> +<br /> +define void @testf(float addrspace(1)* %out, float %x) #1 {<br /> + %y = fmul float 3.0, %x<br /> + %sin = call float @llvm.sin.f32(float %y)<br /> + store float %sin, float addrspace(1)* %out<br /> + ret void<br /> +}<br /> +<br /> ;FUNC-LABEL: testv<br /> ;EG: SIN * T{{[0-9]+\.[XYZW], PV\.[XYZW]}}<br /> ;EG: SIN * T{{[0-9]+\.[XYZW], PV\.[XYZW]}}<br /> -- <br /> <a href="http://1.8.3.2">1.8.3.2</a><br /></blockquote><br />Do you need me to commit this for you?</pre></blockquote></div><br>
-- <br>
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