<html><head><meta http-equiv="Content-Type" content="text/html charset=windows-1252"></head><body style="word-wrap: break-word; -webkit-nbsp-mode: space; -webkit-line-break: after-white-space;"><div></div><div><br><div><blockquote type="cite"><div>On Jul 10, 2014, at 10:59 AM, Benjamin Kramer <<a href="mailto:benny.kra@gmail.com">benny.kra@gmail.com</a>> wrote:</div><br class="Apple-interchange-newline"><div><br style="font-family: Helvetica; font-size: 12px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; orphans: auto; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; widows: auto; word-spacing: 0px; -webkit-text-stroke-width: 0px;"><span style="font-family: Helvetica; font-size: 12px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; orphans: auto; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; widows: auto; word-spacing: 0px; -webkit-text-stroke-width: 0px; float: none; display: inline !important;">On 10.07.2014, at 19:46, Quentin Colombet <</span><a href="mailto:qcolombet@apple.com" style="font-family: Helvetica; font-size: 12px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; orphans: auto; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; widows: auto; word-spacing: 0px; -webkit-text-stroke-width: 0px;">qcolombet@apple.com</a><span style="font-family: Helvetica; font-size: 12px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; orphans: auto; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; widows: auto; word-spacing: 0px; -webkit-text-stroke-width: 0px; float: none; display: inline !important;">> wrote:</span><br style="font-family: Helvetica; font-size: 12px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; orphans: auto; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; widows: auto; word-spacing: 0px; -webkit-text-stroke-width: 0px;"><br style="font-family: Helvetica; font-size: 12px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; orphans: auto; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; widows: auto; word-spacing: 0px; -webkit-text-stroke-width: 0px;"><blockquote type="cite" style="font-family: Helvetica; font-size: 12px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; orphans: auto; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; widows: auto; word-spacing: 0px; -webkit-text-stroke-width: 0px;">Hi Benjamin,<br><br>I have narrowed down a failure of the factor test case (from the llvm test-suite: SingleSource/UnitTests/SignlessTypes) to this commit.<br><br>The failure happens at Os on a haswell machine running macosx.<br><br>I have reduced the problem to the attached test.ll and I proposed to fix that with the attached patch.<br>Basically the masks for the shuffle are wrong for vectors with 8 elements.<br><br>** To Reproduce **<br><br>Basically this test takes 8 numbers: 8, 9, …, 15 and divide each of them by 7 and print the result.<br><br>On a haswell machine<br>llc -mattr=-avx2 test.ll -o ok.s<br>llc -mattr=+avx2 test.ll -o ko.s<br><br>clang ok.s -arch x86_64 -o ok.out<br>clang ko.s -arch x86_64 -march core-avx2 -o ko.out<br><br>./ok.out<br>1<br>1<br>1<br>1<br>1<br>1<br>2<br>2<br><br><br>./ko.out<br>1<br>1<br>1<br>1<br>1<br>1<br>1 <-- 14/7 == 1!!!<br>2<br><br>** Feedback Needed **<br><br>Could you review the attached patch?<br><br>Moreover, because of this patch, vector-idiv.ll is failing. To me the output seems reasonable but could you take a look?<br>I’ll update the patch to match the new pattern if they are fine.<br></blockquote><br style="font-family: Helvetica; font-size: 12px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; orphans: auto; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; widows: auto; word-spacing: 0px; -webkit-text-stroke-width: 0px;"><span style="font-family: Helvetica; font-size: 12px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; orphans: auto; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; widows: auto; word-spacing: 0px; -webkit-text-stroke-width: 0px; float: none; display: inline !important;">Your patch is correct, and vector-idiv.ll was buggy. I think this bug is already fixed with r212611 (the shufflemasks I had in place for AVX2 were completely bogus, I should've noticed this earlier). However, I like the effort that you put into documenting the lowering with verbose comments. Would you mind rebasing them on top of r212611?</span><br style="font-family: Helvetica; font-size: 12px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; orphans: auto; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; widows: auto; word-spacing: 0px; -webkit-text-stroke-width: 0px;"><br style="font-family: Helvetica; font-size: 12px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; orphans: auto; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; widows: auto; word-spacing: 0px; -webkit-text-stroke-width: 0px;"><span style="font-family: Helvetica; font-size: 12px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; orphans: auto; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; widows: auto; word-spacing: 0px; -webkit-text-stroke-width: 0px; float: none; display: inline !important;">Really sorry that you had to spent so much time on this silly oversight of mine.</span><br style="font-family: Helvetica; font-size: 12px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; orphans: auto; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; widows: auto; word-spacing: 0px; -webkit-text-stroke-width: 0px;"><span style="font-family: Helvetica; font-size: 12px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; orphans: auto; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; widows: auto; word-spacing: 0px; -webkit-text-stroke-width: 0px; float: none; display: inline !important;">- Ben</span><br style="font-family: Helvetica; font-size: 12px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; orphans: auto; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; widows: auto; word-spacing: 0px; -webkit-text-stroke-width: 0px;"><br style="font-family: Helvetica; font-size: 12px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; orphans: auto; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; widows: auto; word-spacing: 0px; -webkit-text-stroke-width: 0px;"><blockquote type="cite" style="font-family: Helvetica; font-size: 12px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; orphans: auto; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; widows: auto; word-spacing: 0px; -webkit-text-stroke-width: 0px;"><br>Thanks,<br>-Quentin<br><lower_mullohi.patch><test.ll><br><br>This commit (and more generally the custom lowering of MUL_LOHI)<span class="Apple-converted-space"> </span><br><blockquote type="cite">On May 2, 2014, at 5:42 AM, Benjamin Kramer <<a href="mailto:benny.kra@gmail.com">benny.kra@gmail.com</a>> wrote:<br><br><br>On 02.05.2014, at 13:48, Patrik Hägglund H <<a href="mailto:patrik.h.hagglund@ericsson.com">patrik.h.hagglund@ericsson.com</a>> wrote:<br><br><blockquote type="cite">Hi Benjamin,<br><br>This commit is causing a regression for an llvm-stress test, as shown below.<br></blockquote><br>r207835 fixes the crash. Thanks for the test case!<br><br>- Ben<br><br><blockquote type="cite"><br>/Patrik Hägglund<br><br>bin/llvm-stress -size 185 -seed 7564 | bin/llc -march=x86-64 -mcpu=corei7 -o /dev/null<br><br>llc: ../lib/CodeGen/SelectionDAG/SelectionDAG.cpp:5728: void llvm::SelectionDAG::ReplaceAllUsesWith(llvm::SDNode *, llvm::SDNode *): Assertion `(!From->hasAnyUseOfValue(i) || From->getValueType(i) == To->getValueType(i)) && "Cannot use this version of ReplaceAllUsesWith!"' failed.<br>0 llc 0x00000000010b5a55 llvm::sys::PrintStackTrace(_IO_FILE*) + 37<br>1 llc 0x00000000010b5e93<br>2 libpthread.so.0 0x00007f7d65bcb7c0<br>3 libc.so.6 0x00007f7d64ecfb35 gsignal + 53<br>4 libc.so.6 0x00007f7d64ed1111 abort + 385<br>5 libc.so.6 0x00007f7d64ec89f0 __assert_fail + 240<br>6 llc 0x0000000000f3a524<br>7 llc 0x0000000000ec4e45 llvm::SelectionDAG::Combine(llvm::CombineLevel, llvm::AliasAnalysis&, llvm::CodeGenOpt::Level) + 1573<br>8 llc 0x0000000000fad035 llvm::SelectionDAGISel::CodeGenAndEmitDAG() + 901<br>9 llc 0x0000000000fac368 llvm::SelectionDAGISel::SelectAllBasicBlocks(llvm::Function const&) + 6504<br>10 llc 0x0000000000fa9c64 llvm::SelectionDAGISel::runOnMachineFunction(llvm::MachineFunction&) + 1332<br>11 llc 0x0000000000c3261c llvm::MachineFunctionPass::runOnFunction(llvm::Function&) + 124<br>12 llc 0x0000000000e1f20a llvm::FPPassManager::runOnFunction(llvm::Function&) + 362<br>13 llc 0x0000000000e1f49b llvm::FPPassManager::runOnModule(llvm::Module&) + 43<br>14 llc 0x0000000000e1fa37 llvm::legacy::PassManagerImpl::run(llvm::Module&) + 999<br>15 llc 0x000000000056d835 main + 6549<br>16 libc.so.6 0x00007f7d64ebbc16 __libc_start_main + 230<br>17 llc 0x000000000056bdb9<br>Stack dump:<br>0. Program arguments: bin/llc -march=x86-64 -mcpu=corei7 -o /dev/null<br>1. Running pass 'Function Pass Manager' on module '<stdin>'.<br>2. Running pass 'X86 DAG->DAG Instruction Selection' on function '@autogen_SD7564'<br>Abort<br><br><br>-----Original Message-----<br>From: <a href="mailto:llvm-commits-bounces@cs.uiuc.edu">llvm-commits-bounces@cs.uiuc.edu</a> [<a href="mailto:llvm-commits-bounces@cs.uiuc.edu">mailto:llvm-commits-bounces@cs.uiuc.edu</a>] On Behalf Of Benjamin Kramer<br>Sent: den 27 april 2014 01:10<br>To: <a href="mailto:llvm-commits@cs.uiuc.edu">llvm-commits@cs.uiuc.edu</a><br>Subject: [llvm] r207338 - DAGCombiner: Simplify code a bit, make more transforms work with vectors.<br><br>Author: d0k<br>Date: Sat Apr 26 18:09:49 2014<br>New Revision: 207338<br><br>URL: <a href="http://llvm.org/viewvc/llvm-project?rev=207338&view=rev">http://llvm.org/viewvc/llvm-project?rev=207338&view=rev</a><br>Log:<br>DAGCombiner: Simplify code a bit, make more transforms work with vectors.<br><br>Modified:<br>llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp<br>llvm/trunk/test/CodeGen/X86/vector-idiv.ll<br><br>Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp<br>URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=207338&r1=207337&r2=207338&view=diff">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=207338&r1=207337&r2=207338&view=diff</a><br>==============================================================================<br>--- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original)<br>+++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Sat Apr 26 18:09:49 2014<br>@@ -644,8 +644,13 @@ static ConstantSDNode *isConstOrConstSpl<br>if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N))<br> return CN;<br><br>- if (BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(N))<br>- return BV->getConstantSplatValue();<br>+ if (BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(N)) {<br>+ ConstantSDNode *CN = BV->getConstantSplatValue();<br>+<br>+ // BuildVectors can truncate their operands. Ignore that case here.<br>+ if (CN && CN->getValueType(0) == N.getValueType().getScalarType())<br>+ return CN;<br>+ }<br><br>return nullptr;<br>}<br>@@ -1957,8 +1962,8 @@ SDValue DAGCombiner::visitMUL(SDNode *N)<br>SDValue DAGCombiner::visitSDIV(SDNode *N) {<br>SDValue N0 = N->getOperand(0);<br>SDValue N1 = N->getOperand(1);<br>- ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode());<br>- ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode());<br>+ ConstantSDNode *N0C = isConstOrConstSplat(N0);<br>+ ConstantSDNode *N1C = isConstOrConstSplat(N1);<br>EVT VT = N->getValueType(0);<br><br>// fold vector ops<br>@@ -1985,25 +1990,15 @@ SDValue DAGCombiner::visitSDIV(SDNode *N<br> N0, N1);<br>}<br><br>- const APInt *Divisor = nullptr;<br>- if (N1C) {<br>- Divisor = &N1C->getAPIntValue();<br>- } else if (N1.getValueType().isVector() &&<br>- N1->getOpcode() == ISD::BUILD_VECTOR) {<br>- BuildVectorSDNode *BV = cast<BuildVectorSDNode>(N->getOperand(1));<br>- if (ConstantSDNode *C = BV->getConstantSplatValue())<br>- Divisor = &C->getAPIntValue();<br>- }<br>-<br>// fold (sdiv X, pow2) -> simple ops after legalize<br>- if (Divisor && !!*Divisor &&<br>- (Divisor->isPowerOf2() || (-*Divisor).isPowerOf2())) {<br>+ if (N1C && !N1C->isNullValue() && (N1C->getAPIntValue().isPowerOf2() ||<br>+ (-N1C->getAPIntValue()).isPowerOf2())) {<br> // If dividing by powers of two is cheap, then don't perform the following<br> // fold.<br> if (TLI.isPow2DivCheap())<br> return SDValue();<br><br>- unsigned lg2 = Divisor->countTrailingZeros();<br>+ unsigned lg2 = N1C->getAPIntValue().countTrailingZeros();<br><br> // Splat the sign bit into the register<br> SDValue SGN =<br>@@ -2025,7 +2020,7 @@ SDValue DAGCombiner::visitSDIV(SDNode *N<br><br> // If we're dividing by a positive value, we're done. Otherwise, we must<br> // negate the result.<br>- if (Divisor->isNonNegative())<br>+ if (N1C->getAPIntValue().isNonNegative())<br> return SRA;<br><br> AddToWorkList(SRA.getNode());<br>@@ -2034,7 +2029,7 @@ SDValue DAGCombiner::visitSDIV(SDNode *N<br><br>// if integer divide is expensive and we satisfy the requirements, emit an<br>// alternate sequence.<br>- if ((N1C || N1->getOpcode() == ISD::BUILD_VECTOR) && !TLI.isIntDivCheap()) {<br>+ if (N1C && !TLI.isIntDivCheap()) {<br> SDValue Op = BuildSDIV(N);<br> if (Op.getNode()) return Op;<br>}<br>@@ -2052,8 +2047,8 @@ SDValue DAGCombiner::visitSDIV(SDNode *N<br>SDValue DAGCombiner::visitUDIV(SDNode *N) {<br>SDValue N0 = N->getOperand(0);<br>SDValue N1 = N->getOperand(1);<br>- ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode());<br>- ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode());<br>+ ConstantSDNode *N0C = isConstOrConstSplat(N0);<br>+ ConstantSDNode *N1C = isConstOrConstSplat(N1);<br>EVT VT = N->getValueType(0);<br><br>// fold vector ops<br>@@ -2086,7 +2081,7 @@ SDValue DAGCombiner::visitUDIV(SDNode *N<br> }<br>}<br>// fold (udiv x, c) -> alternate<br>- if ((N1C || N1->getOpcode() == ISD::BUILD_VECTOR) && !TLI.isIntDivCheap()) {<br>+ if (N1C && !TLI.isIntDivCheap()) {<br> SDValue Op = BuildUDIV(N);<br> if (Op.getNode()) return Op;<br>}<br>@@ -2104,8 +2099,8 @@ SDValue DAGCombiner::visitUDIV(SDNode *N<br>SDValue DAGCombiner::visitSREM(SDNode *N) {<br>SDValue N0 = N->getOperand(0);<br>SDValue N1 = N->getOperand(1);<br>- ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);<br>- ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);<br>+ ConstantSDNode *N0C = isConstOrConstSplat(N0);<br>+ ConstantSDNode *N1C = isConstOrConstSplat(N1);<br>EVT VT = N->getValueType(0);<br><br>// fold (srem c1, c2) -> c1%c2<br>@@ -2146,8 +2141,8 @@ SDValue DAGCombiner::visitSREM(SDNode *N<br>SDValue DAGCombiner::visitUREM(SDNode *N) {<br>SDValue N0 = N->getOperand(0);<br>SDValue N1 = N->getOperand(1);<br>- ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);<br>- ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);<br>+ ConstantSDNode *N0C = isConstOrConstSplat(N0);<br>+ ConstantSDNode *N1C = isConstOrConstSplat(N1);<br>EVT VT = N->getValueType(0);<br><br>// fold (urem c1, c2) -> c1%c2<br>@@ -11187,28 +11182,20 @@ SDValue DAGCombiner::SimplifySetCC(EVT V<br>/// multiplying by a magic number. See:<br>/// <<a href="http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html">http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html</a>><br>SDValue DAGCombiner::BuildSDIV(SDNode *N) {<br>- const APInt *Divisor;<br>- if (N->getValueType(0).isVector()) {<br>- // Handle splat vectors.<br>- BuildVectorSDNode *BV = cast<BuildVectorSDNode>(N->getOperand(1));<br>- if (ConstantSDNode *C = BV->getConstantSplatValue())<br>- Divisor = &C->getAPIntValue();<br>- else<br>- return SDValue();<br>- } else {<br>- Divisor = &cast<ConstantSDNode>(N->getOperand(1))->getAPIntValue();<br>- }<br>+ ConstantSDNode *C = isConstOrConstSplat(N->getOperand(1));<br>+ if (!C)<br>+ return SDValue();<br><br>// Avoid division by zero.<br>- if (!*Divisor)<br>+ if (!C->getAPIntValue())<br> return SDValue();<br><br>std::vector<SDNode*> Built;<br>- SDValue S = TLI.BuildSDIV(N, *Divisor, DAG, LegalOperations, &Built);<br>+ SDValue S =<br>+ TLI.BuildSDIV(N, C->getAPIntValue(), DAG, LegalOperations, &Built);<br><br>- for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end();<br>- ii != ee; ++ii)<br>- AddToWorkList(*ii);<br>+ for (SDNode *N : Built)<br>+ AddToWorkList(N);<br>return S;<br>}<br><br>@@ -11217,28 +11204,20 @@ SDValue DAGCombiner::BuildSDIV(SDNode *N<br>/// multiplying by a magic number. See:<br>/// <<a href="http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html">http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html</a>><br>SDValue DAGCombiner::BuildUDIV(SDNode *N) {<br>- const APInt *Divisor;<br>- if (N->getValueType(0).isVector()) {<br>- // Handle splat vectors.<br>- BuildVectorSDNode *BV = cast<BuildVectorSDNode>(N->getOperand(1));<br>- if (ConstantSDNode *C = BV->getConstantSplatValue())<br>- Divisor = &C->getAPIntValue();<br>- else<br>- return SDValue();<br>- } else {<br>- Divisor = &cast<ConstantSDNode>(N->getOperand(1))->getAPIntValue();<br>- }<br>+ ConstantSDNode *C = isConstOrConstSplat(N->getOperand(1));<br>+ if (!C)<br>+ return SDValue();<br><br>// Avoid division by zero.<br>- if (!*Divisor)<br>+ if (!C->getAPIntValue())<br> return SDValue();<br><br>std::vector<SDNode*> Built;<br>- SDValue S = TLI.BuildUDIV(N, *Divisor, DAG, LegalOperations, &Built);<br>+ SDValue S =<br>+ TLI.BuildUDIV(N, C->getAPIntValue(), DAG, LegalOperations, &Built);<br><br>- for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end();<br>- ii != ee; ++ii)<br>- AddToWorkList(*ii);<br>+ for (SDNode *N : Built)<br>+ AddToWorkList(N);<br>return S;<br>}<br><br><br>Modified: llvm/trunk/test/CodeGen/X86/vector-idiv.ll<br>URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/vector-idiv.ll?rev=207338&r1=207337&r2=207338&view=diff">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/vector-idiv.ll?rev=207338&r1=207337&r2=207338&view=diff</a><br>==============================================================================<br>--- llvm/trunk/test/CodeGen/X86/vector-idiv.ll (original)<br>+++ llvm/trunk/test/CodeGen/X86/vector-idiv.ll Sat Apr 26 18:09:49 2014<br>@@ -151,3 +151,38 @@ define <8 x i32> @test9(<8 x i32> %a) {<br>; AVX: vpsrad $2<br>; AVX: vpadd<br>}<br>+<br>+define <8 x i32> @test10(<8 x i32> %a) {<br>+ %rem = urem <8 x i32> %a, <i32 7, i32 7, i32 7, i32 7,i32 7, i32 7, i32 7, i32 7><br>+ ret <8 x i32> %rem<br>+<br>+; AVX-LABEL: test10:<br>+; AVX: vpermd<br>+; AVX: vpmuludq<br>+; AVX: vshufps<span class="Apple-tab-span" style="white-space: pre;"> </span>$-35<br>+; AVX: vpmuludq<br>+; AVX: vshufps<span class="Apple-tab-span" style="white-space: pre;"> </span>$-35<br>+; AVX: vpsubd<br>+; AVX: vpsrld $1<br>+; AVX: vpadd<br>+; AVX: vpsrld $2<br>+; AVX: vpmulld<br>+}<br>+<br>+define <8 x i32> @test11(<8 x i32> %a) {<br>+ %rem = srem <8 x i32> %a, <i32 7, i32 7, i32 7, i32 7,i32 7, i32 7, i32 7, i32 7><br>+ ret <8 x i32> %rem<br>+<br>+; AVX-LABEL: test11:<br>+; AVX: vpermd<br>+; AVX: vpmuldq<br>+; AVX: vshufps<span class="Apple-tab-span" style="white-space: pre;"> </span>$-35<br>+; AVX: vpmuldq<br>+; AVX: vshufps<span class="Apple-tab-span" style="white-space: pre;"> </span>$-35<br>+; AVX: vpshufd<span class="Apple-tab-span" style="white-space: pre;"> </span>$-40<br>+; AVX: vpadd<br>+; AVX: vpsrld $31<br>+; AVX: vpsrad $2<br>+; AVX: vpadd<br>+; AVX: vpmulld<br>+}<br><br><br>_______________________________________________<br>llvm-commits mailing list<br><a href="mailto:llvm-commits@cs.uiuc.edu">llvm-commits@cs.uiuc.edu</a><br>http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits<br></blockquote><br><br>_______________________________________________<br>llvm-commits mailing list<br><a href="mailto:llvm-commits@cs.uiuc.edu">llvm-commits@cs.uiuc.edu</a><br>http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits</blockquote></blockquote></div></blockquote></div><br></div></body></html>