<html><head><meta http-equiv="Content-Type" content="text/html charset=us-ascii"></head><body style="word-wrap: break-word; -webkit-nbsp-mode: space; -webkit-line-break: after-white-space;"><div><br></div><div>Hi,</div><div><br></div><div>I implemented a pass for a late machine instruction combiner that may replace an instruction sequence by combined instruction(s) when it is beneficial to do so. It provides the infrastructure to evaluate instruction combining patterns like mul+add->madd based on machine trace information. Currently the DAG Combiner greedily generates combined instructions, which usually is a win for code size, but unfortunately can cause performance losses. To remedy this the new pass changes the logic from always generate combined instruction(s) to only do so when beneficial.</div><div><br></div><div><br></div><div>The design choice was driven by the desire to make it simple to a) add new pattern and b) add support for machine combining in a target. Consequently the combiner pass comes in 3 patches: First, the target independent driver that walks all instructions of a basic block, asks the target for possible combiner pattern, evaluates each pattern by having the target generate the instruction sequence represented by the pattern and finally replaces the old code when the new sequence is more efficient. The pattern and the new code sequence are opaque to the driver. Second, the target dependent code which currently supports only AArch64: for a given instruction it records the possible combiner pattern and on demand generates the instruction sequence it represents. Third, optional dumps the critical path length for tuning support.</div><div><br></div><div><br></div><div>* The patches</div><div><br></div><div>1) Target independent</div><div></div></body></html>