<div dir="ltr"><div>I thought we sort of had a desire to move away from intrinsics for things that could be represented natively.</div><div><br></div>I think you still need a clang patch to get them for "free". But there's no feature flag checks on builtins until backend lowering which is confusing and leads us to encourage the use of the header files.</div>
<div class="gmail_extra"><br><br><div class="gmail_quote">On Wed, Jun 25, 2014 at 8:54 AM, Chandler Carruth <span dir="ltr"><<a href="mailto:chandlerc@gmail.com" target="_blank">chandlerc@gmail.com</a>></span> wrote:<br>
<blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"><div dir="ltr"><div class="gmail_extra"><div class="gmail_quote"><div class="">On Wed, Jun 25, 2014 at 5:18 PM, Craig Topper <span dir="ltr"><<a href="mailto:craig.topper@gmail.com" target="_blank">craig.topper@gmail.com</a>></span> wrote:<br>
<blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"><div dir="ltr">What's the motivation? Can't these be represented with appropriate shufflevector indices?</div>
</blockquote>
<div><br></div></div><div>My motivation is testing, nothing more.</div><div><br></div><div>They can certainly be represented with appropriate shufflevector instructions, but then those go through the entire generic combiner and lowering which makes testing the target-specific combines quite a bit harder (the independent ones almost always nuke them).</div>
<div><br></div><div>It also seems nice to support them as GCC documents the builtins and this get's us those builtins for "free".</div><div><div class="h5"><div> </div><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">
<div class="gmail_extra"><div><div><br><br><div class="gmail_quote">On Wed, Jun 25, 2014 at 6:12 AM, Chandler Carruth <span dir="ltr"><<a href="mailto:chandlerc@gmail.com" target="_blank">chandlerc@gmail.com</a>></span> wrote:<br>
<blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">Author: chandlerc<br>
Date: Wed Jun 25 08:12:54 2014<br>
New Revision: 211694<br>
<br>
URL: <a href="http://llvm.org/viewvc/llvm-project?rev=211694&view=rev" target="_blank">http://llvm.org/viewvc/llvm-project?rev=211694&view=rev</a><br>
Log:<br>
[x86] Add intrinsics for the pshufd, pshuflw, and pshufhw instructions.<br>
<br>
Modified:<br>
llvm/trunk/include/llvm/IR/IntrinsicsX86.td<br>
llvm/trunk/lib/Target/X86/X86ISelLowering.cpp<br>
llvm/trunk/test/CodeGen/X86/sse2-intrinsics-x86.ll<br>
<br>
Modified: llvm/trunk/include/llvm/IR/IntrinsicsX86.td<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/IR/IntrinsicsX86.td?rev=211694&r1=211693&r2=211694&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/IR/IntrinsicsX86.td?rev=211694&r1=211693&r2=211694&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/include/llvm/IR/IntrinsicsX86.td (original)<br>
+++ llvm/trunk/include/llvm/IR/IntrinsicsX86.td Wed Jun 25 08:12:54 2014<br>
@@ -667,6 +667,15 @@ let TargetPrefix = "x86" in { // All in<br>
def int_x86_ssse3_pshuf_b_128 : GCCBuiltin<"__builtin_ia32_pshufb128">,<br>
Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty,<br>
llvm_v16i8_ty], [IntrNoMem]>;<br>
+ def int_x86_sse2_pshuf_d : GCCBuiltin<"__builtin_ia32_pshufd">,<br>
+ Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_i8_ty],<br>
+ [IntrNoMem]>;<br>
+ def int_x86_sse2_pshufl_w : GCCBuiltin<"__builtin_ia32_pshuflw">,<br>
+ Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty, llvm_i8_ty],<br>
+ [IntrNoMem]>;<br>
+ def int_x86_sse2_pshufh_w : GCCBuiltin<"__builtin_ia32_pshufhw">,<br>
+ Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty, llvm_i8_ty],<br>
+ [IntrNoMem]>;<br>
def int_x86_sse_pshuf_w : GCCBuiltin<"__builtin_ia32_pshufw">,<br>
Intrinsic<[llvm_x86mmx_ty], [llvm_x86mmx_ty, llvm_i8_ty],<br>
[IntrNoMem]>;<br>
<br>
Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=211694&r1=211693&r2=211694&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=211694&r1=211693&r2=211694&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)<br>
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Wed Jun 25 08:12:54 2014<br>
@@ -12660,6 +12660,18 @@ static SDValue LowerINTRINSIC_WO_CHAIN(S<br>
return DAG.getNode(X86ISD::PSHUFB, dl, Op.getValueType(),<br>
Op.getOperand(1), Op.getOperand(2));<br>
<br>
+ case Intrinsic::x86_sse2_pshuf_d:<br>
+ return DAG.getNode(X86ISD::PSHUFD, dl, Op.getValueType(),<br>
+ Op.getOperand(1), Op.getOperand(2));<br>
+<br>
+ case Intrinsic::x86_sse2_pshufl_w:<br>
+ return DAG.getNode(X86ISD::PSHUFLW, dl, Op.getValueType(),<br>
+ Op.getOperand(1), Op.getOperand(2));<br>
+<br>
+ case Intrinsic::x86_sse2_pshufh_w:<br>
+ return DAG.getNode(X86ISD::PSHUFHW, dl, Op.getValueType(),<br>
+ Op.getOperand(1), Op.getOperand(2));<br>
+<br>
case Intrinsic::x86_ssse3_psign_b_128:<br>
case Intrinsic::x86_ssse3_psign_w_128:<br>
case Intrinsic::x86_ssse3_psign_d_128:<br>
<br>
Modified: llvm/trunk/test/CodeGen/X86/sse2-intrinsics-x86.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/sse2-intrinsics-x86.ll?rev=211694&r1=211693&r2=211694&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/sse2-intrinsics-x86.ll?rev=211694&r1=211693&r2=211694&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/X86/sse2-intrinsics-x86.ll (original)<br>
+++ llvm/trunk/test/CodeGen/X86/sse2-intrinsics-x86.ll Wed Jun 25 08:12:54 2014<br>
@@ -717,3 +717,30 @@ define void @test_x86_sse2_pause() {<br>
ret void<br>
}<br>
declare void @llvm.x86.sse2.pause() nounwind<br>
+<br>
+define <4 x i32> @test_x86_sse2_pshuf_d(<4 x i32> %a) {<br>
+; CHECK-LABEL: test_x86_sse2_pshuf_d:<br>
+; CHECK: pshufd $27<br>
+entry:<br>
+ %res = call <4 x i32> @llvm.x86.sse2.pshuf.d(<4 x i32> %a, i8 27) nounwind readnone<br>
+ ret <4 x i32> %res<br>
+}<br>
+declare <4 x i32> @llvm.x86.sse2.pshuf.d(<4 x i32>, i8) nounwind readnone<br>
+<br>
+define <8 x i16> @test_x86_sse2_pshufl_w(<8 x i16> %a) {<br>
+; CHECK-LABEL: test_x86_sse2_pshufl_w:<br>
+; CHECK: pshuflw $27<br>
+entry:<br>
+ %res = call <8 x i16> @llvm.x86.sse2.pshufl.w(<8 x i16> %a, i8 27) nounwind readnone<br>
+ ret <8 x i16> %res<br>
+}<br>
+declare <8 x i16> @llvm.x86.sse2.pshufl.w(<8 x i16>, i8) nounwind readnone<br>
+<br>
+define <8 x i16> @test_x86_sse2_pshufh_w(<8 x i16> %a) {<br>
+; CHECK-LABEL: test_x86_sse2_pshufh_w:<br>
+; CHECK: pshufhw $27<br>
+entry:<br>
+ %res = call <8 x i16> @llvm.x86.sse2.pshufh.w(<8 x i16> %a, i8 27) nounwind readnone<br>
+ ret <8 x i16> %res<br>
+}<br>
+declare <8 x i16> @llvm.x86.sse2.pshufh.w(<8 x i16>, i8) nounwind readnone<br>
<br>
<br>
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</blockquote></div><br><br clear="all"><div><br></div></div></div><span><font color="#888888">-- <br>~Craig
</font></span></div>
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<br></blockquote></div></div></div><br></div></div>
</blockquote></div><br><br clear="all"><div><br></div>-- <br>~Craig
</div>