<html><head><meta http-equiv="Content-Type" content="text/html charset=windows-1252"></head><body style="word-wrap: break-word; -webkit-nbsp-mode: space; -webkit-line-break: after-white-space;"><br><div><div>On Jun 22, 2014, at 12:49 PM, Jan Vesely <<a href="mailto:jan.vesely@rutgers.edu">jan.vesely@rutgers.edu</a>> wrote:</div><br class="Apple-interchange-newline"><blockquote type="cite"><div style="font-size: 12px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; orphans: auto; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; widows: auto; word-spacing: 0px; -webkit-text-stroke-width: 0px;">On Sat, 2014-06-21 at 18:05 -0700, Matt Arsenault wrote:<br><blockquote type="cite">On Jun 21, 2014, at 4:24 PM, Jan Vesely <<a href="mailto:jan.vesely@rutgers.edu">jan.vesely@rutgers.edu</a>> wrote:<br><br><blockquote type="cite">Signed-off-by: Jan Vesely <<a href="mailto:jan.vesely@rutgers.edu">jan.vesely@rutgers.edu</a>><br>---<br><br>I'm not sure about the SDIV/SREM24 versions, but the comment suggested<br>they are unused anyway.<br></blockquote><br>It wouldn’t be hard to get these to work again, it just requires<br>changing the type check with a range check based on computeMaskedBits<br>for the operands. I would rather fix that instead of deleting these<br>(unless these don’t actually end up emitting better code than the<br>normal implementation)<br></blockquote><br>I don't think these have a chance of generating better code than 32bit<br>path. There might be some minor optimizations in the intro before<br>URECIP, but after that instruction all information about known 1s/0s<br>don't help anymore.<br>I think if there's any chance of lowering nodes based on known bits,<br>it's better handled in later in combining after the divrem node has been<br>legalized.<br><br>If you prefer too keep them around anyway, I can drop this patch from<br>the series.<br><br>regards,<br>jan<br><br><br></div></blockquote><div><br></div><div>I think the (maybe) advantages of the 24-bit path are the tricks involve the floating point instructions, not necessarily standard simplification of bits. I think it would be hard to reconstruct that information later. After you push your other patches I can check if this actually ends up producing shorter code or not</div><div><br></div><br><blockquote type="cite"><div style="font-size: 12px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; orphans: auto; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; widows: auto; word-spacing: 0px; -webkit-text-stroke-width: 0px;"><blockquote type="cite"><br><blockquote type="cite"><br>lib/Target/R600/AMDGPUISelLowering.cpp | 247 ---------------------------------<br>lib/Target/R600/AMDGPUISelLowering.h | 7 -<br>2 files changed, 254 deletions(-)<br><br>diff --git a/lib/Target/R600/AMDGPUISelLowering.cpp b/lib/Target/R600/AMDGPUISelLowering.cpp<br>index f473d1d..0dabbdd 100644<br>--- a/lib/Target/R600/AMDGPUISelLowering.cpp<br>+++ b/lib/Target/R600/AMDGPUISelLowering.cpp<br>@@ -296,7 +296,6 @@ AMDGPUTargetLowering::AMDGPUTargetLowering(TargetMachine &TM) :<br> setOperationAction(ISD::SUB, VT, Expand);<br> setOperationAction(ISD::SINT_TO_FP, VT, Expand);<br> setOperationAction(ISD::UINT_TO_FP, VT, Expand);<br>- // TODO: Implement custom UREM / SREM routines.<br> setOperationAction(ISD::SDIV, VT, Expand);<br> setOperationAction(ISD::UDIV, VT, Expand);<br> setOperationAction(ISD::SREM, VT, Expand);<br>@@ -507,8 +506,6 @@ SDValue AMDGPUTargetLowering::LowerOperation(SDValue Op,<br> case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op, DAG);<br> case ISD::FrameIndex: return LowerFrameIndex(Op, DAG);<br> case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);<br>- case ISD::SDIV: return LowerSDIV(Op, DAG);<br>- case ISD::SREM: return LowerSREM(Op, DAG);<br> case ISD::UDIVREM: return LowerUDIVREM(Op, DAG);<br> case ISD::SDIVREM: return LowerSDIVREM(Op, DAG);<br> case ISD::FCEIL: return LowerFCEIL(Op, DAG);<br>@@ -1296,250 +1293,6 @@ SDValue AMDGPUTargetLowering::LowerSTORE(SDValue Op, SelectionDAG &DAG) const {<br> return SDValue();<br>}<br><br>-SDValue AMDGPUTargetLowering::LowerSDIV24(SDValue Op, SelectionDAG &DAG) const {<br>- SDLoc DL(Op);<br>- EVT OVT = Op.getValueType();<br>- SDValue LHS = Op.getOperand(0);<br>- SDValue RHS = Op.getOperand(1);<br>- MVT INTTY;<br>- MVT FLTTY;<br>- if (!OVT.isVector()) {<br>- INTTY = MVT::i32;<br>- FLTTY = MVT::f32;<br>- } else if (OVT.getVectorNumElements() == 2) {<br>- INTTY = MVT::v2i32;<br>- FLTTY = MVT::v2f32;<br>- } else if (OVT.getVectorNumElements() == 4) {<br>- INTTY = MVT::v4i32;<br>- FLTTY = MVT::v4f32;<br>- }<br>- unsigned bitsize = OVT.getScalarType().getSizeInBits();<br>- // char|short jq = ia ^ ib;<br>- SDValue jq = DAG.getNode(ISD::XOR, DL, OVT, LHS, RHS);<br>-<br>- // jq = jq >> (bitsize - 2)<br>- jq = DAG.getNode(ISD::SRA, DL, OVT, jq, DAG.getConstant(bitsize - 2, OVT));<br>-<br>- // jq = jq | 0x1<br>- jq = DAG.getNode(ISD::OR, DL, OVT, jq, DAG.getConstant(1, OVT));<br>-<br>- // jq = (int)jq<br>- jq = DAG.getSExtOrTrunc(jq, DL, INTTY);<br>-<br>- // int ia = (int)LHS;<br>- SDValue ia = DAG.getSExtOrTrunc(LHS, DL, INTTY);<br>-<br>- // int ib, (int)RHS;<br>- SDValue ib = DAG.getSExtOrTrunc(RHS, DL, INTTY);<br>-<br>- // float fa = (float)ia;<br>- SDValue fa = DAG.getNode(ISD::SINT_TO_FP, DL, FLTTY, ia);<br>-<br>- // float fb = (float)ib;<br>- SDValue fb = DAG.getNode(ISD::SINT_TO_FP, DL, FLTTY, ib);<br>-<br>- // float fq = native_divide(fa, fb);<br>- SDValue fq = DAG.getNode(AMDGPUISD::DIV_INF, DL, FLTTY, fa, fb);<br>-<br>- // fq = trunc(fq);<br>- fq = DAG.getNode(ISD::FTRUNC, DL, FLTTY, fq);<br>-<br>- // float fqneg = -fq;<br>- SDValue fqneg = DAG.getNode(ISD::FNEG, DL, FLTTY, fq);<br>-<br>- // float fr = mad(fqneg, fb, fa);<br>- SDValue fr = DAG.getNode(ISD::FADD, DL, FLTTY,<br>- DAG.getNode(ISD::MUL, DL, FLTTY, fqneg, fb), fa);<br>-<br>- // int iq = (int)fq;<br>- SDValue iq = DAG.getNode(ISD::FP_TO_SINT, DL, INTTY, fq);<br>-<br>- // fr = fabs(fr);<br>- fr = DAG.getNode(ISD::FABS, DL, FLTTY, fr);<br>-<br>- // fb = fabs(fb);<br>- fb = DAG.getNode(ISD::FABS, DL, FLTTY, fb);<br>-<br>- // int cv = fr >= fb;<br>- SDValue cv;<br>- if (INTTY == MVT::i32) {<br>- cv = DAG.getSetCC(DL, INTTY, fr, fb, ISD::SETOGE);<br>- } else {<br>- cv = DAG.getSetCC(DL, INTTY, fr, fb, ISD::SETOGE);<br>- }<br>- // jq = (cv ? jq : 0);<br>- jq = DAG.getNode(ISD::SELECT, DL, OVT, cv, jq,<br>- DAG.getConstant(0, OVT));<br>- // dst = iq + jq;<br>- iq = DAG.getSExtOrTrunc(iq, DL, OVT);<br>- iq = DAG.getNode(ISD::ADD, DL, OVT, iq, jq);<br>- return iq;<br>-}<br>-<br>-SDValue AMDGPUTargetLowering::LowerSDIV32(SDValue Op, SelectionDAG &DAG) const {<br>- SDLoc DL(Op);<br>- EVT OVT = Op.getValueType();<br>- SDValue LHS = Op.getOperand(0);<br>- SDValue RHS = Op.getOperand(1);<br>- // The LowerSDIV32 function generates equivalent to the following IL.<br>- // mov r0, LHS<br>- // mov r1, RHS<br>- // ilt r10, r0, 0<br>- // ilt r11, r1, 0<br>- // iadd r0, r0, r10<br>- // iadd r1, r1, r11<br>- // ixor r0, r0, r10<br>- // ixor r1, r1, r11<br>- // udiv r0, r0, r1<br>- // ixor r10, r10, r11<br>- // iadd r0, r0, r10<br>- // ixor DST, r0, r10<br>-<br>- // mov r0, LHS<br>- SDValue r0 = LHS;<br>-<br>- // mov r1, RHS<br>- SDValue r1 = RHS;<br>-<br>- // ilt r10, r0, 0<br>- SDValue r10 = DAG.getSelectCC(DL,<br>- r0, DAG.getConstant(0, OVT),<br>- DAG.getConstant(-1, OVT),<br>- DAG.getConstant(0, OVT),<br>- ISD::SETLT);<br>-<br>- // ilt r11, r1, 0<br>- SDValue r11 = DAG.getSelectCC(DL,<br>- r1, DAG.getConstant(0, OVT),<br>- DAG.getConstant(-1, OVT),<br>- DAG.getConstant(0, OVT),<br>- ISD::SETLT);<br>-<br>- // iadd r0, r0, r10<br>- r0 = DAG.getNode(ISD::ADD, DL, OVT, r0, r10);<br>-<br>- // iadd r1, r1, r11<br>- r1 = DAG.getNode(ISD::ADD, DL, OVT, r1, r11);<br>-<br>- // ixor r0, r0, r10<br>- r0 = DAG.getNode(ISD::XOR, DL, OVT, r0, r10);<br>-<br>- // ixor r1, r1, r11<br>- r1 = DAG.getNode(ISD::XOR, DL, OVT, r1, r11);<br>-<br>- // udiv r0, r0, r1<br>- r0 = DAG.getNode(ISD::UDIV, DL, OVT, r0, r1);<br>-<br>- // ixor r10, r10, r11<br>- r10 = DAG.getNode(ISD::XOR, DL, OVT, r10, r11);<br>-<br>- // iadd r0, r0, r10<br>- r0 = DAG.getNode(ISD::ADD, DL, OVT, r0, r10);<br>-<br>- // ixor DST, r0, r10<br>- SDValue DST = DAG.getNode(ISD::XOR, DL, OVT, r0, r10);<br>- return DST;<br>-}<br>-<br>-SDValue AMDGPUTargetLowering::LowerSDIV64(SDValue Op, SelectionDAG &DAG) const {<br>- return SDValue(Op.getNode(), 0);<br>-}<br>-<br>-SDValue AMDGPUTargetLowering::LowerSDIV(SDValue Op, SelectionDAG &DAG) const {<br>- EVT OVT = Op.getValueType().getScalarType();<br>-<br>- if (OVT == MVT::i64)<br>- return LowerSDIV64(Op, DAG);<br>-<br>- if (OVT.getScalarType() == MVT::i32)<br>- return LowerSDIV32(Op, DAG);<br>-<br>- if (OVT == MVT::i16 || OVT == MVT::i8) {<br>- // FIXME: We should be checking for the masked bits. This isn't reached<br>- // because i8 and i16 are not legal types.<br>- return LowerSDIV24(Op, DAG);<br>- }<br>-<br>- return SDValue(Op.getNode(), 0);<br>-}<br>-<br>-SDValue AMDGPUTargetLowering::LowerSREM32(SDValue Op, SelectionDAG &DAG) const {<br>- SDLoc DL(Op);<br>- EVT OVT = Op.getValueType();<br>- SDValue LHS = Op.getOperand(0);<br>- SDValue RHS = Op.getOperand(1);<br>- // The LowerSREM32 function generates equivalent to the following IL.<br>- // mov r0, LHS<br>- // mov r1, RHS<br>- // ilt r10, r0, 0<br>- // ilt r11, r1, 0<br>- // iadd r0, r0, r10<br>- // iadd r1, r1, r11<br>- // ixor r0, r0, r10<br>- // ixor r1, r1, r11<br>- // udiv r20, r0, r1<br>- // umul r20, r20, r1<br>- // sub r0, r0, r20<br>- // iadd r0, r0, r10<br>- // ixor DST, r0, r10<br>-<br>- // mov r0, LHS<br>- SDValue r0 = LHS;<br>-<br>- // mov r1, RHS<br>- SDValue r1 = RHS;<br>-<br>- // ilt r10, r0, 0<br>- SDValue r10 = DAG.getSetCC(DL, OVT, r0, DAG.getConstant(0, OVT), ISD::SETLT);<br>-<br>- // ilt r11, r1, 0<br>- SDValue r11 = DAG.getSetCC(DL, OVT, r1, DAG.getConstant(0, OVT), ISD::SETLT);<br>-<br>- // iadd r0, r0, r10<br>- r0 = DAG.getNode(ISD::ADD, DL, OVT, r0, r10);<br>-<br>- // iadd r1, r1, r11<br>- r1 = DAG.getNode(ISD::ADD, DL, OVT, r1, r11);<br>-<br>- // ixor r0, r0, r10<br>- r0 = DAG.getNode(ISD::XOR, DL, OVT, r0, r10);<br>-<br>- // ixor r1, r1, r11<br>- r1 = DAG.getNode(ISD::XOR, DL, OVT, r1, r11);<br>-<br>- // udiv r20, r0, r1<br>- SDValue r20 = DAG.getNode(ISD::UREM, DL, OVT, r0, r1);<br>-<br>- // umul r20, r20, r1<br>- r20 = DAG.getNode(AMDGPUISD::UMUL, DL, OVT, r20, r1);<br>-<br>- // sub r0, r0, r20<br>- r0 = DAG.getNode(ISD::SUB, DL, OVT, r0, r20);<br>-<br>- // iadd r0, r0, r10<br>- r0 = DAG.getNode(ISD::ADD, DL, OVT, r0, r10);<br>-<br>- // ixor DST, r0, r10<br>- SDValue DST = DAG.getNode(ISD::XOR, DL, OVT, r0, r10);<br>- return DST;<br>-}<br>-<br>-SDValue AMDGPUTargetLowering::LowerSREM64(SDValue Op, SelectionDAG &DAG) const {<br>- return SDValue(Op.getNode(), 0);<br>-}<br>-<br>-SDValue AMDGPUTargetLowering::LowerSREM(SDValue Op, SelectionDAG &DAG) const {<br>- EVT OVT = Op.getValueType();<br>-<br>- if (OVT.getScalarType() == MVT::i64)<br>- return LowerSREM64(Op, DAG);<br>-<br>- if (OVT.getScalarType() == MVT::i32)<br>- return LowerSREM32(Op, DAG);<br>-<br>- return SDValue(Op.getNode(), 0);<br>-}<br>-<br>SDValue AMDGPUTargetLowering::LowerUDIVREM(SDValue Op,<br> SelectionDAG &DAG) const {<br> SDLoc DL(Op);<br>diff --git a/lib/Target/R600/AMDGPUISelLowering.h b/lib/Target/R600/AMDGPUISelLowering.h<br>index 0db89ecb..4d83ddd 100644<br>--- a/lib/Target/R600/AMDGPUISelLowering.h<br>+++ b/lib/Target/R600/AMDGPUISelLowering.h<br>@@ -43,13 +43,6 @@ private:<br> /// \brief Split a vector store into multiple scalar stores.<br> /// \returns The resulting chain.<br><br>- SDValue LowerSDIV(SDValue Op, SelectionDAG &DAG) const;<br>- SDValue LowerSDIV24(SDValue Op, SelectionDAG &DAG) const;<br>- SDValue LowerSDIV32(SDValue Op, SelectionDAG &DAG) const;<br>- SDValue LowerSDIV64(SDValue Op, SelectionDAG &DAG) const;<br>- SDValue LowerSREM(SDValue Op, SelectionDAG &DAG) const;<br>- SDValue LowerSREM32(SDValue Op, SelectionDAG &DAG) const;<br>- SDValue LowerSREM64(SDValue Op, SelectionDAG &DAG) const;<br> SDValue LowerSDIVREM(SDValue Op, SelectionDAG &DAG) const;<br> SDValue LowerUDIVREM(SDValue Op, SelectionDAG &DAG) const;<br> SDValue LowerFCEIL(SDValue Op, SelectionDAG &DAG) const;<br>--<span class="Apple-converted-space"> </span><br>1.9.3<br><br>_______________________________________________<br>llvm-commits mailing list<br><a href="mailto:llvm-commits@cs.uiuc.edu">llvm-commits@cs.uiuc.edu</a><br>http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits<br></blockquote><br></blockquote><br>--<span class="Apple-converted-space"> </span><br>Jan Vesely <<a href="mailto:jan.vesely@rutgers.edu">jan.vesely@rutgers.edu</a>></div></blockquote></div><br></body></html>