<div dir="ltr"><div class="gmail_extra"><div class="gmail_quote">On Mon, Jun 16, 2014 at 3:30 PM, Alp Toker <span dir="ltr"><<a href="mailto:alp@nuanti.com" target="_blank">alp@nuanti.com</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">
Hi Manuel,<br>
<br>
These issues need to be resolved before further commits are made, following the same standard we expect from on-list patch review. It's my understanding that you have to fix these centrally so I'm addressing the comments to you this time.<br>
<br>
The "Depends on D4117" doesn't make sense from a standard version control view or mailing list workflow. Can you update entries like this in your script to point to an SVN revision?<br>
<br>
Also don't generate a "Reviewers" line. The "Reviewed By" line should *probably* go away as well as we don't do this with other commits, but if you feel strongly I guess it's OK to keep for now.<br>
<br>
Otherwise looks fine to start using again once those points are addressed.</blockquote><div><br></div><div>The commit messages are only indirectly related to phabricator:</div><div>There is a tool one can use that makes sending patches really easy - that tool is called "arc".</div>
<div>If you use that tool to commit the patch (which is completely optional, I personally use "arc" for the review flow, but submit without it), it creates those rather verbose commit messages. I personally discourage people from using "arc commit", because I also dislike those messages. If you feel strongly about a style guide for commit messages, please start a thread on llvmdev/cfe-dev.</div>
<div><br></div><div>Thanks,</div><div>/Manuel</div><div><br></div><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"><span class="HOEnZb"><font color="#888888"><br>
<br>
Alp.</font></span><div class="HOEnZb"><div class="h5"><br>
<br>
<br>
<br>
-------- Original Message --------<br>
Subject: [llvm] r211013 - [mips] Merge most of the big/little endian checks in atomic.ll<br>
Date: Mon, 16 Jun 2014 10:25:17 -0000<br>
From: Daniel Sanders <<a href="mailto:daniel.sanders@imgtec.com" target="_blank">daniel.sanders@imgtec.com</a>><br>
To: <a href="mailto:llvm-commits@cs.uiuc.edu" target="_blank">llvm-commits@cs.uiuc.edu</a><br>
<br>
<br>
<br>
Author: dsanders<br>
Date: Mon Jun 16 05:25:17 2014<br>
New Revision: 211013<br>
<br>
URL: <a href="http://llvm.org/viewvc/llvm-project?rev=211013&view=rev" target="_blank">http://llvm.org/viewvc/llvm-<u></u>project?rev=211013&view=rev</a><br>
Log:<br>
[mips] Merge most of the big/little endian checks in atomic.ll<br>
<br>
Summary:<br>
There is very little difference between the big and little endian cases in<br>
test/CodeGen/Mips/atomic.ll. Merge them together using multiple<br>
FileCheck prefixes.<br>
<br>
Depends on D4117<br>
<br>
Reviewers: jkolek, zoran.jovanovic, vmedic<br>
<br>
Reviewed By: vmedic<br>
<br>
Differential Revision: <a href="http://reviews.llvm.org/D4118" target="_blank">http://reviews.llvm.org/D4118</a><br>
<br>
Modified:<br>
llvm/trunk/test/CodeGen/Mips/<u></u>atomic.ll<br>
<br>
Modified: llvm/trunk/test/CodeGen/Mips/<u></u>atomic.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/atomic.ll?rev=211013&r1=211012&r2=211013&view=diff" target="_blank">http://llvm.org/viewvc/llvm-<u></u>project/llvm/trunk/test/<u></u>CodeGen/Mips/atomic.ll?rev=<u></u>211013&r1=211012&r2=211013&<u></u>view=diff</a><br>
==============================<u></u>==============================<u></u>==================<br>
--- llvm/trunk/test/CodeGen/Mips/<u></u>atomic.ll (original)<br>
+++ llvm/trunk/test/CodeGen/Mips/<u></u>atomic.ll Mon Jun 16 05:25:17 2014<br>
@@ -1,5 +1,5 @@<br>
-; RUN: llc -march=mipsel --disable-machine-licm < %s | FileCheck %s -check-prefix=CHECK-EL<br>
-; RUN: llc -march=mips --disable-machine-licm < %s | FileCheck %s -check-prefix=CHECK-EB<br>
+; RUN: llc -march=mipsel --disable-machine-licm < %s | FileCheck %s -check-prefix=ALL -check-prefix=CHECK-EL<br>
+; RUN: llc -march=mips --disable-machine-licm < %s | FileCheck %s -check-prefix=ALL -check-prefix=CHECK-EB<br>
@x = common global i32 0, align 4<br>
@@ -8,21 +8,14 @@ entry:<br>
%0 = atomicrmw add i32* @x, i32 %incr monotonic<br>
ret i32 %0<br>
-; CHECK-EL-LABEL: AtomicLoadAdd32:<br>
-; CHECK-EL: lw $[[R0:[0-9]+]], %got(x)<br>
-; CHECK-EL: $[[BB0:[A-Z_0-9]+]]:<br>
-; CHECK-EL: ll $[[R1:[0-9]+]], 0($[[R0]])<br>
-; CHECK-EL: addu $[[R2:[0-9]+]], $[[R1]], $4<br>
-; CHECK-EL: sc $[[R2]], 0($[[R0]])<br>
-; CHECK-EL: beqz $[[R2]], $[[BB0]]<br>
-<br>
-; CHECK-EB-LABEL: AtomicLoadAdd32:<br>
-; CHECK-EB: lw $[[R0:[0-9]+]], %got(x)<br>
-; CHECK-EB: $[[BB0:[A-Z_0-9]+]]:<br>
-; CHECK-EB: ll $[[R1:[0-9]+]], 0($[[R0]])<br>
-; CHECK-EB: addu $[[R2:[0-9]+]], $[[R1]], $4<br>
-; CHECK-EB: sc $[[R2]], 0($[[R0]])<br>
-; CHECK-EB: beqz $[[R2]], $[[BB0]]<br>
+; ALL-LABEL: AtomicLoadAdd32:<br>
+<br>
+; ALL: lw $[[R0:[0-9]+]], %got(x)<br>
+; ALL: $[[BB0:[A-Z_0-9]+]]:<br>
+; ALL: ll $[[R1:[0-9]+]], 0($[[R0]])<br>
+; ALL: addu $[[R2:[0-9]+]], $[[R1]], $4<br>
+; ALL: sc $[[R2]], 0($[[R0]])<br>
+; ALL: beqz $[[R2]], $[[BB0]]<br>
}<br>
define i32 @AtomicLoadNand32(i32 %incr) nounwind {<br>
@@ -30,23 +23,15 @@ entry:<br>
%0 = atomicrmw nand i32* @x, i32 %incr monotonic<br>
ret i32 %0<br>
-; CHECK-EL-LABEL: AtomicLoadNand32:<br>
-; CHECK-EL: lw $[[R0:[0-9]+]], %got(x)<br>
-; CHECK-EL: $[[BB0:[A-Z_0-9]+]]:<br>
-; CHECK-EL: ll $[[R1:[0-9]+]], 0($[[R0]])<br>
-; CHECK-EL: and $[[R3:[0-9]+]], $[[R1]], $4<br>
-; CHECK-EL: nor $[[R2:[0-9]+]], $zero, $[[R3]]<br>
-; CHECK-EL: sc $[[R2]], 0($[[R0]])<br>
-; CHECK-EL: beqz $[[R2]], $[[BB0]]<br>
-<br>
-; CHECK-EB-LABEL: AtomicLoadNand32:<br>
-; CHECK-EB: lw $[[R0:[0-9]+]], %got(x)<br>
-; CHECK-EB: $[[BB0:[A-Z_0-9]+]]:<br>
-; CHECK-EB: ll $[[R1:[0-9]+]], 0($[[R0]])<br>
-; CHECK-EB: and $[[R3:[0-9]+]], $[[R1]], $4<br>
-; CHECK-EB: nor $[[R2:[0-9]+]], $zero, $[[R3]]<br>
-; CHECK-EB: sc $[[R2]], 0($[[R0]])<br>
-; CHECK-EB: beqz $[[R2]], $[[BB0]]<br>
+; ALL-LABEL: AtomicLoadNand32:<br>
+<br>
+; ALL: lw $[[R0:[0-9]+]], %got(x)<br>
+; ALL: $[[BB0:[A-Z_0-9]+]]:<br>
+; ALL: ll $[[R1:[0-9]+]], 0($[[R0]])<br>
+; ALL: and $[[R3:[0-9]+]], $[[R1]], $4<br>
+; ALL: nor $[[R2:[0-9]+]], $zero, $[[R3]]<br>
+; ALL: sc $[[R2]], 0($[[R0]])<br>
+; ALL: beqz $[[R2]], $[[BB0]]<br>
}<br>
define i32 @AtomicSwap32(i32 %newval) nounwind {<br>
@@ -57,19 +42,13 @@ entry:<br>
%0 = atomicrmw xchg i32* @x, i32 %tmp monotonic<br>
ret i32 %0<br>
-; CHECK-EL-LABEL: AtomicSwap32:<br>
-; CHECK-EL: lw $[[R0:[0-9]+]], %got(x)<br>
-; CHECK-EL: $[[BB0:[A-Z_0-9]+]]:<br>
-; CHECK-EL: ll ${{[0-9]+}}, 0($[[R0]])<br>
-; CHECK-EL: sc $[[R2:[0-9]+]], 0($[[R0]])<br>
-; CHECK-EL: beqz $[[R2]], $[[BB0]]<br>
-<br>
-; CHECK-EB-LABEL: AtomicSwap32:<br>
-; CHECK-EB: lw $[[R0:[0-9]+]], %got(x)<br>
-; CHECK-EB: $[[BB0:[A-Z_0-9]+]]:<br>
-; CHECK-EB: ll ${{[0-9]+}}, 0($[[R0]])<br>
-; CHECK-EB: sc $[[R2:[0-9]+]], 0($[[R0]])<br>
-; CHECK-EB: beqz $[[R2]], $[[BB0]]<br>
+; ALL-LABEL: AtomicSwap32:<br>
+<br>
+; ALL: lw $[[R0:[0-9]+]], %got(x)<br>
+; ALL: $[[BB0:[A-Z_0-9]+]]:<br>
+; ALL: ll ${{[0-9]+}}, 0($[[R0]])<br>
+; ALL: sc $[[R2:[0-9]+]], 0($[[R0]])<br>
+; ALL: beqz $[[R2]], $[[BB0]]<br>
}<br>
define i32 @AtomicCmpSwap32(i32 %oldval, i32 %newval) nounwind {<br>
@@ -81,23 +60,15 @@ entry:<br>
%1 = extractvalue { i32, i1 } %0, 0<br>
ret i32 %1<br>
-; CHECK-EL-LABEL: AtomicCmpSwap32:<br>
-; CHECK-EL: lw $[[R0:[0-9]+]], %got(x)<br>
-; CHECK-EL: $[[BB0:[A-Z_0-9]+]]:<br>
-; CHECK-EL: ll $2, 0($[[R0]])<br>
-; CHECK-EL: bne $2, $4, $[[BB1:[A-Z_0-9]+]]<br>
-; CHECK-EL: sc $[[R2:[0-9]+]], 0($[[R0]])<br>
-; CHECK-EL: beqz $[[R2]], $[[BB0]]<br>
-; CHECK-EL: $[[BB1]]:<br>
-<br>
-; CHECK-EB-LABEL: AtomicCmpSwap32:<br>
-; CHECK-EB: lw $[[R0:[0-9]+]], %got(x)<br>
-; CHECK-EB: $[[BB0:[A-Z_0-9]+]]:<br>
-; CHECK-EB: ll $2, 0($[[R0]])<br>
-; CHECK-EB: bne $2, $4, $[[BB1:[A-Z_0-9]+]]<br>
-; CHECK-EB: sc $[[R2:[0-9]+]], 0($[[R0]])<br>
-; CHECK-EB: beqz $[[R2]], $[[BB0]]<br>
-; CHECK-EB: $[[BB1]]:<br>
+; ALL-LABEL: AtomicCmpSwap32:<br>
+<br>
+; ALL: lw $[[R0:[0-9]+]], %got(x)<br>
+; ALL: $[[BB0:[A-Z_0-9]+]]:<br>
+; ALL: ll $2, 0($[[R0]])<br>
+; ALL: bne $2, $4, $[[BB1:[A-Z_0-9]+]]<br>
+; ALL: sc $[[R2:[0-9]+]], 0($[[R0]])<br>
+; ALL: beqz $[[R2]], $[[BB0]]<br>
+; ALL: $[[BB1]]:<br>
}<br>
@@ -109,56 +80,33 @@ entry:<br>
%0 = atomicrmw add i8* @y, i8 %incr monotonic<br>
ret i8 %0<br>
-; CHECK-EL-LABEL: AtomicLoadAdd8:<br>
-; CHECK-EL: lw $[[R0:[0-9]+]], %got(y)<br>
-; CHECK-EL: addiu $[[R1:[0-9]+]], $zero, -4<br>
-; CHECK-EL: and $[[R2:[0-9]+]], $[[R0]], $[[R1]]<br>
-; CHECK-EL: andi $[[R3:[0-9]+]], $[[R0]], 3<br>
-; CHECK-EL: sll $[[R4:[0-9]+]], $[[R3]], 3<br>
-; CHECK-EL: ori $[[R5:[0-9]+]], $zero, 255<br>
-; CHECK-EL: sllv $[[R6:[0-9]+]], $[[R5]], $[[R4]]<br>
-; CHECK-EL: nor $[[R7:[0-9]+]], $zero, $[[R6]]<br>
-; CHECK-EL: sllv $[[R9:[0-9]+]], $4, $[[R4]]<br>
-<br>
-; CHECK-EL: $[[BB0:[A-Z_0-9]+]]:<br>
-; CHECK-EL: ll $[[R10:[0-9]+]], 0($[[R2]])<br>
-; CHECK-EL: addu $[[R11:[0-9]+]], $[[R10]], $[[R9]]<br>
-; CHECK-EL: and $[[R12:[0-9]+]], $[[R11]], $[[R6]]<br>
-; CHECK-EL: and $[[R13:[0-9]+]], $[[R10]], $[[R7]]<br>
-; CHECK-EL: or $[[R14:[0-9]+]], $[[R13]], $[[R12]]<br>
-; CHECK-EL: sc $[[R14]], 0($[[R2]])<br>
-; CHECK-EL: beqz $[[R14]], $[[BB0]]<br>
-<br>
-; CHECK-EL: and $[[R15:[0-9]+]], $[[R10]], $[[R6]]<br>
-; CHECK-EL: srlv $[[R16:[0-9]+]], $[[R15]], $[[R4]]<br>
-; CHECK-EL: sll $[[R17:[0-9]+]], $[[R16]], 24<br>
-; CHECK-EL: sra $2, $[[R17]], 24<br>
-<br>
-; CHECK-EB-LABEL: AtomicLoadAdd8:<br>
-; CHECK-EB: lw $[[R0:[0-9]+]], %got(y)<br>
-; CHECK-EB: addiu $[[R1:[0-9]+]], $zero, -4<br>
-; CHECK-EB: and $[[R2:[0-9]+]], $[[R0]], $[[R1]]<br>
-; CHECK-EB: andi $[[R3:[0-9]+]], $[[R0]], 3<br>
-; CHECK-EB: xori $[[R4:[0-9]+]], $[[R3]], 3<br>
-; CHECK-EB: sll $[[R5:[0-9]+]], $[[R4]], 3<br>
-; CHECK-EB: ori $[[R6:[0-9]+]], $zero, 255<br>
-; CHECK-EB: sllv $[[R7:[0-9]+]], $[[R6]], $[[R5]]<br>
-; CHECK-EB: nor $[[R8:[0-9]+]], $zero, $[[R7]]<br>
-; CHECK-EB: sllv $[[R9:[0-9]+]], $4, $[[R5]]<br>
-<br>
-; CHECK-EB: $[[BB0:[A-Z_0-9]+]]:<br>
-; CHECK-EB: ll $[[R10:[0-9]+]], 0($[[R2]])<br>
-; CHECK-EB: addu $[[R11:[0-9]+]], $[[R10]], $[[R9]]<br>
-; CHECK-EB: and $[[R12:[0-9]+]], $[[R11]], $[[R7]]<br>
-; CHECK-EB: and $[[R13:[0-9]+]], $[[R10]], $[[R8]]<br>
-; CHECK-EB: or $[[R14:[0-9]+]], $[[R13]], $[[R12]]<br>
-; CHECK-EB: sc $[[R14]], 0($[[R2]])<br>
-; CHECK-EB: beqz $[[R14]], $[[BB0]]<br>
-<br>
-; CHECK-EB: and $[[R15:[0-9]+]], $[[R10]], $[[R7]]<br>
-; CHECK-EB: srlv $[[R16:[0-9]+]], $[[R15]], $[[R5]]<br>
-; CHECK-EB: sll $[[R17:[0-9]+]], $[[R16]], 24<br>
-; CHECK-EB: sra $2, $[[R17]], 24<br>
+; ALL-LABEL: AtomicLoadAdd8:<br>
+<br>
+; ALL: lw $[[R0:[0-9]+]], %got(y)<br>
+; ALL: addiu $[[R1:[0-9]+]], $zero, -4<br>
+; ALL: and $[[R2:[0-9]+]], $[[R0]], $[[R1]]<br>
+; ALL: andi $[[R3:[0-9]+]], $[[R0]], 3<br>
+; CHECK-EB: xori $[[R4:[0-9]+]], $[[R3]], 3<br>
+; CHECK-EB: sll $[[R5:[0-9]+]], $[[R4]], 3<br>
+; CHECK-EL: sll $[[R5:[0-9]+]], $[[R3]], 3<br>
+; ALL: ori $[[R6:[0-9]+]], $zero, 255<br>
+; ALL: sllv $[[R7:[0-9]+]], $[[R6]], $[[R5]]<br>
+; ALL: nor $[[R8:[0-9]+]], $zero, $[[R7]]<br>
+; ALL: sllv $[[R9:[0-9]+]], $4, $[[R5]]<br>
+<br>
+; ALL: $[[BB0:[A-Z_0-9]+]]:<br>
+; ALL: ll $[[R10:[0-9]+]], 0($[[R2]])<br>
+; ALL: addu $[[R11:[0-9]+]], $[[R10]], $[[R9]]<br>
+; ALL: and $[[R12:[0-9]+]], $[[R11]], $[[R7]]<br>
+; ALL: and $[[R13:[0-9]+]], $[[R10]], $[[R8]]<br>
+; ALL: or $[[R14:[0-9]+]], $[[R13]], $[[R12]]<br>
+; ALL: sc $[[R14]], 0($[[R2]])<br>
+; ALL: beqz $[[R14]], $[[BB0]]<br>
+<br>
+; ALL: and $[[R15:[0-9]+]], $[[R10]], $[[R7]]<br>
+; ALL: srlv $[[R16:[0-9]+]], $[[R15]], $[[R5]]<br>
+; ALL: sll $[[R17:[0-9]+]], $[[R16]], 24<br>
+; ALL: sra $2, $[[R17]], 24<br>
}<br>
define signext i8 @AtomicLoadSub8(i8 signext %incr) nounwind {<br>
@@ -166,56 +114,33 @@ entry:<br>
%0 = atomicrmw sub i8* @y, i8 %incr monotonic<br>
ret i8 %0<br>
-; CHECK-EL-LABEL: AtomicLoadSub8:<br>
-; CHECK-EL: lw $[[R0:[0-9]+]], %got(y)<br>
-; CHECK-EL: addiu $[[R1:[0-9]+]], $zero, -4<br>
-; CHECK-EL: and $[[R2:[0-9]+]], $[[R0]], $[[R1]]<br>
-; CHECK-EL: andi $[[R3:[0-9]+]], $[[R0]], 3<br>
-; CHECK-EL: sll $[[R4:[0-9]+]], $[[R3]], 3<br>
-; CHECK-EL: ori $[[R5:[0-9]+]], $zero, 255<br>
-; CHECK-EL: sllv $[[R6:[0-9]+]], $[[R5]], $[[R4]]<br>
-; CHECK-EL: nor $[[R7:[0-9]+]], $zero, $[[R6]]<br>
-; CHECK-EL: sllv $[[R9:[0-9]+]], $4, $[[R4]]<br>
-<br>
-; CHECK-EL: $[[BB0:[A-Z_0-9]+]]:<br>
-; CHECK-EL: ll $[[R10:[0-9]+]], 0($[[R2]])<br>
-; CHECK-EL: subu $[[R11:[0-9]+]], $[[R10]], $[[R9]]<br>
-; CHECK-EL: and $[[R12:[0-9]+]], $[[R11]], $[[R6]]<br>
-; CHECK-EL: and $[[R13:[0-9]+]], $[[R10]], $[[R7]]<br>
-; CHECK-EL: or $[[R14:[0-9]+]], $[[R13]], $[[R12]]<br>
-; CHECK-EL: sc $[[R14]], 0($[[R2]])<br>
-; CHECK-EL: beqz $[[R14]], $[[BB0]]<br>
-<br>
-; CHECK-EL: and $[[R15:[0-9]+]], $[[R10]], $[[R6]]<br>
-; CHECK-EL: srlv $[[R16:[0-9]+]], $[[R15]], $[[R4]]<br>
-; CHECK-EL: sll $[[R17:[0-9]+]], $[[R16]], 24<br>
-; CHECK-EL: sra $2, $[[R17]], 24<br>
-<br>
-; CHECK-EB-LABEL: AtomicLoadSub8:<br>
-; CHECK-EB: lw $[[R0:[0-9]+]], %got(y)<br>
-; CHECK-EB: addiu $[[R1:[0-9]+]], $zero, -4<br>
-; CHECK-EB: and $[[R2:[0-9]+]], $[[R0]], $[[R1]]<br>
-; CHECK-EB: andi $[[R3:[0-9]+]], $[[R0]], 3<br>
+; ALL-LABEL: AtomicLoadSub8:<br>
+<br>
+; ALL: lw $[[R0:[0-9]+]], %got(y)<br>
+; ALL: addiu $[[R1:[0-9]+]], $zero, -4<br>
+; ALL: and $[[R2:[0-9]+]], $[[R0]], $[[R1]]<br>
+; ALL: andi $[[R3:[0-9]+]], $[[R0]], 3<br>
+; CHECK-EL: sll $[[R5:[0-9]+]], $[[R3]], 3<br>
; CHECK-EB: xori $[[R4:[0-9]+]], $[[R3]], 3<br>
; CHECK-EB: sll $[[R5:[0-9]+]], $[[R4]], 3<br>
-; CHECK-EB: ori $[[R6:[0-9]+]], $zero, 255<br>
-; CHECK-EB: sllv $[[R7:[0-9]+]], $[[R6]], $[[R5]]<br>
-; CHECK-EB: nor $[[R8:[0-9]+]], $zero, $[[R7]]<br>
-; CHECK-EB: sllv $[[R9:[0-9]+]], $4, $[[R5]]<br>
-<br>
-; CHECK-EB: $[[BB0:[A-Z_0-9]+]]:<br>
-; CHECK-EB: ll $[[R10:[0-9]+]], 0($[[R2]])<br>
-; CHECK-EB: subu $[[R11:[0-9]+]], $[[R10]], $[[R9]]<br>
-; CHECK-EB: and $[[R12:[0-9]+]], $[[R11]], $[[R7]]<br>
-; CHECK-EB: and $[[R13:[0-9]+]], $[[R10]], $[[R8]]<br>
-; CHECK-EB: or $[[R14:[0-9]+]], $[[R13]], $[[R12]]<br>
-; CHECK-EB: sc $[[R14]], 0($[[R2]])<br>
-; CHECK-EB: beqz $[[R14]], $[[BB0]]<br>
-<br>
-; CHECK-EB: and $[[R15:[0-9]+]], $[[R10]], $[[R7]]<br>
-; CHECK-EB: srlv $[[R16:[0-9]+]], $[[R15]], $[[R5]]<br>
-; CHECK-EB: sll $[[R17:[0-9]+]], $[[R16]], 24<br>
-; CHECK-EB: sra $2, $[[R17]], 24<br>
+; ALL: ori $[[R6:[0-9]+]], $zero, 255<br>
+; ALL: sllv $[[R7:[0-9]+]], $[[R6]], $[[R5]]<br>
+; ALL: nor $[[R8:[0-9]+]], $zero, $[[R7]]<br>
+; ALL: sllv $[[R9:[0-9]+]], $4, $[[R5]]<br>
+<br>
+; ALL: $[[BB0:[A-Z_0-9]+]]:<br>
+; ALL: ll $[[R10:[0-9]+]], 0($[[R2]])<br>
+; ALL: subu $[[R11:[0-9]+]], $[[R10]], $[[R9]]<br>
+; ALL: and $[[R12:[0-9]+]], $[[R11]], $[[R7]]<br>
+; ALL: and $[[R13:[0-9]+]], $[[R10]], $[[R8]]<br>
+; ALL: or $[[R14:[0-9]+]], $[[R13]], $[[R12]]<br>
+; ALL: sc $[[R14]], 0($[[R2]])<br>
+; ALL: beqz $[[R14]], $[[BB0]]<br>
+<br>
+; ALL: and $[[R15:[0-9]+]], $[[R10]], $[[R7]]<br>
+; ALL: srlv $[[R16:[0-9]+]], $[[R15]], $[[R5]]<br>
+; ALL: sll $[[R17:[0-9]+]], $[[R16]], 24<br>
+; ALL: sra $2, $[[R17]], 24<br>
}<br>
define signext i8 @AtomicLoadNand8(i8 signext %incr) nounwind {<br>
@@ -223,58 +148,34 @@ entry:<br>
%0 = atomicrmw nand i8* @y, i8 %incr monotonic<br>
ret i8 %0<br>
-; CHECK-EL-LABEL: AtomicLoadNand8:<br>
-; CHECK-EL: lw $[[R0:[0-9]+]], %got(y)<br>
-; CHECK-EL: addiu $[[R1:[0-9]+]], $zero, -4<br>
-; CHECK-EL: and $[[R2:[0-9]+]], $[[R0]], $[[R1]]<br>
-; CHECK-EL: andi $[[R3:[0-9]+]], $[[R0]], 3<br>
-; CHECK-EL: sll $[[R4:[0-9]+]], $[[R3]], 3<br>
-; CHECK-EL: ori $[[R5:[0-9]+]], $zero, 255<br>
-; CHECK-EL: sllv $[[R6:[0-9]+]], $[[R5]], $[[R4]]<br>
-; CHECK-EL: nor $[[R7:[0-9]+]], $zero, $[[R6]]<br>
-; CHECK-EL: sllv $[[R9:[0-9]+]], $4, $[[R4]]<br>
-<br>
-; CHECK-EL: $[[BB0:[A-Z_0-9]+]]:<br>
-; CHECK-EL: ll $[[R10:[0-9]+]], 0($[[R2]])<br>
-; CHECK-EL: and $[[R18:[0-9]+]], $[[R10]], $[[R9]]<br>
-; CHECK-EL: nor $[[R11:[0-9]+]], $zero, $[[R18]]<br>
-; CHECK-EL: and $[[R12:[0-9]+]], $[[R11]], $[[R6]]<br>
-; CHECK-EL: and $[[R13:[0-9]+]], $[[R10]], $[[R7]]<br>
-; CHECK-EL: or $[[R14:[0-9]+]], $[[R13]], $[[R12]]<br>
-; CHECK-EL: sc $[[R14]], 0($[[R2]])<br>
-; CHECK-EL: beqz $[[R14]], $[[BB0]]<br>
-<br>
-; CHECK-EL: and $[[R15:[0-9]+]], $[[R10]], $[[R6]]<br>
-; CHECK-EL: srlv $[[R16:[0-9]+]], $[[R15]], $[[R4]]<br>
-; CHECK-EL: sll $[[R17:[0-9]+]], $[[R16]], 24<br>
-; CHECK-EL: sra $2, $[[R17]], 24<br>
-<br>
-; CHECK-EB-LABEL: AtomicLoadNand8:<br>
-; CHECK-EB: lw $[[R0:[0-9]+]], %got(y)<br>
-; CHECK-EB: addiu $[[R1:[0-9]+]], $zero, -4<br>
-; CHECK-EB: and $[[R2:[0-9]+]], $[[R0]], $[[R1]]<br>
-; CHECK-EB: andi $[[R3:[0-9]+]], $[[R0]], 3<br>
-; CHECK-EB: xori $[[R4:[0-9]+]], $[[R3]], 3<br>
-; CHECK-EB: sll $[[R5:[0-9]+]], $[[R4]], 3<br>
-; CHECK-EB: ori $[[R6:[0-9]+]], $zero, 255<br>
-; CHECK-EB: sllv $[[R7:[0-9]+]], $[[R6]], $[[R5]]<br>
-; CHECK-EB: nor $[[R8:[0-9]+]], $zero, $[[R7]]<br>
-; CHECK-EB: sllv $[[R9:[0-9]+]], $4, $[[R5]]<br>
-<br>
-; CHECK-EB: $[[BB0:[A-Z_0-9]+]]:<br>
-; CHECK-EB: ll $[[R10:[0-9]+]], 0($[[R2]])<br>
-; CHECK-EB: and $[[R18:[0-9]+]], $[[R10]], $[[R9]]<br>
-; CHECK-EB: nor $[[R11:[0-9]+]], $zero, $[[R18]]<br>
-; CHECK-EB: and $[[R12:[0-9]+]], $[[R11]], $[[R7]]<br>
-; CHECK-EB: and $[[R13:[0-9]+]], $[[R10]], $[[R8]]<br>
-; CHECK-EB: or $[[R14:[0-9]+]], $[[R13]], $[[R12]]<br>
-; CHECK-EB: sc $[[R14]], 0($[[R2]])<br>
-; CHECK-EB: beqz $[[R14]], $[[BB0]]<br>
-<br>
-; CHECK-EB: and $[[R15:[0-9]+]], $[[R10]], $[[R7]]<br>
-; CHECK-EB: srlv $[[R16:[0-9]+]], $[[R15]], $[[R5]]<br>
-; CHECK-EB: sll $[[R17:[0-9]+]], $[[R16]], 24<br>
-; CHECK-EB: sra $2, $[[R17]], 24<br>
+; ALL-LABEL: AtomicLoadNand8:<br>
+<br>
+; ALL: lw $[[R0:[0-9]+]], %got(y)<br>
+; ALL: addiu $[[R1:[0-9]+]], $zero, -4<br>
+; ALL: and $[[R2:[0-9]+]], $[[R0]], $[[R1]]<br>
+; ALL: andi $[[R3:[0-9]+]], $[[R0]], 3<br>
+; CHECK-EL: sll $[[R5:[0-9]+]], $[[R3]], 3<br>
+; CHECK-EB: xori $[[R4:[0-9]+]], $[[R3]], 3<br>
+; CHECK-EB: sll $[[R5:[0-9]+]], $[[R4]], 3<br>
+; ALL: ori $[[R6:[0-9]+]], $zero, 255<br>
+; ALL: sllv $[[R7:[0-9]+]], $[[R6]], $[[R5]]<br>
+; ALL: nor $[[R8:[0-9]+]], $zero, $[[R7]]<br>
+; ALL: sllv $[[R9:[0-9]+]], $4, $[[R5]]<br>
+<br>
+; ALL: $[[BB0:[A-Z_0-9]+]]:<br>
+; ALL: ll $[[R10:[0-9]+]], 0($[[R2]])<br>
+; ALL: and $[[R18:[0-9]+]], $[[R10]], $[[R9]]<br>
+; ALL: nor $[[R11:[0-9]+]], $zero, $[[R18]]<br>
+; ALL: and $[[R12:[0-9]+]], $[[R11]], $[[R7]]<br>
+; ALL: and $[[R13:[0-9]+]], $[[R10]], $[[R8]]<br>
+; ALL: or $[[R14:[0-9]+]], $[[R13]], $[[R12]]<br>
+; ALL: sc $[[R14]], 0($[[R2]])<br>
+; ALL: beqz $[[R14]], $[[BB0]]<br>
+<br>
+; ALL: and $[[R15:[0-9]+]], $[[R10]], $[[R7]]<br>
+; ALL: srlv $[[R16:[0-9]+]], $[[R15]], $[[R5]]<br>
+; ALL: sll $[[R17:[0-9]+]], $[[R16]], 24<br>
+; ALL: sra $2, $[[R17]], 24<br>
}<br>
define signext i8 @AtomicSwap8(i8 signext %newval) nounwind {<br>
@@ -282,54 +183,32 @@ entry:<br>
%0 = atomicrmw xchg i8* @y, i8 %newval monotonic<br>
ret i8 %0<br>
-; CHECK-EL-LABEL: AtomicSwap8:<br>
-; CHECK-EL: lw $[[R0:[0-9]+]], %got(y)<br>
-; CHECK-EL: addiu $[[R1:[0-9]+]], $zero, -4<br>
-; CHECK-EL: and $[[R2:[0-9]+]], $[[R0]], $[[R1]]<br>
-; CHECK-EL: andi $[[R3:[0-9]+]], $[[R0]], 3<br>
-; CHECK-EL: sll $[[R4:[0-9]+]], $[[R3]], 3<br>
-; CHECK-EL: ori $[[R5:[0-9]+]], $zero, 255<br>
-; CHECK-EL: sllv $[[R6:[0-9]+]], $[[R5]], $[[R4]]<br>
-; CHECK-EL: nor $[[R7:[0-9]+]], $zero, $[[R6]]<br>
-; CHECK-EL: sllv $[[R9:[0-9]+]], $4, $[[R4]]<br>
-<br>
-; CHECK-EL: $[[BB0:[A-Z_0-9]+]]:<br>
-; CHECK-EL: ll $[[R10:[0-9]+]], 0($[[R2]])<br>
-; CHECK-EL: and $[[R18:[0-9]+]], $[[R9]], $[[R6]]<br>
-; CHECK-EL: and $[[R13:[0-9]+]], $[[R10]], $[[R7]]<br>
-; CHECK-EL: or $[[R14:[0-9]+]], $[[R13]], $[[R18]]<br>
-; CHECK-EL: sc $[[R14]], 0($[[R2]])<br>
-; CHECK-EL: beqz $[[R14]], $[[BB0]]<br>
-<br>
-; CHECK-EL: and $[[R15:[0-9]+]], $[[R10]], $[[R6]]<br>
-; CHECK-EL: srlv $[[R16:[0-9]+]], $[[R15]], $[[R4]]<br>
-; CHECK-EL: sll $[[R17:[0-9]+]], $[[R16]], 24<br>
-; CHECK-EL: sra $2, $[[R17]], 24<br>
-<br>
-; CHECK-EB-LABEL: AtomicSwap8:<br>
-; CHECK-EB: lw $[[R0:[0-9]+]], %got(y)<br>
-; CHECK-EB: addiu $[[R1:[0-9]+]], $zero, -4<br>
-; CHECK-EB: and $[[R2:[0-9]+]], $[[R0]], $[[R1]]<br>
-; CHECK-EB: andi $[[R3:[0-9]+]], $[[R0]], 3<br>
-; CHECK-EB: xori $[[R4:[0-9]+]], $[[R3]], 3<br>
-; CHECK-EB: sll $[[R5:[0-9]+]], $[[R4]], 3<br>
-; CHECK-EB: ori $[[R6:[0-9]+]], $zero, 255<br>
-; CHECK-EB: sllv $[[R7:[0-9]+]], $[[R6]], $[[R5]]<br>
-; CHECK-EB: nor $[[R8:[0-9]+]], $zero, $[[R7]]<br>
-; CHECK-EB: sllv $[[R9:[0-9]+]], $4, $[[R5]]<br>
-<br>
-; CHECK-EB: $[[BB0:[A-Z_0-9]+]]:<br>
-; CHECK-EB: ll $[[R10:[0-9]+]], 0($[[R2]])<br>
-; CHECK-EB: and $[[R18:[0-9]+]], $[[R9]], $[[R7]]<br>
-; CHECK-EB: and $[[R13:[0-9]+]], $[[R10]], $[[R8]]<br>
-; CHECK-EB: or $[[R14:[0-9]+]], $[[R13]], $[[R18]]<br>
-; CHECK-EB: sc $[[R14]], 0($[[R2]])<br>
-; CHECK-EB: beqz $[[R14]], $[[BB0]]<br>
-<br>
-; CHECK-EB: and $[[R15:[0-9]+]], $[[R10]], $[[R7]]<br>
-; CHECK-EB: srlv $[[R16:[0-9]+]], $[[R15]], $[[R5]]<br>
-; CHECK-EB: sll $[[R17:[0-9]+]], $[[R16]], 24<br>
-; CHECK-EB: sra $2, $[[R17]], 24<br>
+; ALL-LABEL: AtomicSwap8:<br>
+<br>
+; ALL: lw $[[R0:[0-9]+]], %got(y)<br>
+; ALL: addiu $[[R1:[0-9]+]], $zero, -4<br>
+; ALL: and $[[R2:[0-9]+]], $[[R0]], $[[R1]]<br>
+; ALL: andi $[[R3:[0-9]+]], $[[R0]], 3<br>
+; CHECK-EL: sll $[[R5:[0-9]+]], $[[R3]], 3<br>
+; CHECK-EB: xori $[[R4:[0-9]+]], $[[R3]], 3<br>
+; CHECK-EB: sll $[[R5:[0-9]+]], $[[R4]], 3<br>
+; ALL: ori $[[R6:[0-9]+]], $zero, 255<br>
+; ALL: sllv $[[R7:[0-9]+]], $[[R6]], $[[R5]]<br>
+; ALL: nor $[[R8:[0-9]+]], $zero, $[[R7]]<br>
+; ALL: sllv $[[R9:[0-9]+]], $4, $[[R5]]<br>
+<br>
+; ALL: $[[BB0:[A-Z_0-9]+]]:<br>
+; ALL: ll $[[R10:[0-9]+]], 0($[[R2]])<br>
+; ALL: and $[[R18:[0-9]+]], $[[R9]], $[[R7]]<br>
+; ALL: and $[[R13:[0-9]+]], $[[R10]], $[[R8]]<br>
+; ALL: or $[[R14:[0-9]+]], $[[R13]], $[[R18]]<br>
+; ALL: sc $[[R14]], 0($[[R2]])<br>
+; ALL: beqz $[[R14]], $[[BB0]]<br>
+<br>
+; ALL: and $[[R15:[0-9]+]], $[[R10]], $[[R7]]<br>
+; ALL: srlv $[[R16:[0-9]+]], $[[R15]], $[[R5]]<br>
+; ALL: sll $[[R17:[0-9]+]], $[[R16]], 24<br>
+; ALL: sra $2, $[[R17]], 24<br>
}<br>
define signext i8 @AtomicCmpSwap8(i8 signext %oldval, i8 signext %newval) nounwind {<br>
@@ -338,64 +217,37 @@ entry:<br>
%0 = extractvalue { i8, i1 } %pair0, 0<br>
ret i8 %0<br>
-; CHECK-EL-LABEL: AtomicCmpSwap8:<br>
-; CHECK-EL: lw $[[R0:[0-9]+]], %got(y)<br>
-; CHECK-EL: addiu $[[R1:[0-9]+]], $zero, -4<br>
-; CHECK-EL: and $[[R2:[0-9]+]], $[[R0]], $[[R1]]<br>
-; CHECK-EL: andi $[[R3:[0-9]+]], $[[R0]], 3<br>
-; CHECK-EL: sll $[[R4:[0-9]+]], $[[R3]], 3<br>
-; CHECK-EL: ori $[[R5:[0-9]+]], $zero, 255<br>
-; CHECK-EL: sllv $[[R6:[0-9]+]], $[[R5]], $[[R4]]<br>
-; CHECK-EL: nor $[[R7:[0-9]+]], $zero, $[[R6]]<br>
-; CHECK-EL: andi $[[R8:[0-9]+]], $4, 255<br>
-; CHECK-EL: sllv $[[R9:[0-9]+]], $[[R8]], $[[R4]]<br>
-; CHECK-EL: andi $[[R10:[0-9]+]], $5, 255<br>
-; CHECK-EL: sllv $[[R11:[0-9]+]], $[[R10]], $[[R4]]<br>
-<br>
-; CHECK-EL: $[[BB0:[A-Z_0-9]+]]:<br>
-; CHECK-EL: ll $[[R12:[0-9]+]], 0($[[R2]])<br>
-; CHECK-EL: and $[[R13:[0-9]+]], $[[R12]], $[[R6]]<br>
-; CHECK-EL: bne $[[R13]], $[[R9]], $[[BB1:[A-Z_0-9]+]]<br>
-<br>
-; CHECK-EL: and $[[R14:[0-9]+]], $[[R12]], $[[R7]]<br>
-; CHECK-EL: or $[[R15:[0-9]+]], $[[R14]], $[[R11]]<br>
-; CHECK-EL: sc $[[R15]], 0($[[R2]])<br>
-; CHECK-EL: beqz $[[R15]], $[[BB0]]<br>
-<br>
-; CHECK-EL: $[[BB1]]:<br>
-; CHECK-EL: srlv $[[R16:[0-9]+]], $[[R13]], $[[R4]]<br>
-; CHECK-EL: sll $[[R17:[0-9]+]], $[[R16]], 24<br>
-; CHECK-EL: sra $2, $[[R17]], 24<br>
-<br>
-; CHECK-EB-LABEL: AtomicCmpSwap8:<br>
-; CHECK-EB: lw $[[R0:[0-9]+]], %got(y)<br>
-; CHECK-EB: addiu $[[R1:[0-9]+]], $zero, -4<br>
-; CHECK-EB: and $[[R2:[0-9]+]], $[[R0]], $[[R1]]<br>
-; CHECK-EB: andi $[[R3:[0-9]+]], $[[R0]], 3<br>
-; CHECK-EB: xori $[[R4:[0-9]+]], $[[R3]], 3<br>
-; CHECK-EB: sll $[[R5:[0-9]+]], $[[R4]], 3<br>
-; CHECK-EB: ori $[[R6:[0-9]+]], $zero, 255<br>
-; CHECK-EB: sllv $[[R7:[0-9]+]], $[[R6]], $[[R5]]<br>
-; CHECK-EB: nor $[[R8:[0-9]+]], $zero, $[[R7]]<br>
-; CHECK-EB: andi $[[R9:[0-9]+]], $4, 255<br>
-; CHECK-EB: sllv $[[R10:[0-9]+]], $[[R9]], $[[R5]]<br>
-; CHECK-EB: andi $[[R11:[0-9]+]], $5, 255<br>
-; CHECK-EB: sllv $[[R12:[0-9]+]], $[[R11]], $[[R5]]<br>
-<br>
-; CHECK-EB: $[[BB0:[A-Z_0-9]+]]:<br>
-; CHECK-EB: ll $[[R13:[0-9]+]], 0($[[R2]])<br>
-; CHECK-EB: and $[[R14:[0-9]+]], $[[R13]], $[[R7]]<br>
-; CHECK-EB: bne $[[R14]], $[[R10]], $[[BB1:[A-Z_0-9]+]]<br>
-<br>
-; CHECK-EB: and $[[R15:[0-9]+]], $[[R13]], $[[R8]]<br>
-; CHECK-EB: or $[[R16:[0-9]+]], $[[R15]], $[[R12]]<br>
-; CHECK-EB: sc $[[R16]], 0($[[R2]])<br>
-; CHECK-EB: beqz $[[R16]], $[[BB0]]<br>
-<br>
-; CHECK-EB: $[[BB1]]:<br>
-; CHECK-EB: srlv $[[R17:[0-9]+]], $[[R14]], $[[R5]]<br>
-; CHECK-EB: sll $[[R18:[0-9]+]], $[[R17]], 24<br>
-; CHECK-EB: sra $2, $[[R18]], 24<br>
+; ALL-LABEL: AtomicCmpSwap8:<br>
+<br>
+; ALL: lw $[[R0:[0-9]+]], %got(y)<br>
+; ALL: addiu $[[R1:[0-9]+]], $zero, -4<br>
+; ALL: and $[[R2:[0-9]+]], $[[R0]], $[[R1]]<br>
+; ALL: andi $[[R3:[0-9]+]], $[[R0]], 3<br>
+; CHECK-EL: sll $[[R5:[0-9]+]], $[[R3]], 3<br>
+; CHECK-EB: xori $[[R4:[0-9]+]], $[[R3]], 3<br>
+; CHECK-EB: sll $[[R5:[0-9]+]], $[[R4]], 3<br>
+; ALL: ori $[[R6:[0-9]+]], $zero, 255<br>
+; ALL: sllv $[[R7:[0-9]+]], $[[R6]], $[[R5]]<br>
+; ALL: nor $[[R8:[0-9]+]], $zero, $[[R7]]<br>
+; ALL: andi $[[R9:[0-9]+]], $4, 255<br>
+; ALL: sllv $[[R10:[0-9]+]], $[[R9]], $[[R5]]<br>
+; ALL: andi $[[R11:[0-9]+]], $5, 255<br>
+; ALL: sllv $[[R12:[0-9]+]], $[[R11]], $[[R5]]<br>
+<br>
+; ALL: $[[BB0:[A-Z_0-9]+]]:<br>
+; ALL: ll $[[R13:[0-9]+]], 0($[[R2]])<br>
+; ALL: and $[[R14:[0-9]+]], $[[R13]], $[[R7]]<br>
+; ALL: bne $[[R14]], $[[R10]], $[[BB1:[A-Z_0-9]+]]<br>
+<br>
+; ALL: and $[[R15:[0-9]+]], $[[R13]], $[[R8]]<br>
+; ALL: or $[[R16:[0-9]+]], $[[R15]], $[[R12]]<br>
+; ALL: sc $[[R16]], 0($[[R2]])<br>
+; ALL: beqz $[[R16]], $[[BB0]]<br>
+<br>
+; ALL: $[[BB1]]:<br>
+; ALL: srlv $[[R17:[0-9]+]], $[[R14]], $[[R5]]<br>
+; ALL: sll $[[R18:[0-9]+]], $[[R17]], 24<br>
+; ALL: sra $2, $[[R18]], 24<br>
}<br>
@countsint = common global i32 0, align 4<br>
@@ -405,19 +257,13 @@ entry:<br>
%0 = atomicrmw add i32* @countsint, i32 %v seq_cst<br>
ret i32 %0<br>
-; CHECK-EL-LABEL: CheckSync:<br>
-; CHECK-EL: sync 0<br>
-; CHECK-EL: ll<br>
-; CHECK-EL: sc<br>
-; CHECK-EL: beq<br>
-; CHECK-EL: sync 0<br>
-<br>
-; CHECK-EB-LABEL: CheckSync:<br>
-; CHECK-EB: sync 0<br>
-; CHECK-EB: ll<br>
-; CHECK-EB: sc<br>
-; CHECK-EB: beq<br>
-; CHECK-EB: sync 0<br>
+; ALL-LABEL: CheckSync:<br>
+<br>
+; ALL: sync 0<br>
+; ALL: ll<br>
+; ALL: sc<br>
+; ALL: beq<br>
+; ALL: sync 0<br>
}<br>
; make sure that this assertion in<br>
<br>
<br>
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