<div dir="ltr"><div><div><div><div>Hi Quentin,<br><br></div>1- Yes, they look suspicious because I forget to turn off my SWIFT pass. However, I added my SWIFT pass after ExecutionDependencyFix in ARMTargetMachcine.cpp file.<br>
....<br>bool ARMPassConfig::addPreSched2() {<br> // FIXME: temporarily disabling load / store optimization pass for Thumb1.<br><br> if (getOptLevel() != CodeGenOpt::None) {<br> if (!getARMSubtarget().isThumb1Only()) { <br>
addPass(createARMLoadStoreOptimizationPass());<br> printAndVerify("After ARM load / store optimizer");<br> }<br> if (getARMSubtarget().hasNEON())<br> addPass(createExecutionDependencyFixPass(&ARM::DPRRegClass));<br>
}<br><b><br>addPass(createSWIFT());</b> <- Here is my pass; This pass is responsible for duplicating instructions (By using reserved registers) <br><br> // Expand some pseudo instructions into multiple instructions to allow<br>
// proper scheduling.<br> addPass(createARMExpandPseudoPass());<br>....<br><br></div><div>But, the problem is not because of this SWIFT pass. <b>Please check the attached bugpoint.txt</b>, this is the one which address only to the "ran out of register during register allocation" error.<br>
</div><div><br><br></div> 2- I got the llc output for several program and cross compiled them for ARM, and ran them on gem5 simulator. They work perfectly, this error "ran out of register during register allocation" appears just on some programs such as JPEG (Mibench) and GCC from SPEC2006. <br>
<br></div>Thanks,<br></div>Danna<br><div><div><div><br><br><br></div></div></div></div><div class="gmail_extra"><br><br><div class="gmail_quote">On Wed, Jun 11, 2014 at 7:12 PM, Quentin Colombet <span dir="ltr"><<a href="mailto:qcolombet@apple.com" target="_blank">qcolombet@apple.com</a>></span> wrote:<br>
<blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"><div style="word-wrap:break-word">Hi Danna,<div><br></div><div>I haven’t look yet at all your inputs, but the MachineInstr dump for bugpoint.txt looks suspicious.</div>
<div>Let me take an example:</div><div><div>BB#0: derived from LLVM BB %entry</div><div> Live Ins: %R0 %R1 %R2 %R11 %LR</div><div><span style="white-space:pre-wrap"> </span>%R4<def> = MOVr %R0, pred:14, pred:%noreg, opt:%noreg</div>
<div><span style="white-space:pre-wrap"> </span>%R7<def> = MOVr %R1, pred:14, pred:%noreg, opt:%noreg</div><div><span style="white-space:pre-wrap"> </span>%R8<def> = MOVr %R2, pred:14, pred:%noreg, opt:%noreg</div>
<div><span style="white-space:pre-wrap"> </span>%R9<def> = MOVr %R3, pred:14, pred:%noreg, opt:%noreg <— R3 is not live in nor defined before being used</div><div><span style="white-space:pre-wrap"> </span>%R10<def> = MOVr %R11, pred:14, pred:%noreg, opt:%noreg</div>
<div><span style="white-space:pre-wrap"> </span>%R5<def> = SUBrr %R5, %R5, pred:14, pred:%noreg, opt:%noreg <— Same for R5</div></div><div><br></div><div>My questions are the following:</div><div>1. When does your pass run?</div>
<div>2. Have you checked that the produced MachineInstr IR is valid (by running the verifier after your pass)?</div><div><br></div><div>Let us first solve the verifier issues, then we will see if the register allocator is at fault.</div>
<div><br></div><div>Thanks,</div><div>-Quentin</div><div><br><div><div><div class="h5"><div>On Jun 11, 2014, at 6:31 PM, Danna bib <<a href="mailto:danna1364@gmail.com" target="_blank">danna1364@gmail.com</a>> wrote:</div>
<br></div></div><blockquote type="cite"><div><div class="h5"><div dir="ltr"><div><div><div><div><div>Hi Dear Quentin,<br><br></div>Thank you for your response.<br><br></div>I ran bugpoint, and attach the outputs to this email. Hopefully they help.<br>
<br></div><div>My command line is this:<br>
~/Desktop/Mibench/consumer/jpeg/jpeg-6a$ llc -reserveRegs=true -march=arm -O0 cjpeg.ll -o cjpeg.s <br>error: ran out of registers during register allocation<br><br></div><div>For running bugponit I used this:<br>bugpoint cjpeg.ll -llc-safe --safe-tool-args -reserveRegs=true -march=arm -O0 | tee bugpoint.txt<br>
<br></div><div><br></div>My goal is duplication of almost all assembly instructions (for applying some fault-tolerant method), So, I need to reserve half of registers for those duplicated instructions.<br><br></div>regards,<br>
</div>Danna<br></div><div class="gmail_extra"><br><br><div class="gmail_quote">On Mon, Jun 9, 2014 at 2:43 PM, Quentin Colombet <span dir="ltr"><<a href="mailto:qcolombet@apple.com" target="_blank">qcolombet@apple.com</a>></span> wrote:<br>
<blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">Hi Danna,<br>
<div><br>
On Jun 2, 2014, at 10:54 AM, Danna bib <<a href="mailto:danna1364@gmail.com" target="_blank">danna1364@gmail.com</a>> wrote:<br>
<br>
> Hello all,<br>
><br>
> I am working with LLVM 3.4. I reserved half of arm registers in order to do some optimization in backend (after register allocation). It works fine with several SPEC2006 benchmarks, but in some of them such as gcc and gobmk, I got the following error.<br>
> "LLVM ERROR: ran out of registers during register allocation"<br>
> So, my question is how I can solve that problem?<br>
<br>
</div>Without the input IR, this is hard to tell.<br>
Could you try to reduce a test case with bugpoint and we can try to help from here.<br>
<br>
The question though is why do you need to reserved so many registers?<br>
<br>
Thanks,<br>
-Quentin<br>
<div><br>
><br>
> I would appreciate any advise you may have.<br>
><br>
> regards,<br>
> Danna<br>
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</blockquote></div><br></div>
</div></div><span><bugpoint.txt></span><span><bugpoint-reduced-simplified.bc></span><span><bugpoint-reduced-function.bc></span><span><bugpoint-reduced-blocks.bc></span></blockquote></div><br></div>
</div></blockquote></div><br></div>