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<P>Hi Rafael,</P>
<P> </P>
<P>I found the bug. Basically, this was giving problem for operands having bitwidth 1.</P>
<P>It was always returning true for 'WillNotOverFlowSignedAdd' and hence the test case :</P>
<P><EM></EM> </P>
<P><EM>define i32 @foo(i32 %x, i1 %y) {<BR>%v1 = sext i1 %y to i32<BR>%v2 = add i32 %v1, -1<BR>ret i32 %v2<BR>}<BR></P></EM>
<P>was getting reduced to </P>
<P><EM>define i32 @foo(i32 %x, i1 %y) {<BR>%addconv = xor i1 %y, true<BR>%v2 = sext i1 %addconv to i32<BR>ret i32 %v2<BR></EM><EM>}</EM></P>
<P><EM></EM> </P>
<P>Because -1 is represented as 1 in 1 bit representation, and it was always returning true for NotSignedOverFlow, </P>
<P>the carry bit was getting ignored and the add was getting converted to xor operations (since 'xor' = 'add neglecting carry bit' ) </P>
<P>causing error.</P>
<P> </P>
<P>I have handled this condition in the updated patch -> return true only if one of the operand has 0 bit for BitWidth 1.</P>
<P>Added the above test case as well.</P>
<P> </P>
<P>Attaching updated patch. Please help in reviewing it.</P>
<P> </P>
<P>Thanks ! </P>
<P><BR>Regards,</P>
<P>Suyog Sarda</P>
<P> </P>
<P>------- <B>Original Message</B> -------</P>
<P><B>Sender</B> : Rafael Espíndola<rafael.espindola@gmail.com></P>
<P><B>Date</B> : May 31, 2014 04:06 (GMT+09:00)</P>
<P><B>Title</B> : Re: [llvm] r209746 - InstCombine: Improvement to check if signed addition overflows.</P>
<P> </P>> Strangely though, removing the symmetric call gives good result of<BR>> test-func.ll you had provided (I donno how but it works, even though the<BR>> second call would be dead).<BR><BR>Well, we have to understand what is wrong with it.<BR><BR>The testcase reduces to just<BR><BR>define i32 @foo(i32 %x, i1 %y) {<BR> %v1 = sext i1 %y to i32<BR> %v2 = add i32 %v1, -1<BR> ret i32 %v2<BR>}<BR><BR>which with the patch gets converted to<BR><BR>define i32 @foo(i32 %x, i1 %y) {<BR> %addconv = xor i1 %y, true<BR> %v2 = sext i1 %addconv to i32<BR> ret i32 %v2<BR>}<BR><BR>Can you step over instcombine and see what invalid transformation is being done?<BR><BR>Cheers,<BR>Rafael<BR>
<P> </P>
<P> </P><!--SP:suyog.sarda--><!--suyog.sarda:EP-->
<P> </P>
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