<HTML><BODY><p>Hi all!</p><p>I'm sorry this is my first code review, I did not find info in manuals...<br>1) Does anybody know have Phabricator the tag like <noformat> or {code} in JIRA not performing formatting?<br>2) How can I get patch using arcanist (arc diff) with available context? I think it will be automatically... (((<br><br><br><br><br><br><br><br><br><br><br><br><br><br><br><br><br><br><br><br><br><br><br><br>
Hi atrick,<br>
<br>
1) The reason why CSE ignored COPY is PerformTrivialCoalescing.<br>
If COPY insert into HASH and perform PerformTrivialCoalescing: MI->eraseFromParent()<br>
HASH will be broken. Main idea is to perform PerformTrivialCoalescing before insertion.<br>
**************************************************************************<br>
2) cross-regclass copy:<br>
We develop backend for new architecture with independent GPR and ADDRRegs classes.<br>
In this case we have redundant MOVs(between independent disjoint reg classes):<br>
move r0.l, a0.l <<<<<<<<<<<<<br>
store r2.d, (a0.l)<br>
move r0.l, a0.l <<<<<<<<<<<<<br>
store r4.d, (a0.l+8)<br>
Now CSE removes this type of MOV.<br>
**************************************************************************<br>
3) subreg copy: CodeGen\X86\cse-add-with-overflow.ll passed<br>
because we got CSE for second "add" and correspondent COPYs<br>
and "Simple Register Coalescing" performed coalescing for<br>
first "add" and correspondent COPYs (This scheme seems natural,<br>
so I removed FIXME in PerformTrivialCoalescing):<br>
//-------- dump using patch: -print-after-all:<br>
# *** IR Dump After Machine Loop Invariant Code Motion ***:<br>
# Machine code for function redundantadd: SSA<br>
Function Live Ins: %RDI in %vreg2, %RSI in %vreg3<br>
<br>
BB#0: derived from LLVM BB %entry<br>
Live Ins: %RDI %RSI<br>
%vreg3<def> = COPY %RSI; GR64:%vreg3<br>
%vreg2<def> = COPY %RDI; GR64:%vreg2<br>
%vreg0<def> = MOV64rm %vreg2, 1, %noreg, 0, %noreg; mem:LD8[%a0] GR64:%vreg0,%vreg2<br>
%vreg1<def> = MOV64rm %vreg3, 1, %noreg, 0, %noreg; mem:LD8[%a1] GR64:%vreg1,%vreg3<br>
%vreg4<def> = COPY %vreg0:sub_32bit; GR32:%vreg4 GR64:%vreg0<br>
%vreg5<def> = COPY %vreg1:sub_32bit; GR32:%vreg5 GR64:%vreg1<br>
%vreg6<def,tied1> = ADD32rr %vreg4<tied0>, %vreg5<kill>, %EFLAGS<imp-def>; GR32:%vreg6,%vreg4,%vreg5<br>
JNO_4 <BB#2>, %EFLAGS<imp-use><br>
JMP_4 <BB#1><br>
Successors according to CFG: BB#1(1) BB#2(1048575)<br>
<br>
BB#1: derived from LLVM BB %exit2<br>
Predecessors according to CFG: BB#0<br>
<br>
BB#2: derived from LLVM BB %return<br>
Predecessors according to CFG: BB#0<br>
>>>>>>>>> %vreg7<def> = COPY %vreg0:sub_32bit; GR32:%vreg7 GR64:%vreg0<br>
>>>>>>>>> %vreg8<def> = COPY %vreg1:sub_32bit; GR32:%vreg8 GR64:%vreg1<br>
>>>>>>>>> %vreg9<def,tied1> = ADD32rr %vreg8<tied0>, %vreg7<kill>, %EFLAGS<imp-def,dead>; GR32:%vreg9,%vreg8,%vreg7<br>
%vreg10<def> = SUBREG_TO_REG 0, %vreg9<kill>, 4; GR64:%vreg10 GR32:%vreg9<br>
%RAX<def> = COPY %vreg10; GR64:%vreg10<br>
RETQ %RAX<br>
<br>
# End machine code for function redundantadd.<br>
<br>
# *** IR Dump After Machine Common Subexpression Elimination ***:<br>
# Machine code for function redundantadd: SSA<br>
Function Live Ins: %RDI in %vreg2, %RSI in %vreg3<br>
<br>
BB#0: derived from LLVM BB %entry<br>
Live Ins: %RDI %RSI<br>
%vreg3<def> = COPY %RSI; GR64:%vreg3<br>
%vreg2<def> = COPY %RDI; GR64:%vreg2<br>
%vreg0<def> = MOV64rm %vreg2, 1, %noreg, 0, %noreg; mem:LD8[%a0] GR64:%vreg0,%vreg2<br>
%vreg1<def> = MOV64rm %vreg3, 1, %noreg, 0, %noreg; mem:LD8[%a1] GR64:%vreg1,%vreg3<br>
%vreg4<def> = COPY %vreg0:sub_32bit; GR32:%vreg4 GR64:%vreg0<br>
%vreg5<def> = COPY %vreg1:sub_32bit; GR32:%vreg5 GR64:%vreg1<br>
%vreg6<def,tied1> = ADD32rr %vreg4<tied0>, %vreg5, %EFLAGS<imp-def>; GR32:%vreg6,%vreg4,%vreg5<br>
JNO_4 <BB#2>, %EFLAGS<imp-use><br>
JMP_4 <BB#1><br>
Successors according to CFG: BB#1(1) BB#2(1048575)<br>
<br>
BB#1: derived from LLVM BB %exit2<br>
Predecessors according to CFG: BB#0<br>
<br>
BB#2: derived from LLVM BB %return<br>
Predecessors according to CFG: BB#0<br>
%vreg10<def> = SUBREG_TO_REG 0, %vreg6, 4; GR64:%vreg10 GR32:%vreg6<br>
%RAX<def> = COPY %vreg10; GR64:%vreg10<br>
RETQ %RAX<br>
<br>
# End machine code for function redundantadd.<br>
.........................................<br>
.........................................<br>
# *** IR Dump After Live Interval Analysis ***:<br>
# Machine code for function redundantadd: Post SSA<br>
Function Live Ins: %RDI in %vreg2, %RSI in %vreg3<br>
<br>
0B BB#0: derived from LLVM BB %entry<br>
Live Ins: %RDI %RSI<br>
16B %vreg3<def> = COPY %RSI; GR64:%vreg3<br>
32B %vreg2<def> = COPY %RDI; GR64:%vreg2<br>
48B %vreg0<def> = MOV64rm %vreg2, 1, %noreg, 0, %noreg; mem:LD8[%a0] GR64:%vreg0,%vreg2<br>
64B %vreg1<def> = MOV64rm %vreg3, 1, %noreg, 0, %noreg; mem:LD8[%a1] GR64:%vreg1,%vreg3<br>
>>>>>>>>>>80B %vreg4<def> = COPY %vreg0:sub_32bit; GR32:%vreg4 GR64:%vreg0<br>
>>>>>>>>>>96B %vreg5<def> = COPY %vreg1:sub_32bit; GR32:%vreg5 GR64:%vreg1<br>
>>>>>>>>>>112B %vreg6<def> = COPY %vreg5; GR32:%vreg6,%vreg5<br>
128B %vreg6<def,tied1> = ADD32rr %vreg6<tied0>, %vreg4, %EFLAGS<imp-def>; GR32:%vreg6,%vreg4<br>
144B JNO_4 <BB#2>, %EFLAGS<imp-use,kill><br>
160B JMP_4 <BB#1><br>
Successors according to CFG: BB#1(1) BB#2(1048575)<br>
<br>
176B BB#1: derived from LLVM BB %exit2<br>
Predecessors according to CFG: BB#0<br>
<br>
192B BB#2: derived from LLVM BB %return<br>
Predecessors according to CFG: BB#0<br>
208B %vreg10<def> = SUBREG_TO_REG 0, %vreg6, 4; GR64:%vreg10 GR32:%vreg6<br>
224B %RAX<def> = COPY %vreg10; GR64:%vreg10<br>
240B RETQ %RAX<kill><br>
<br>
# End machine code for function redundantadd.<br>
<br>
# *** IR Dump After Simple Register Coalescing ***:<br>
# Machine code for function redundantadd: Post SSA<br>
Function Live Ins: %RDI in %vreg2, %RSI in %vreg3<br>
<br>
0B BB#0: derived from LLVM BB %entry<br>
Live Ins: %RDI %RSI<br>
16B %vreg3<def> = COPY %RSI; GR64:%vreg3<br>
32B %vreg2<def> = COPY %RDI; GR64:%vreg2<br>
48B %vreg0<def> = MOV64rm %vreg2, 1, %noreg, 0, %noreg; mem:LD8[%a0] GR64_with_sub_8bit:%vreg0 GR64:%vreg2<br>
64B %vreg10<def> = MOV64rm %vreg3, 1, %noreg, 0, %noreg; mem:LD8[%a1] GR64_with_sub_8bit:%vreg10 GR64:%vreg3<br>
128B %vreg10:sub_32bit<def,tied1> = ADD32rr %vreg10:sub_32bit<tied0>, %vreg0:sub_32bit, %EFLAGS<imp-def>; GR64_with_sub_8bit:%vreg10,%vreg0<br>
144B JNO_4 <BB#2>, %EFLAGS<imp-use,kill><br>
160B JMP_4 <BB#1><br>
Successors according to CFG: BB#1(1) BB#2(1048575)<br>
<br>
176B BB#1: derived from LLVM BB %exit2<br>
Predecessors according to CFG: BB#0<br>
<br>
192B BB#2: derived from LLVM BB %return<br>
Predecessors according to CFG: BB#0<br>
224B %RAX<def> = COPY %vreg10; GR64_with_sub_8bit:%vreg10<br>
240B RETQ %RAX<kill><br>
<br>
# End machine code for function redundantadd.<br>
<br>
//--------<br>
Also I modified cse-add-with-overflow.ll to minimize test.<br>
**************************************************************************<br>
4) problem with CodeGen/X86/inline-asm-fpstack.ll:<br>
//-------- dump: -print-after-all:<br>
# *** IR Dump After Machine Loop Invariant Code Motion ***:<br>
# Machine code for function testPR4185b: Post SSA<br>
Constant Pool:<br>
cp#0: 1.000000e+06, align=4<br>
<br>
BB#0: derived from LLVM BB %return<br>
%FP0<def> = LD_Fp32m80 %noreg, 1, %noreg, <cp#0>, %noreg, %FPSW<imp-def,dead>; mem:LD4[ConstantPool]<br>
>>>>>>> %ST0<def> = COPY %FP0<br>
INLINEASM <es:fistl $0> [sideeffect] [attdialect], $0:[reguse], %ST0<br>
>>>>>>> %ST0<def> = COPY %FP0<kill><br>
INLINEASM <es:fistpl $0> [sideeffect] [attdialect], $0:[reguse], %ST0, $1:[clobber], %ST0<earlyclobber,imp-def><br>
RETL<br>
<br>
# End machine code for function testPR4185b.<br>
<br>
# *** IR Dump After Prologue/Epilogue Insertion & Frame Finalization ***:<br>
# Machine code for function testPR4185b: Post SSA<br>
Constant Pool:<br>
cp#0: 1.000000e+06, align=4<br>
<br>
BB#0: derived from LLVM BB %return<br>
LD_F32m %noreg, 1, %noreg, <cp#0>, %noreg, %FPSW<imp-def,dead>; mem:LD4[ConstantPool]<br>
INLINEASM <es:fistl $0> [sideeffect] [attdialect], $0:[reguse], %ST0<br>
INLINEASM <es:fistpl $0> [sideeffect] [attdialect], $0:[reguse], %ST0, $1:[clobber], %ST0<earlyclobber,imp-def><br>
RETL<br>
<br>
# End machine code for function testPR4185b.<br>
<br>
//-------- dump using patch:<br>
# *** IR Dump After Machine Loop Invariant Code Motion ***:<br>
# Machine code for function testPR4185b: Post SSA<br>
Constant Pool:<br>
cp#0: 1.000000e+06, align=4<br>
<br>
BB#0: derived from LLVM BB %return<br>
%FP0<def> = LD_Fp32m80 %noreg, 1, %noreg, <cp#0>, %noreg, %FPSW<imp-def,dead>; mem:LD4[ConstantPool]<br>
>>>>>>>>> %ST0<def> = COPY %FP0<kill><br>
INLINEASM <es:fistl $0> [sideeffect] [attdialect], $0:[reguse], %ST0<br>
INLINEASM <es:fistpl $0> [sideeffect] [attdialect], $0:[reguse], %ST0, $1:[clobber], %ST0<earlyclobber,imp-def><br>
RETL<br>
<br>
# End machine code for function testPR4185b.<br>
<br>
# *** IR Dump After Prologue/Epilogue Insertion & Frame Finalization ***:<br>
# Machine code for function testPR4185b: Post SSA<br>
Constant Pool:<br>
cp#0: 1.000000e+06, align=4<br>
<br>
BB#0: derived from LLVM BB %return<br>
LD_F32m %noreg, 1, %noreg, <cp#0>, %noreg, %FPSW<imp-def,dead>; mem:LD4[ConstantPool]<br>
INLINEASM <es:fistl $0> [sideeffect] [attdialect], $0:[reguse], %ST0<br>
>>>>>>>>??? ST_FPrr %ST0, %FPSW<imp-def><br>
>>>>>>>>??? LD_F0 %FPSW<imp-def><br>
INLINEASM <es:fistpl $0> [sideeffect] [attdialect], $0:[reguse], %ST0, $1:[clobber], %ST0<earlyclobber,imp-def><br>
RETL<br>
<br>
# End machine code for function testPR4185b.<br>
<br>
//--------<br>
I'm looking for why "Prologue/Epilogue Insertion" include<br>
ST_FPrr %ST0, %FPSW<imp-def><br>
LD_F0 %FPSW<imp-def><br>
asap. For now we have option -cse-ignore-copy with correspondent FIXME.<br>
<br>
<a href="http://reviews.llvm.org/D3948" target="_blank">http://reviews.llvm.org/D3948</a><br>
<br>
Files:<br>
lib/CodeGen/MachineCSE.cpp<br>
test/CodeGen/ARM/atomic-64bit.ll<br>
test/CodeGen/ARM/debug-info-branch-folding.ll<br>
test/CodeGen/X86/cse-add-with-overflow.ll<br>
test/CodeGen/X86/inline-asm-fpstack.ll<br>
<br>
<br></p><hr>
<br>-- <br>Данил Трошков<br></BODY></HTML>