<html><head><meta http-equiv="Content-Type" content="text/html charset=us-ascii"></head><body style="word-wrap: break-word; -webkit-nbsp-mode: space; -webkit-line-break: after-white-space;">On May 20, 2014, at 3:49 PM, Alexey Samsonov <<a href="mailto:samsonov@google.com">samsonov@google.com</a>> wrote:<br><div><div><br class="Apple-interchange-newline"><blockquote type="cite"><div dir="ltr"><div class="gmail_extra"><br><div class="gmail_quote">On Tue, May 20, 2014 at 2:47 PM, Adam Nemet <span dir="ltr"><<a href="mailto:anemet@apple.com" target="_blank">anemet@apple.com</a>></span> wrote:<br>
<blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left-width:1px;border-left-color:rgb(204,204,204);border-left-style:solid;padding-left:1ex">Author: anemet<br>
Date: Tue May 20 16:47:07 2014<br>
New Revision: 209242<br>
<br>
URL: <a href="http://llvm.org/viewvc/llvm-project?rev=209242&view=rev" target="_blank">http://llvm.org/viewvc/llvm-project?rev=209242&view=rev</a><br>
Log:<br>
[ARM64] PR19792: Fix cycle in DAG after performPostLD1Combine<br>
<br>
Povray and dealII currently assert with "Overran sorted position" in<br>
AssignTopologicalOrder. The problem is that performPostLD1Combine can<br>
introduce cycles.<br>
<br>
Consider:<br>
<br>
(insert_vector_elt (INSERT_SUBREG undef,<br>
(load (add %vreg0, Constant<8>), undef), <= A<br>
TargetConstant<2>),<br>
(load %vreg0, undef), <= B<br>
Constant<1>)<br>
<br>
This is turned into a LD1LANEpost node. However the address in A is not a<br>
valid user of the post-incremented address of B in LD1LANEpost.<br>
<br>
Added:<br>
llvm/trunk/test/CodeGen/ARM64/indexed-vector-ldst-2.ll<br>
Modified:<br>
llvm/trunk/lib/Target/ARM64/ARM64ISelLowering.cpp<br>
<br>
Modified: llvm/trunk/lib/Target/ARM64/ARM64ISelLowering.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM64/ARM64ISelLowering.cpp?rev=209242&r1=209241&r2=209242&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM64/ARM64ISelLowering.cpp?rev=209242&r1=209241&r2=209242&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/ARM64/ARM64ISelLowering.cpp (original)<br>
+++ llvm/trunk/lib/Target/ARM64/ARM64ISelLowering.cpp Tue May 20 16:47:07 2014<br>
@@ -7298,6 +7298,7 @@ static SDValue performPostLD1Combine(SDN<br>
}<br>
<br>
SDValue Addr = LD->getOperand(1);<br>
+ SDValue Vector = N->getOperand(0);<br>
// Search for a use of the address operand that is an increment.<br>
for (SDNode::use_iterator UI = Addr.getNode()->use_begin(), UE =<br>
Addr.getNode()->use_end(); UI != UE; ++UI) {<br>
@@ -7310,6 +7311,10 @@ static SDValue performPostLD1Combine(SDN<br>
// would create a cycle.<br>
if (User->isPredecessorOf(LD) || LD->isPredecessorOf(User))<br>
continue;<br>
+ // Also check that add is not used in the vector operand. This would also<br>
+ // create a cycle.<br>
+ if (User->isPredecessorOf(Vector.getNode()))<br>
+ continue;<br>
<br>
// If the increment is a constant, it must match the memory ref size.<br>
SDValue Inc = User->getOperand(User->getOperand(0) == Addr ? 1 : 0);<br>
@@ -7324,7 +7329,7 @@ static SDValue performPostLD1Combine(SDN<br>
SmallVector<SDValue, 8> Ops;<br>
Ops.push_back(LD->getOperand(0)); // Chain<br>
if (IsLaneOp) {<br>
- Ops.push_back(N->getOperand(0)); // The vector to be inserted<br>
+ Ops.push_back(Vector); // The vector to be inserted<br>
Ops.push_back(N->getOperand(2)); // The lane to be inserted in the vector<br>
}<br>
Ops.push_back(Addr);<br>
<br>
Added: llvm/trunk/test/CodeGen/ARM64/indexed-vector-ldst-2.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM64/indexed-vector-ldst-2.ll?rev=209242&view=auto" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM64/indexed-vector-ldst-2.ll?rev=209242&view=auto</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/ARM64/indexed-vector-ldst-2.ll (added)<br>
+++ llvm/trunk/test/CodeGen/ARM64/indexed-vector-ldst-2.ll Tue May 20 16:47:07 2014<br>
@@ -0,0 +1,40 @@<br>
+; RUN: llc %s<br></blockquote><div><br></div><div>^^</div><div>This line would create file test/CodeGen/ARM64/indexed-vector-ldst-2.s in the source tree. I've mailed a fix in r209252.</div></div></div></div></blockquote><div><br></div><div>Ah! Sorry about that and thanks for the fix!</div><div><br></div><div>Adam</div><br><blockquote type="cite"><div dir="ltr"><div class="gmail_extra"><div class="gmail_quote"><div> </div><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left-width:1px;border-left-color:rgb(204,204,204);border-left-style:solid;padding-left:1ex">
+<br>
+; This used to assert with "Overran sorted position" in AssignTopologicalOrder<br>
+; due to a cycle created in performPostLD1Combine.<br>
+<br>
+target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"<br>
+target triple = "arm64-apple-ios7.0.0"<br>
+<br>
+; Function Attrs: nounwind ssp<br>
+define void @f(double* %P1) #0 {<br>
+entry:<br>
+ %arrayidx4 = getelementptr inbounds double* %P1, i64 1<br>
+ %0 = load double* %arrayidx4, align 8, !tbaa !1<br>
+ %1 = load double* %P1, align 8, !tbaa !1<br>
+ %2 = insertelement <2 x double> undef, double %0, i32 0<br>
+ %3 = insertelement <2 x double> %2, double %1, i32 1<br>
+ %4 = fsub <2 x double> zeroinitializer, %3<br>
+ %5 = fmul <2 x double> undef, %4<br>
+ %6 = extractelement <2 x double> %5, i32 0<br>
+ %cmp168 = fcmp olt double %6, undef<br>
+ br i1 %cmp168, label %if.then172, label %return<br>
+<br>
+if.then172: ; preds = %cond.end90<br>
+ %7 = tail call i64 @llvm.objectsize.i64.p0i8(i8* undef, i1 false)<br>
+ br label %return<br>
+<br>
+return: ; preds = %if.then172, %cond.end90, %entry<br>
+ ret void<br>
+}<br>
+<br>
+; Function Attrs: nounwind readnone<br>
+declare i64 @llvm.objectsize.i64.p0i8(i8*, i1) #1<br>
+<br>
+attributes #0 = { nounwind ssp "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }<br>
+attributes #1 = { nounwind readnone }<br>
+<br>
+!1 = metadata !{metadata !2, metadata !2, i64 0}<br>
+!2 = metadata !{metadata !"double", metadata !3, i64 0}<br>
+!3 = metadata !{metadata !"omnipotent char", metadata !4, i64 0}<br>
+!4 = metadata !{metadata !"Simple C/C++ TBAA"}<br>
<br>
<br>
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</blockquote></div><br><br clear="all"><div><br></div>-- <br><div dir="ltr">Alexey Samsonov, Mountain View, CA</div>
</div></div>
</blockquote></div><br></div></body></html>