<div dir="ltr">This test fails on Windows:<div><a href="http://bb.pgr.jp/builders/ninja-x64-msvc-RA-centos6/builds/2682">http://bb.pgr.jp/builders/ninja-x64-msvc-RA-centos6/builds/2682</a><br></div><div><br></div><div>The Windows target is thumb-only. You need to add a triple.</div>
</div><div class="gmail_extra"><br><br><div class="gmail_quote">On Mon, May 12, 2014 at 12:53 PM, Louis Gerbarg <span dir="ltr"><<a href="mailto:lgg@apple.com" target="_blank">lgg@apple.com</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">
Author: louis<br>
Date: Mon May 12 14:53:52 2014<br>
New Revision: 208620<br>
<br>
URL: <a href="http://llvm.org/viewvc/llvm-project?rev=208620&view=rev" target="_blank">http://llvm.org/viewvc/llvm-project?rev=208620&view=rev</a><br>
Log:<br>
Add support bswap16 to/from memory compiling to rev16 on ARM/Thumb<br>
<br>
The current patterns for REV16 misses mostn __builtin_bswap16() due to<br>
legalization promoting the operands to from load/stores toi32s and then<br>
truncing/extending them. This patch adds new patterns that catch the resultant<br>
DAGs and codegens them to rev16 instructions. Tests included.<br>
<br>
rdar://15353652<br>
<br>
Added:<br>
llvm/trunk/test/CodeGen/ARM/bswap16.ll<br>
Modified:<br>
llvm/trunk/lib/Target/ARM/ARMInstrInfo.td<br>
llvm/trunk/lib/Target/ARM/ARMInstrThumb.td<br>
<br>
Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=208620&r1=208619&r2=208620&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=208620&r1=208619&r2=208620&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original)<br>
+++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Mon May 12 14:53:52 2014<br>
@@ -4122,6 +4122,11 @@ def REV16 : AMiscA1I<0b01101011, 0b1011,<br>
Requires<[IsARM, HasV6]>,<br>
Sched<[WriteALU]>;<br>
<br>
+def : ARMV6Pat<(srl (bswap (extloadi16 addrmode3:$addr)), (i32 16)),<br>
+ (REV16 (LDRH addrmode3:$addr))>;<br>
+def : ARMV6Pat<(truncstorei16 (srl (bswap GPR:$Rn), (i32 16)), addrmode3:$addr),<br>
+ (STRH (REV16 GPR:$Rn), addrmode3:$addr)>;<br>
+<br>
let AddedComplexity = 5 in<br>
def REVSH : AMiscA1I<0b01101111, 0b1011, (outs GPR:$Rd), (ins GPR:$Rm),<br>
IIC_iUNAr, "revsh", "\t$Rd, $Rm",<br>
<br>
Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb.td<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb.td?rev=208620&r1=208619&r2=208620&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb.td?rev=208620&r1=208619&r2=208620&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/ARM/ARMInstrThumb.td (original)<br>
+++ llvm/trunk/lib/Target/ARM/ARMInstrThumb.td Mon May 12 14:53:52 2014<br>
@@ -1308,6 +1308,18 @@ def : T1Pat<(addc tGPR:$lhs, imm8_255_<br>
def : T1Pat<(subc tGPR:$lhs, tGPR:$rhs),<br>
(tSUBrr tGPR:$lhs, tGPR:$rhs)>;<br>
<br>
+// Bswap 16 with load/store<br>
+def : T1Pat<(srl (bswap (extloadi16 t_addrmode_rrs2:$addr)), (i32 16)),<br>
+ (tREV16 (tLDRHr t_addrmode_rrs2:$addr))>;<br>
+def : T1Pat<(srl (bswap (extloadi16 t_addrmode_is2:$addr)), (i32 16)),<br>
+ (tREV16 (tLDRHi t_addrmode_is2:$addr))>;<br>
+def : T1Pat<(truncstorei16 (srl (bswap tGPR:$Rn), (i32 16)),<br>
+ t_addrmode_rrs2:$addr),<br>
+ (tSTRHr (tREV16 tGPR:$Rn), t_addrmode_rrs2:$addr)>;<br>
+def : T1Pat<(truncstorei16 (srl (bswap tGPR:$Rn), (i32 16)),<br>
+ t_addrmode_is2:$addr),<br>
+ (tSTRHi(tREV16 tGPR:$Rn), t_addrmode_is2:$addr)>;<br>
+<br>
// ConstantPool<br>
def : T1Pat<(ARMWrapper tconstpool :$dst), (tLEApcrel tconstpool :$dst)>;<br>
<br>
<br>
Added: llvm/trunk/test/CodeGen/ARM/bswap16.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/bswap16.ll?rev=208620&view=auto" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/bswap16.ll?rev=208620&view=auto</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/ARM/bswap16.ll (added)<br>
+++ llvm/trunk/test/CodeGen/ARM/bswap16.ll Mon May 12 14:53:52 2014<br>
@@ -0,0 +1,42 @@<br>
+; RUN: llc -march=arm -mattr=v6 < %s | FileCheck %s<br>
+; RUN: llc -march=thumb -mattr=v6 < %s | FileCheck %s<br>
+<br>
+<br>
+define void @test1(i16* nocapture %data) {<br>
+entry:<br>
+ %0 = load i16* %data, align 2<br>
+ %1 = tail call i16 @llvm.bswap.i16(i16 %0)<br>
+ store i16 %1, i16* %data, align 2<br>
+ ret void<br>
+<br>
+ ; CHECK-LABEL: test1:<br>
+ ; CHECK: ldrh r[[R1:[0-9]+]], [r0]<br>
+ ; CHECK: rev16 r[[R1]], r[[R1]]<br>
+ ; CHECK: strh r[[R1]], [r0]<br>
+}<br>
+<br>
+<br>
+define void @test2(i16* nocapture %data, i16 zeroext %in) {<br>
+entry:<br>
+ %0 = tail call i16 @llvm.bswap.i16(i16 %in)<br>
+ store i16 %0, i16* %data, align 2<br>
+ ret void<br>
+<br>
+ ; CHECK-LABEL: test2:<br>
+ ; CHECK: rev16 r[[R1:[0-9]+]], r1<br>
+ ; CHECK: strh r[[R1]], [r0]<br>
+}<br>
+<br>
+<br>
+define i16 @test3(i16* nocapture %data) {<br>
+entry:<br>
+ %0 = load i16* %data, align 2<br>
+ %1 = tail call i16 @llvm.bswap.i16(i16 %0)<br>
+ ret i16 %1<br>
+<br>
+ ; CHECK-LABEL: test3:<br>
+ ; CHECK: ldrh r[[R0:[0-9]+]], [r0]<br>
+ ; CHECK: rev16 r[[R0]], r0<br>
+}<br>
+<br>
+declare i16 @llvm.bswap.i16(i16)<br>
<br>
<br>
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</blockquote></div><br></div>