<html><head><meta http-equiv="content-type" content="text/html; charset=utf-8"></head><body dir="auto"><div><div style="direction: ltr;"><span style="-webkit-text-size-adjust: auto;">Excellent. Thank you Filipe. </span></div><br></div><div style="-webkit-text-size-adjust: auto;"><br>On May 11, 2014, at 2:47, Filipe Cabecinhas <<a href="mailto:me@filcab.net">me@filcab.net</a>> wrote:<br><br></div><blockquote type="cite" style="-webkit-text-size-adjust: auto;"><div>Hi Nadav,<div><br></div><div>There was a missing check which triggered a bug when we had registers bigger than 128 bits. It's fixed and the bug marked as fixed.</div><div><br></div><div>Thanks,</div><div><br></div><div>
Filipe<br><br>On Saturday, May 10, 2014, Nadav Rotem <<a href="mailto:nrotem@apple.com">nrotem@apple.com</a>> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">
Filipe,<br>
<br>
It looks like this commit caused: "Bug 19694 - Mesa llvmpipe lp_test_conv regression."<br>
<br>
Do you mind taking a look?<br>
<br>
Thanks,<br>
Nadav<br>
<br>
On May 7, 2014, at 5:25 PM, Filipe Cabecinhas <<a>me@filcab.net</a>> wrote:<br>
<br>
> Author: filcab<br>
> Date: Wed May 7 19:25:16 2014<br>
> New Revision: 208271<br>
><br>
> URL: <a href="http://llvm.org/viewvc/llvm-project?rev=208271&view=rev" target="_blank">http://llvm.org/viewvc/llvm-project?rev=208271&view=rev</a><br>
> Log:<br>
> Lower certain build_vectors to insertps instructions<br>
><br>
> Summary:<br>
> Vectors built with zeros and elements in the same order as another<br>
> (source) vector are optimized to be built using a single insertps<br>
> instruction.<br>
> Also optimize when we move one element in a vector to a different place<br>
> in that vector while zeroing out some of the other elements.<br>
><br>
> Further optimizations are possible, described in TODO comments.<br>
> I will be implementing at least some of them in the near future.<br>
><br>
> Added some tests for different cases where this optimization triggers.<br>
><br>
> Reviewers: nadav, delena, craig.topper<br>
><br>
> Subscribers: llvm-commits<br>
><br>
> Differential Revision: <a href="http://reviews.llvm.org/D3521" target="_blank">http://reviews.llvm.org/D3521</a><br>
><br>
> Modified:<br>
> llvm/trunk/lib/Target/X86/X86ISelLowering.cpp<br>
> llvm/trunk/test/CodeGen/X86/sse41.ll<br>
><br>
> Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp<br>
> URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=208271&r1=208270&r2=208271&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=208271&r1=208270&r2=208271&view=diff</a><br>
> ==============================================================================<br>
> --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)<br>
> +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Wed May 7 19:25:16 2014<br>
> @@ -5437,6 +5437,74 @@ static SDValue LowerBuildVectorv8i16(SDV<br>
> return V;<br>
> }<br>
><br>
> +/// LowerBuildVectorv4x32 - Custom lower build_vector of v4i32 or v4f32.<br>
> +static SDValue LowerBuildVectorv4x32(SDValue Op, unsigned NumElems,<br>
> + unsigned NonZeros, unsigned NumNonZero,<br>
> + unsigned NumZero, SelectionDAG &DAG,<br>
> + const X86Subtarget *Subtarget,<br>
> + const TargetLowering &TLI) {<br>
> + // We know there's at least one non-zero element<br>
> + unsigned FirstNonZeroIdx = 0;<br>
> + SDValue FirstNonZero = Op->getOperand(FirstNonZeroIdx);<br>
> + while (FirstNonZero.getOpcode() == ISD::UNDEF ||<br>
> + X86::isZeroNode(FirstNonZero)) {<br>
> + ++FirstNonZeroIdx;<br>
> + FirstNonZero = Op->getOperand(FirstNonZeroIdx);<br>
> + }<br>
> +<br>
> + if (FirstNonZero.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||<br>
> + !isa<ConstantSDNode>(FirstNonZero.getOperand(1)))<br>
> + return SDValue();<br>
> +<br>
> + SDValue V = FirstNonZero.getOperand(0);<br>
> + unsigned FirstNonZeroDst = cast<ConstantSDNode>(FirstNonZero.getOperand(1))->getZExtValue();<br>
> + unsigned CorrectIdx = FirstNonZeroDst == FirstNonZeroIdx;<br>
> + unsigned IncorrectIdx = CorrectIdx ? -1U : FirstNonZeroIdx;<br>
> + unsigned IncorrectDst = CorrectIdx ? -1U : FirstNonZeroDst;<br>
> +<br>
> + for (unsigned Idx = FirstNonZeroIdx + 1; Idx < NumElems; ++Idx) {<br>
> + SDValue Elem = Op.getOperand(Idx);<br>
> + if (Elem.getOpcode() == ISD::UNDEF || X86::isZeroNode(Elem))<br>
> + continue;<br>
> +<br>
> + // TODO: What else can be here? Deal with it.<br>
> + if (Elem.getOpcode() != ISD::EXTRACT_VECTOR_ELT)<br>
> + return SDValue();<br>
> +<br>
> + // TODO: Some optimizations are still possible here<br>
> + // ex: Getting one element from a vector, and the rest from</blockquote></div>
</div></blockquote></body></html>