<html><head><meta http-equiv="Content-Type" content="text/html charset=windows-1252"></head><body style="word-wrap: break-word; -webkit-nbsp-mode: space; -webkit-line-break: after-white-space;">Thanks!<div><br><div apple-content-edited="true">
<div style="color: rgb(0, 0, 0); font-family: Helvetica; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; orphans: 2; text-align: -webkit-auto; text-indent: 0px; text-transform: none; white-space: normal; widows: 2; word-spacing: 0px; -webkit-text-size-adjust: auto; -webkit-text-stroke-width: 0px; word-wrap: break-word; -webkit-nbsp-mode: space; -webkit-line-break: after-white-space; ">-Quentin</div>
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<br><div style=""><div>On May 8, 2014, at 3:51 PM, Justin Bogner <<a href="mailto:mail@justinbogner.com">mail@justinbogner.com</a>> wrote:</div><br class="Apple-interchange-newline"><blockquote type="cite"><div style="font-size: 12px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; orphans: auto; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; widows: auto; word-spacing: 0px; -webkit-text-stroke-width: 0px;">Quentin Colombet <<a href="mailto:qcolombet@apple.com">qcolombet@apple.com</a>> writes:<br><blockquote type="cite">Hi Justin,<br><br>I think you have relaxed the test too much.<br><br>On May 8, 2014, at 11:53 AM, Justin Bogner <<a href="mailto:mail@justinbogner.com">mail@justinbogner.com</a>> wrote:<br><br><blockquote type="cite">Author: bogner<br>Date: Thu May 8 13:53:56 2014<br>New Revision: 208351<br><br>URL: <a href="http://llvm.org/viewvc/llvm-project?rev=208351&view=rev">http://llvm.org/viewvc/llvm-project?rev=208351&view=rev</a>> Log:<br>Make a CodeGen test more robust against vector register selection<br><br>Modified:<br> llvm/trunk/test/CodeGen/ARM/func-argpassing-endian.ll<br><br>Modified: llvm/trunk/test/CodeGen/ARM/func-argpassing-endian.ll<br>URL:<br><a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/func-argpassing-endian.ll?rev=208351&r1=208350&r2=208351&view=diff">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/func-argpassing-endian.ll?rev=208351&r1=208350&r2=208351&view=diff</a>> ==============================================================================<br>--- llvm/trunk/test/CodeGen/ARM/func-argpassing-endian.ll (original)<br>+++ llvm/trunk/test/CodeGen/ARM/func-argpassing-endian.ll Thu May 8<br>13:53:56 2014<br>@@ -22,11 +22,11 @@ define void @arg_double( double %val ) {<br><br>define void @arg_v4i32(<4 x i32> %vec ) {<br>; CHECK-LABEL: arg_v4i32:<br>-; CHECK-LE: vmov d17, r2, r3<br>-; CHECK-LE: vmov d16, r0, r1<br>-; CHECK-BE: vmov d17, r3, r2<br>-; CHECK-BE: vmov d16, r1, r0<br>-; CHECK: vst1.32 {d16[0]}, [r0:32]<br>+; CHECK-LE: vmov {{d[0-9]+}}, r2, r3<br>+; CHECK-LE: vmov {{d[0-9]+}}, r0, r1<br>+; CHECK-BE: vmov {{d[0-9]+}}, r3, r2<br>+; CHECK-BE: vmov {{d[0-9]+}}, r1, r0<br>+; CHECK: vst1.32 {{{d[0-9]+}}[0]}, [r0:32]<br></blockquote>We do not actually check now that the store is fed with the value we<br>just created.<br></blockquote><br>Good point. I've tightened this up in r208368.<br><br><blockquote type="cite"><blockquote type="cite"> %tmp = extractelement <4 x i32> %vec, i32 0<br> store i32 %tmp, i32* @var32<br> ret void<br>@@ -51,26 +51,26 @@ define i64 @return_longint() {<br><br>define double @return_double() {<br>; CHECK-LABEL: return_double:<br>-; CHECK-LE: vmov r0, r1, d16<br>-; CHECK-BE: vmov r1, r0, d16<br>+; CHECK-LE: vmov r0, r1, {{d[0-9]+}}<br>+; CHECK-BE: vmov r1, r0, {{d[0-9]+}}<br></blockquote>Isn't this register defined by the ABI? (I’m asking, I do not know.)<br></blockquote><br>Nope, these are regular callee saved registers. Thanks for checking.<br><br><blockquote type="cite"><blockquote type="cite"> ret double 1.0<br>}<br><br>define <4 x i32> @return_v4i32() {<br>; CHECK-LABEL: return_v4i32:<br>-; CHECK-LE: vmov r0, r1, d16<br>-; CHECK-LE: vmov r2, r3, d17<br>-; CHECK-BE: vmov r1, r0, d16<br>-; CHECK-BE: vmov r3, r2, d17<br>+; CHECK-LE: vmov r0, r1, {{d[0-9]+}}<br>+; CHECK-LE: vmov r2, r3, {{d[0-9]+}}<br>+; CHECK-BE: vmov r1, r0, {{d[0-9]+}}<br>+; CHECK-BE: vmov r3, r2, {{d[0-9]+}}<br></blockquote>ABI registers?<br><blockquote type="cite"> ret < 4 x i32> < i32 42, i32 43, i32 44, i32 45 ><br>}<br><br>define <2 x double> @return_v2f64() {<br>; CHECK-LABEL: return_v2f64:<br>-; CHECK-LE: vmov r0, r1, d16<br>-; CHECK-LE: vmov r2, r3, d17<br>-; CHECK-BE: vmov r1, r0, d16<br>-; CHECK-BE: vmov r3, r2, d17<br>+; CHECK-LE: vmov r0, r1, {{d[0-9]+}}<br>+; CHECK-LE: vmov r2, r3, {{d[0-9]+}}<br>+; CHECK-BE: vmov r1, r0, {{d[0-9]+}}<br>+; CHECK-BE: vmov r3, r2, {{d[0-9]+}}<br></blockquote>Ditto?<br><blockquote type="cite"> ret <2 x double> < double 3.14, double 6.28 ><br>}<br><br>@@ -86,8 +86,8 @@ define void @caller_arg_longint() {<br><br>define void @caller_arg_double() {<br>; CHECK-LABEL: caller_arg_double:<br>-; CHECK-LE: vmov r0, r1, d16<br>-; CHECK-BE: vmov r1, r0, d16<br>+; CHECK-LE: vmov r0, r1, {{d[0-9]+}}<br>+; CHECK-BE: vmov r1, r0, {{d[0-9]+}}<br></blockquote>Ditto?<br><blockquote type="cite"> call void @arg_double( double 1.0 )<br> ret void<br>}<br>@@ -104,8 +104,8 @@ define void @caller_return_longint() {<br><br>define void @caller_return_double() {<br>; CHECK-LABEL: caller_return_double:<br>-; CHECK-LE: vmov d17, r0, r1<br>-; CHECK-BE: vmov d17, r1, r0<br>+; CHECK-LE: vmov {{d[0-9]+}}, r0, r1<br>+; CHECK-BE: vmov {{d[0-9]+}}, r1, r0<br></blockquote>Ditto?<br><blockquote type="cite"> %val = call double @return_double( )<br> %tmp = fadd double %val, 3.14<br> store double %tmp, double* @vardouble<br>@@ -120,4 +120,3 @@ define void @caller_return_v2f64() {<br> store double %tmp, double* @vardouble<br> ret void<br>}<br>-<br><br><br>_______________________________________________<br>llvm-commits mailing list<br><a href="mailto:llvm-commits@cs.uiuc.edu">llvm-commits@cs.uiuc.edu</a><br>http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits</blockquote></blockquote></div></blockquote></div><br></div></body></html>