<div dir="ltr">Yes, this is an intentional change.<div>According to Intel optimization reference manual FP addition on Silvermont happens only on port 1 (FPC_RSV1).</div></div><div class="gmail_extra"><br><br><div class="gmail_quote">
2014-04-29 20:58 GMT+04:00 Hal Finkel <span dir="ltr"><<a href="mailto:hfinkel@anl.gov" target="_blank">hfinkel@anl.gov</a>></span>:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">
<div class="HOEnZb"><div class="h5">----- Original Message -----<br>
> From: "Alexey Volkov" <<a href="mailto:avolkov.intel@gmail.com">avolkov.intel@gmail.com</a>><br>
> To: <a href="mailto:llvm-commits@cs.uiuc.edu">llvm-commits@cs.uiuc.edu</a><br>
> Sent: Wednesday, April 23, 2014 3:57:10 AM<br>
> Subject: [llvm] r206957 - [X86] Silvermont new scheduler model<br>
><br>
> Author: volkalex<br>
> Date: Wed Apr 23 03:57:09 2014<br>
> New Revision: 206957<br>
><br>
> URL: <a href="http://llvm.org/viewvc/llvm-project?rev=206957&view=rev" target="_blank">http://llvm.org/viewvc/llvm-project?rev=206957&view=rev</a><br>
> Log:<br>
> [X86] Silvermont new scheduler model<br>
> This model is not final and work is still in progress.<br>
> However there are substantial improvements on integer tests mainly<br>
> because of better RAL with new scheduler.<br>
><br>
> Differential Revision: <a href="http://reviews.llvm.org/D3451" target="_blank">http://reviews.llvm.org/D3451</a><br>
><br>
> Modified:<br>
>     llvm/trunk/lib/Target/X86/X86ScheduleSLM.td<br>
><br>
> Modified: llvm/trunk/lib/Target/X86/X86ScheduleSLM.td<br>
> URL:<br>
> <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ScheduleSLM.td?rev=206957&r1=206956&r2=206957&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ScheduleSLM.td?rev=206957&r1=206956&r2=206957&view=diff</a><br>

> ==============================================================================<br>
> --- llvm/trunk/lib/Target/X86/X86ScheduleSLM.td (original)<br>
> +++ llvm/trunk/lib/Target/X86/X86ScheduleSLM.td Wed Apr 23 03:57:09<br>
> 2014<br>
> @@ -1,4 +1,4 @@<br>
<br>
</div></div>[snip]<br>
<div class=""><br>
> +// Scalar and vector floating point.<br>
> +defm : SMWriteResPair<WriteFAdd,   FPC_RSV1, 3>;<br>
<br>
</div>[snip]<br>
<div class=""><br>
> -<br>
> -  // SSE binary operations<br>
> -  // arithmetic fp scalar<br>
> -  InstrItinData<IIC_SSE_ALU_F32S_RR, [InstrStage<3, [FPC_RSV0,<br>
> FPC_RSV1]>] >,<br>
<br>
</div>[snip]<br>
<br>
Is this an intentional model change? It looks like previously floating-point addition could happen in both FPC_RSV0 or FPC_RSV1, but now it happens only in FPC_RSV1?<br>
<br>
 -Hal<br>
<div class="HOEnZb"><div class="h5"><br>
><br>
><br>
> _______________________________________________<br>
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> <a href="mailto:llvm-commits@cs.uiuc.edu">llvm-commits@cs.uiuc.edu</a><br>
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><br>
<br>
</div></div><span class="HOEnZb"><font color="#888888">--<br>
Hal Finkel<br>
Assistant Computational Scientist<br>
Leadership Computing Facility<br>
Argonne National Laboratory<br>
</font></span></blockquote></div><br><br clear="all"><div><br></div>-- <br><div dir="ltr">Alexey Volkov<div>Intel Corporation</div></div>
</div>