<div dir="ltr">Bot breakage due to this commit should be fixed by r<span style="font-family:arial,sans-serif;font-size:13px">206885.</span><div><br></div><div><font face="arial, sans-serif">- Lang.</font></div></div><div class="gmail_extra">
<br><br><div class="gmail_quote">On Tue, Apr 22, 2014 at 8:41 PM, Lang Hames <span dir="ltr"><<a href="mailto:lhames@gmail.com" target="_blank">lhames@gmail.com</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">
Author: lhames<br>
Date: Tue Apr 22 05:41:56 2014<br>
New Revision: 206879<br>
<br>
URL: <a href="http://llvm.org/viewvc/llvm-project?rev=206879&view=rev" target="_blank">http://llvm.org/viewvc/llvm-project?rev=206879&view=rev</a><br>
Log:<br>
[X86] Use tablegen instead of DAG combines to match BZHI instructions, as<br>
suggested by Ben Kramer in review of r206738.<br>
<br>
Thanks again Ben!<br>
<br>
<br>
Modified:<br>
llvm/trunk/lib/Target/X86/X86ISelLowering.cpp<br>
llvm/trunk/lib/Target/X86/X86ISelLowering.h<br>
llvm/trunk/lib/Target/X86/X86InstrInfo.td<br>
<br>
Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=206879&r1=206878&r2=206879&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=206879&r1=206878&r2=206879&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)<br>
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Tue Apr 22 05:41:56 2014<br>
@@ -14367,7 +14367,6 @@ const char *X86TargetLowering::getTarget<br>
case X86ISD::OR: return "X86ISD::OR";<br>
case X86ISD::XOR: return "X86ISD::XOR";<br>
case X86ISD::AND: return "X86ISD::AND";<br>
- case X86ISD::BZHI: return "X86ISD::BZHI";<br>
case X86ISD::BEXTR: return "X86ISD::BEXTR";<br>
case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM";<br>
case X86ISD::PTEST: return "X86ISD::PTEST";<br>
@@ -18453,40 +18452,13 @@ static SDValue PerformAndCombine(SDNode<br>
if (R.getNode())<br>
return R;<br>
<br>
- // Create BEXTR and BZHI instructions<br>
- // BZHI is X & ((1 << Y) - 1)<br>
+ // Create BEXTR instructions<br>
// BEXTR is ((X >> imm) & (2**size-1))<br>
if (VT == MVT::i32 || VT == MVT::i64) {<br>
SDValue N0 = N->getOperand(0);<br>
SDValue N1 = N->getOperand(1);<br>
SDLoc DL(N);<br>
<br>
- if (Subtarget->hasBMI2()) {<br>
- // Check for (and (add (shl 1, Y), -1), X)<br>
- if (N0.getOpcode() == ISD::ADD && isAllOnes(N0.getOperand(1))) {<br>
- SDValue N00 = N0.getOperand(0);<br>
- if (N00.getOpcode() == ISD::SHL) {<br>
- SDValue N001 = N00.getOperand(1);<br>
- assert(N001.getValueType() == MVT::i8 && "unexpected type");<br>
- ConstantSDNode *C = dyn_cast<ConstantSDNode>(N00.getOperand(0));<br>
- if (C && C->getZExtValue() == 1)<br>
- return DAG.getNode(X86ISD::BZHI, DL, VT, N1, N001);<br>
- }<br>
- }<br>
-<br>
- // Check for (and X, (add (shl 1, Y), -1))<br>
- if (N1.getOpcode() == ISD::ADD && isAllOnes(N1.getOperand(1))) {<br>
- SDValue N10 = N1.getOperand(0);<br>
- if (N10.getOpcode() == ISD::SHL) {<br>
- SDValue N101 = N10.getOperand(1);<br>
- assert(N101.getValueType() == MVT::i8 && "unexpected type");<br>
- ConstantSDNode *C = dyn_cast<ConstantSDNode>(N10.getOperand(0));<br>
- if (C && C->getZExtValue() == 1)<br>
- return DAG.getNode(X86ISD::BZHI, DL, VT, N0, N101);<br>
- }<br>
- }<br>
- }<br>
-<br>
// Check for BEXTR.<br>
if ((Subtarget->hasBMI() || Subtarget->hasTBM()) &&<br>
(N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::SRL)) {<br>
@@ -18504,22 +18476,6 @@ static SDValue PerformAndCombine(SDNode<br>
}<br>
} // BEXTR<br>
<br>
- // Check for BZHI with contiguous mask: (and X, 0x0..0f..f)<br>
- // This should be checked after BEXTR - when X is a shift, a BEXTR is<br>
- // preferrable.<br>
- if (VT == MVT::i64 && Subtarget->hasBMI2()) {<br>
- if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N1)) {<br>
- uint64_t Mask = C->getZExtValue();<br>
- if (isMask_64(Mask)) {<br>
- unsigned LZ = CountTrailingOnes_64(Mask);<br>
- // Only use BZHI for immediates that are too large for an AND:<br>
- if (LZ > 32)<br>
- return DAG.getNode(X86ISD::BZHI, DL, VT, N0,<br>
- DAG.getConstant(LZ, MVT::i8));<br>
- }<br>
- }<br>
- }<br>
-<br>
return SDValue();<br>
}<br>
<br>
<br>
Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.h<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.h?rev=206879&r1=206878&r2=206879&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.h?rev=206879&r1=206878&r2=206879&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/X86/X86ISelLowering.h (original)<br>
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.h Tue Apr 22 05:41:56 2014<br>
@@ -291,7 +291,6 @@ namespace llvm {<br>
ADD, SUB, ADC, SBB, SMUL,<br>
INC, DEC, OR, XOR, AND,<br>
<br>
- BZHI, // BZHI - Zero high bits<br>
BEXTR, // BEXTR - Bit field extract<br>
<br>
UMUL, // LOW, HI, FLAGS = umul LHS, RHS<br>
<br>
Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.td<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.td?rev=206879&r1=206878&r2=206879&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.td?rev=206879&r1=206878&r2=206879&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/X86/X86InstrInfo.td (original)<br>
+++ llvm/trunk/lib/Target/X86/X86InstrInfo.td Tue Apr 22 05:41:56 2014<br>
@@ -2104,18 +2104,36 @@ let Predicates = [HasBMI2], Defs = [EFLA<br>
int_x86_bmi_bzhi_64, loadi64>, VEX_W;<br>
}<br>
<br>
-def : Pat<(X86bzhi GR32:$src1, GR8:$src2),<br>
- (BZHI32rr GR32:$src1,<br>
- (INSERT_SUBREG (i32 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>;<br>
-def : Pat<(X86bzhi (loadi32 addr:$src1), GR8:$src2),<br>
- (BZHI32rm addr:$src1,<br>
- (INSERT_SUBREG (i32 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>;<br>
-def : Pat<(X86bzhi GR64:$src1, GR8:$src2),<br>
- (BZHI64rr GR64:$src1,<br>
- (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>;<br>
-def : Pat<(X86bzhi (loadi64 addr:$src1), GR8:$src2),<br>
- (BZHI64rm addr:$src1,<br>
- (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>;<br>
+<br>
+def CountTrailingOnes : SDNodeXForm<imm, [{<br>
+ // Count the trailing ones in the immediate.<br>
+ return getI8Imm(CountTrailingOnes_64(N->getZExtValue()));<br>
+}]>;<br>
+<br>
+def BZHIMask : ImmLeaf<i64, [{<br>
+ return isMask_64(Imm) && (CountTrailingOnes_64(Imm) > 32);<br>
+}]>;<br>
+<br>
+def : Pat<(and GR64:$src, BZHIMask:$mask),<br>
+ (BZHI64rr GR64:$src,<br>
+ (INSERT_SUBREG (i64 (IMPLICIT_DEF)),<br>
+ (MOV8ri (CountTrailingOnes imm:$mask)), sub_8bit))>;<br>
+<br>
+def : Pat<(and GR32:$src, (add (shl 1, GR8:$lz), -1)),<br>
+ (BZHI32rr GR32:$src,<br>
+ (INSERT_SUBREG (i32 (IMPLICIT_DEF)), GR8:$lz, sub_8bit))>;<br>
+<br>
+def : Pat<(and (loadi32 addr:$src), (add (shl 1, GR8:$lz), -1)),<br>
+ (BZHI32rm addr:$src,<br>
+ (INSERT_SUBREG (i32 (IMPLICIT_DEF)), GR8:$lz, sub_8bit))>;<br>
+<br>
+def : Pat<(and GR64:$src, (add (shl 1, GR8:$lz), -1)),<br>
+ (BZHI64rr GR64:$src,<br>
+ (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR8:$lz, sub_8bit))>;<br>
+<br>
+def : Pat<(and (loadi64 addr:$src), (add (shl 1, GR8:$lz), -1)),<br>
+ (BZHI64rm addr:$src,<br>
+ (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR8:$lz, sub_8bit))>;<br>
<br>
let Predicates = [HasBMI] in {<br>
def : Pat<(X86bextr GR32:$src1, GR32:$src2),<br>
<br>
<br>
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</blockquote></div><br></div>