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<pre wrap="">+ // The low 7 bits encoding value is the register index, for both VGPRs and
+ // SGPRs.
+ unsigned RegIdx = MRI.getEncodingValue(reg) & 0x7;</pre>
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That doesn't looks valid on first glance. For the low 7 bis you
want a mask of 0x1F here, not 0x7.<br>
<br>
Christian.<br>
<br>
Am 14.04.2014 08:51, schrieb Matt Arsenault:<br>
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cite="mid:differential-rev-PHID-DREV-4plewjeezmrjtxvuagle-req@reviews.llvm.org"
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<pre wrap="">Try to figure out the class and number of subregisters.
<a class="moz-txt-link-freetext" href="http://reviews.llvm.org/D3367">http://reviews.llvm.org/D3367</a>
Files:
lib/Target/R600/InstPrinter/AMDGPUInstPrinter.cpp
lib/Target/R600/InstPrinter/AMDGPUInstPrinter.h
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