<div dir="ltr">This broke the build with MSVC 2012:<div><a href="http://bb.pgr.jp/builders/ninja-clang-i686-msc17-R/builds/7999/steps/build_clang_tools/logs/stdio">http://bb.pgr.jp/builders/ninja-clang-i686-msc17-R/builds/7999/steps/build_clang_tools/logs/stdio</a><br>
</div><div><br></div><div>I don't see a quick fix, so I'm reverting.</div><div><br></div><div>The problem is that the AlignmentLoc member makes MemoryOp's default constructor non-trivial, and MSVC doesn't like union members that have default ctors.</div>
</div><div class="gmail_extra"><br><br><div class="gmail_quote">On Wed, Apr 9, 2014 at 2:32 PM, Kevin Enderby <span dir="ltr"><<a href="mailto:enderby@apple.com" target="_blank">enderby@apple.com</a>></span> wrote:<br>
<blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">Author: enderby<br>
Date: Wed Apr 9 16:32:59 2014<br>
New Revision: 205930<br>
<br>
URL: <a href="http://llvm.org/viewvc/llvm-project?rev=205930&view=rev" target="_blank">http://llvm.org/viewvc/llvm-project?rev=205930&view=rev</a><br>
Log:<br>
For the ARM integrated assembler add checking of the<br>
alignments on vld/vst instructions. And report errors for<br>
alignments that are not supported.<br>
<br>
While this is a large diff and an big test case, the changes<br>
are very straight forward. But pretty much had to touch<br>
all vld/vst instructions changing the addrmode to one of the<br>
new ones that where added will do the proper checking for<br>
the specific instruction.<br>
<br>
rdar://11312406<br>
<br>
Added:<br>
llvm/trunk/test/MC/ARM/neon-vld-vst-align.s<br>
Modified:<br>
llvm/trunk/lib/Target/ARM/ARMInstrInfo.td<br>
llvm/trunk/lib/Target/ARM/ARMInstrNEON.td<br>
llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp<br>
<br>
Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=205930&r1=205929&r2=205930&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=205930&r1=205929&r2=205930&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original)<br>
+++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Wed Apr 9 16:32:59 2014<br>
@@ -991,6 +991,81 @@ def addrmode6oneL32 : Operand<i32>,<br>
let EncoderMethod = "getAddrMode6OneLane32AddressOpValue";<br>
}<br>
<br>
+// Base class for addrmode6 with specific alignment restrictions.<br>
+class AddrMode6Align : Operand<i32>,<br>
+ ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{<br>
+ let PrintMethod = "printAddrMode6Operand";<br>
+ let MIOperandInfo = (ops GPR:$addr, i32imm:$align);<br>
+ let EncoderMethod = "getAddrMode6AddressOpValue";<br>
+ let DecoderMethod = "DecodeAddrMode6Operand";<br>
+}<br>
+<br>
+// Special version of addrmode6 to handle no allowed alignment encoding for<br>
+// VLD/VST instructions and checking the alignment is not specified.<br>
+def AddrMode6AlignNoneAsmOperand : AsmOperandClass {<br>
+ let Name = "AlignedMemoryNone";<br>
+ let DiagnosticType = "AlignedMemoryRequiresNone";<br>
+}<br>
+def addrmode6alignNone : AddrMode6Align {<br>
+ // The alignment specifier can only be omitted.<br>
+ let ParserMatchClass = AddrMode6AlignNoneAsmOperand;<br>
+}<br>
+<br>
+// Special version of addrmode6 to handle 16-bit alignment encoding for<br>
+// VLD/VST instructions and checking the alignment value.<br>
+def AddrMode6Align16AsmOperand : AsmOperandClass {<br>
+ let Name = "AlignedMemory16";<br>
+ let DiagnosticType = "AlignedMemoryRequires16";<br>
+}<br>
+def addrmode6align16 : AddrMode6Align {<br>
+ // The alignment specifier can only be 16 or omitted.<br>
+ let ParserMatchClass = AddrMode6Align16AsmOperand;<br>
+}<br>
+<br>
+// Special version of addrmode6 to handle 32-bit alignment encoding for<br>
+// VLD/VST instructions and checking the alignment value.<br>
+def AddrMode6Align32AsmOperand : AsmOperandClass {<br>
+ let Name = "AlignedMemory32";<br>
+ let DiagnosticType = "AlignedMemoryRequires32";<br>
+}<br>
+def addrmode6align32 : AddrMode6Align {<br>
+ // The alignment specifier can only be 32 or omitted.<br>
+ let ParserMatchClass = AddrMode6Align32AsmOperand;<br>
+}<br>
+<br>
+// Special version of addrmode6 to handle 64-bit alignment encoding for<br>
+// VLD/VST instructions and checking the alignment value.<br>
+def AddrMode6Align64AsmOperand : AsmOperandClass {<br>
+ let Name = "AlignedMemory64";<br>
+ let DiagnosticType = "AlignedMemoryRequires64";<br>
+}<br>
+def addrmode6align64 : AddrMode6Align {<br>
+ // The alignment specifier can only be 64 or omitted.<br>
+ let ParserMatchClass = AddrMode6Align64AsmOperand;<br>
+}<br>
+<br>
+// Special version of addrmode6 to handle 64-bit or 128-bit alignment encoding<br>
+// for VLD/VST instructions and checking the alignment value.<br>
+def AddrMode6Align64or128AsmOperand : AsmOperandClass {<br>
+ let Name = "AlignedMemory64or128";<br>
+ let DiagnosticType = "AlignedMemoryRequires64or128";<br>
+}<br>
+def addrmode6align64or128 : AddrMode6Align {<br>
+ // The alignment specifier can only be 64, 128 or omitted.<br>
+ let ParserMatchClass = AddrMode6Align64or128AsmOperand;<br>
+}<br>
+<br>
+// Special version of addrmode6 to handle 64-bit, 128-bit or 256-bit alignment<br>
+// encoding for VLD/VST instructions and checking the alignment value.<br>
+def AddrMode6Align64or128or256AsmOperand : AsmOperandClass {<br>
+ let Name = "AlignedMemory64or128or256";<br>
+ let DiagnosticType = "AlignedMemoryRequires64or128or256";<br>
+}<br>
+def addrmode6align64or128or256 : AddrMode6Align {<br>
+ // The alignment specifier can only be 64, 128, 256 or omitted.<br>
+ let ParserMatchClass = AddrMode6Align64or128or256AsmOperand;<br>
+}<br>
+<br>
// Special version of addrmode6 to handle alignment encoding for VLD-dup<br>
// instructions, specifically VLD4-dup.<br>
def addrmode6dup : Operand<i32>,<br>
@@ -1003,6 +1078,69 @@ def addrmode6dup : Operand<i32>,<br>
let ParserMatchClass = AddrMode6AsmOperand;<br>
}<br>
<br>
+// Base class for addrmode6dup with specific alignment restrictions.<br>
+class AddrMode6DupAlign : Operand<i32>,<br>
+ ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{<br>
+ let PrintMethod = "printAddrMode6Operand";<br>
+ let MIOperandInfo = (ops GPR:$addr, i32imm);<br>
+ let EncoderMethod = "getAddrMode6DupAddressOpValue";<br>
+}<br>
+<br>
+// Special version of addrmode6 to handle no allowed alignment encoding for<br>
+// VLD-dup instruction and checking the alignment is not specified.<br>
+def AddrMode6dupAlignNoneAsmOperand : AsmOperandClass {<br>
+ let Name = "DupAlignedMemoryNone";<br>
+ let DiagnosticType = "DupAlignedMemoryRequiresNone";<br>
+}<br>
+def addrmode6dupalignNone : AddrMode6DupAlign {<br>
+ // The alignment specifier can only be omitted.<br>
+ let ParserMatchClass = AddrMode6dupAlignNoneAsmOperand;<br>
+}<br>
+<br>
+// Special version of addrmode6 to handle 16-bit alignment encoding for VLD-dup<br>
+// instruction and checking the alignment value.<br>
+def AddrMode6dupAlign16AsmOperand : AsmOperandClass {<br>
+ let Name = "DupAlignedMemory16";<br>
+ let DiagnosticType = "DupAlignedMemoryRequires16";<br>
+}<br>
+def addrmode6dupalign16 : AddrMode6DupAlign {<br>
+ // The alignment specifier can only be 16 or omitted.<br>
+ let ParserMatchClass = AddrMode6dupAlign16AsmOperand;<br>
+}<br>
+<br>
+// Special version of addrmode6 to handle 32-bit alignment encoding for VLD-dup<br>
+// instruction and checking the alignment value.<br>
+def AddrMode6dupAlign32AsmOperand : AsmOperandClass {<br>
+ let Name = "DupAlignedMemory32";<br>
+ let DiagnosticType = "DupAlignedMemoryRequires32";<br>
+}<br>
+def addrmode6dupalign32 : AddrMode6DupAlign {<br>
+ // The alignment specifier can only be 32 or omitted.<br>
+ let ParserMatchClass = AddrMode6dupAlign32AsmOperand;<br>
+}<br>
+<br>
+// Special version of addrmode6 to handle 64-bit alignment encoding for VLD<br>
+// instructions and checking the alignment value.<br>
+def AddrMode6dupAlign64AsmOperand : AsmOperandClass {<br>
+ let Name = "DupAlignedMemory64";<br>
+ let DiagnosticType = "DupAlignedMemoryRequires64";<br>
+}<br>
+def addrmode6dupalign64 : AddrMode6DupAlign {<br>
+ // The alignment specifier can only be 64 or omitted.<br>
+ let ParserMatchClass = AddrMode6dupAlign64AsmOperand;<br>
+}<br>
+<br>
+// Special version of addrmode6 to handle 64-bit or 128-bit alignment encoding<br>
+// for VLD instructions and checking the alignment value.<br>
+def AddrMode6dupAlign64or128AsmOperand : AsmOperandClass {<br>
+ let Name = "DupAlignedMemory64or128";<br>
+ let DiagnosticType = "DupAlignedMemoryRequires64or128";<br>
+}<br>
+def addrmode6dupalign64or128 : AddrMode6DupAlign {<br>
+ // The alignment specifier can only be 64, 128 or omitted.<br>
+ let ParserMatchClass = AddrMode6dupAlign64or128AsmOperand;<br>
+}<br>
+<br>
// addrmodepc := pc + reg<br>
//<br>
def addrmodepc : Operand<i32>,<br>
<br>
Modified: llvm/trunk/lib/Target/ARM/ARMInstrNEON.td<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrNEON.td?rev=205930&r1=205929&r2=205930&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrNEON.td?rev=205930&r1=205929&r2=205930&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/ARM/ARMInstrNEON.td (original)<br>
+++ llvm/trunk/lib/Target/ARM/ARMInstrNEON.td Wed Apr 9 16:32:59 2014<br>
@@ -617,37 +617,37 @@ class VLDQQQQWBPseudo<InstrItinClass iti<br>
let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {<br>
<br>
// VLD1 : Vector Load (multiple single elements)<br>
-class VLD1D<bits<4> op7_4, string Dt><br>
+class VLD1D<bits<4> op7_4, string Dt, Operand AddrMode><br>
: NLdSt<0,0b10,0b0111,op7_4, (outs VecListOneD:$Vd),<br>
- (ins addrmode6:$Rn), IIC_VLD1,<br>
+ (ins AddrMode:$Rn), IIC_VLD1,<br>
"vld1", Dt, "$Vd, $Rn", "", []> {<br>
let Rm = 0b1111;<br>
let Inst{4} = Rn{4};<br>
let DecoderMethod = "DecodeVLDST1Instruction";<br>
}<br>
-class VLD1Q<bits<4> op7_4, string Dt><br>
+class VLD1Q<bits<4> op7_4, string Dt, Operand AddrMode><br>
: NLdSt<0,0b10,0b1010,op7_4, (outs VecListDPair:$Vd),<br>
- (ins addrmode6:$Rn), IIC_VLD1x2,<br>
+ (ins AddrMode:$Rn), IIC_VLD1x2,<br>
"vld1", Dt, "$Vd, $Rn", "", []> {<br>
let Rm = 0b1111;<br>
let Inst{5-4} = Rn{5-4};<br>
let DecoderMethod = "DecodeVLDST1Instruction";<br>
}<br>
<br>
-def VLD1d8 : VLD1D<{0,0,0,?}, "8">;<br>
-def VLD1d16 : VLD1D<{0,1,0,?}, "16">;<br>
-def VLD1d32 : VLD1D<{1,0,0,?}, "32">;<br>
-def VLD1d64 : VLD1D<{1,1,0,?}, "64">;<br>
-<br>
-def VLD1q8 : VLD1Q<{0,0,?,?}, "8">;<br>
-def VLD1q16 : VLD1Q<{0,1,?,?}, "16">;<br>
-def VLD1q32 : VLD1Q<{1,0,?,?}, "32">;<br>
-def VLD1q64 : VLD1Q<{1,1,?,?}, "64">;<br>
+def VLD1d8 : VLD1D<{0,0,0,?}, "8", addrmode6align64>;<br>
+def VLD1d16 : VLD1D<{0,1,0,?}, "16", addrmode6align64>;<br>
+def VLD1d32 : VLD1D<{1,0,0,?}, "32", addrmode6align64>;<br>
+def VLD1d64 : VLD1D<{1,1,0,?}, "64", addrmode6align64>;<br>
+<br>
+def VLD1q8 : VLD1Q<{0,0,?,?}, "8", addrmode6align64or128>;<br>
+def VLD1q16 : VLD1Q<{0,1,?,?}, "16", addrmode6align64or128>;<br>
+def VLD1q32 : VLD1Q<{1,0,?,?}, "32", addrmode6align64or128>;<br>
+def VLD1q64 : VLD1Q<{1,1,?,?}, "64", addrmode6align64or128>;<br>
<br>
// ...with address register writeback:<br>
-multiclass VLD1DWB<bits<4> op7_4, string Dt> {<br>
+multiclass VLD1DWB<bits<4> op7_4, string Dt, Operand AddrMode> {<br>
def _fixed : NLdSt<0,0b10, 0b0111,op7_4, (outs VecListOneD:$Vd, GPR:$wb),<br>
- (ins addrmode6:$Rn), IIC_VLD1u,<br>
+ (ins AddrMode:$Rn), IIC_VLD1u,<br>
"vld1", Dt, "$Vd, $Rn!",<br>
"$Rn.addr = $wb", []> {<br>
let Rm = 0b1101; // NLdSt will assign to the right encoding bits.<br>
@@ -655,16 +655,16 @@ multiclass VLD1DWB<bits<4> op7_4, string<br>
let DecoderMethod = "DecodeVLDST1Instruction";<br>
}<br>
def _register : NLdSt<0,0b10,0b0111,op7_4, (outs VecListOneD:$Vd, GPR:$wb),<br>
- (ins addrmode6:$Rn, rGPR:$Rm), IIC_VLD1u,<br>
+ (ins AddrMode:$Rn, rGPR:$Rm), IIC_VLD1u,<br>
"vld1", Dt, "$Vd, $Rn, $Rm",<br>
"$Rn.addr = $wb", []> {<br>
let Inst{4} = Rn{4};<br>
let DecoderMethod = "DecodeVLDST1Instruction";<br>
}<br>
}<br>
-multiclass VLD1QWB<bits<4> op7_4, string Dt> {<br>
+multiclass VLD1QWB<bits<4> op7_4, string Dt, Operand AddrMode> {<br>
def _fixed : NLdSt<0,0b10,0b1010,op7_4, (outs VecListDPair:$Vd, GPR:$wb),<br>
- (ins addrmode6:$Rn), IIC_VLD1x2u,<br>
+ (ins AddrMode:$Rn), IIC_VLD1x2u,<br>
"vld1", Dt, "$Vd, $Rn!",<br>
"$Rn.addr = $wb", []> {<br>
let Rm = 0b1101; // NLdSt will assign to the right encoding bits.<br>
@@ -672,7 +672,7 @@ multiclass VLD1QWB<bits<4> op7_4, string<br>
let DecoderMethod = "DecodeVLDST1Instruction";<br>
}<br>
def _register : NLdSt<0,0b10,0b1010,op7_4, (outs VecListDPair:$Vd, GPR:$wb),<br>
- (ins addrmode6:$Rn, rGPR:$Rm), IIC_VLD1x2u,<br>
+ (ins AddrMode:$Rn, rGPR:$Rm), IIC_VLD1x2u,<br>
"vld1", Dt, "$Vd, $Rn, $Rm",<br>
"$Rn.addr = $wb", []> {<br>
let Inst{5-4} = Rn{5-4};<br>
@@ -680,27 +680,27 @@ multiclass VLD1QWB<bits<4> op7_4, string<br>
}<br>
}<br>
<br>
-defm VLD1d8wb : VLD1DWB<{0,0,0,?}, "8">;<br>
-defm VLD1d16wb : VLD1DWB<{0,1,0,?}, "16">;<br>
-defm VLD1d32wb : VLD1DWB<{1,0,0,?}, "32">;<br>
-defm VLD1d64wb : VLD1DWB<{1,1,0,?}, "64">;<br>
-defm VLD1q8wb : VLD1QWB<{0,0,?,?}, "8">;<br>
-defm VLD1q16wb : VLD1QWB<{0,1,?,?}, "16">;<br>
-defm VLD1q32wb : VLD1QWB<{1,0,?,?}, "32">;<br>
-defm VLD1q64wb : VLD1QWB<{1,1,?,?}, "64">;<br>
+defm VLD1d8wb : VLD1DWB<{0,0,0,?}, "8", addrmode6align64>;<br>
+defm VLD1d16wb : VLD1DWB<{0,1,0,?}, "16", addrmode6align64>;<br>
+defm VLD1d32wb : VLD1DWB<{1,0,0,?}, "32", addrmode6align64>;<br>
+defm VLD1d64wb : VLD1DWB<{1,1,0,?}, "64", addrmode6align64>;<br>
+defm VLD1q8wb : VLD1QWB<{0,0,?,?}, "8", addrmode6align64or128>;<br>
+defm VLD1q16wb : VLD1QWB<{0,1,?,?}, "16", addrmode6align64or128>;<br>
+defm VLD1q32wb : VLD1QWB<{1,0,?,?}, "32", addrmode6align64or128>;<br>
+defm VLD1q64wb : VLD1QWB<{1,1,?,?}, "64", addrmode6align64or128>;<br>
<br>
// ...with 3 registers<br>
-class VLD1D3<bits<4> op7_4, string Dt><br>
+class VLD1D3<bits<4> op7_4, string Dt, Operand AddrMode><br>
: NLdSt<0,0b10,0b0110,op7_4, (outs VecListThreeD:$Vd),<br>
- (ins addrmode6:$Rn), IIC_VLD1x3, "vld1", Dt,<br>
+ (ins AddrMode:$Rn), IIC_VLD1x3, "vld1", Dt,<br>
"$Vd, $Rn", "", []> {<br>
let Rm = 0b1111;<br>
let Inst{4} = Rn{4};<br>
let DecoderMethod = "DecodeVLDST1Instruction";<br>
}<br>
-multiclass VLD1D3WB<bits<4> op7_4, string Dt> {<br>
+multiclass VLD1D3WB<bits<4> op7_4, string Dt, Operand AddrMode> {<br>
def _fixed : NLdSt<0,0b10,0b0110, op7_4, (outs VecListThreeD:$Vd, GPR:$wb),<br>
- (ins addrmode6:$Rn), IIC_VLD1x2u,<br>
+ (ins AddrMode:$Rn), IIC_VLD1x2u,<br>
"vld1", Dt, "$Vd, $Rn!",<br>
"$Rn.addr = $wb", []> {<br>
let Rm = 0b1101; // NLdSt will assign to the right encoding bits.<br>
@@ -708,7 +708,7 @@ multiclass VLD1D3WB<bits<4> op7_4, strin<br>
let DecoderMethod = "DecodeVLDST1Instruction";<br>
}<br>
def _register : NLdSt<0,0b10,0b0110,op7_4, (outs VecListThreeD:$Vd, GPR:$wb),<br>
- (ins addrmode6:$Rn, rGPR:$Rm), IIC_VLD1x2u,<br>
+ (ins AddrMode:$Rn, rGPR:$Rm), IIC_VLD1x2u,<br>
"vld1", Dt, "$Vd, $Rn, $Rm",<br>
"$Rn.addr = $wb", []> {<br>
let Inst{4} = Rn{4};<br>
@@ -716,32 +716,32 @@ multiclass VLD1D3WB<bits<4> op7_4, strin<br>
}<br>
}<br>
<br>
-def VLD1d8T : VLD1D3<{0,0,0,?}, "8">;<br>
-def VLD1d16T : VLD1D3<{0,1,0,?}, "16">;<br>
-def VLD1d32T : VLD1D3<{1,0,0,?}, "32">;<br>
-def VLD1d64T : VLD1D3<{1,1,0,?}, "64">;<br>
-<br>
-defm VLD1d8Twb : VLD1D3WB<{0,0,0,?}, "8">;<br>
-defm VLD1d16Twb : VLD1D3WB<{0,1,0,?}, "16">;<br>
-defm VLD1d32Twb : VLD1D3WB<{1,0,0,?}, "32">;<br>
-defm VLD1d64Twb : VLD1D3WB<{1,1,0,?}, "64">;<br>
+def VLD1d8T : VLD1D3<{0,0,0,?}, "8", addrmode6align64>;<br>
+def VLD1d16T : VLD1D3<{0,1,0,?}, "16", addrmode6align64>;<br>
+def VLD1d32T : VLD1D3<{1,0,0,?}, "32", addrmode6align64>;<br>
+def VLD1d64T : VLD1D3<{1,1,0,?}, "64", addrmode6align64>;<br>
+<br>
+defm VLD1d8Twb : VLD1D3WB<{0,0,0,?}, "8", addrmode6align64>;<br>
+defm VLD1d16Twb : VLD1D3WB<{0,1,0,?}, "16", addrmode6align64>;<br>
+defm VLD1d32Twb : VLD1D3WB<{1,0,0,?}, "32", addrmode6align64>;<br>
+defm VLD1d64Twb : VLD1D3WB<{1,1,0,?}, "64", addrmode6align64>;<br>
<br>
def VLD1d64TPseudo : VLDQQPseudo<IIC_VLD1x3>;<br>
def VLD1d64TPseudoWB_fixed : VLDQQWBfixedPseudo<IIC_VLD1x3>;<br>
def VLD1d64TPseudoWB_register : VLDQQWBregisterPseudo<IIC_VLD1x3>;<br>
<br>
// ...with 4 registers<br>
-class VLD1D4<bits<4> op7_4, string Dt><br>
+class VLD1D4<bits<4> op7_4, string Dt, Operand AddrMode><br>
: NLdSt<0, 0b10, 0b0010, op7_4, (outs VecListFourD:$Vd),<br>
- (ins addrmode6:$Rn), IIC_VLD1x4, "vld1", Dt,<br>
+ (ins AddrMode:$Rn), IIC_VLD1x4, "vld1", Dt,<br>
"$Vd, $Rn", "", []> {<br>
let Rm = 0b1111;<br>
let Inst{5-4} = Rn{5-4};<br>
let DecoderMethod = "DecodeVLDST1Instruction";<br>
}<br>
-multiclass VLD1D4WB<bits<4> op7_4, string Dt> {<br>
+multiclass VLD1D4WB<bits<4> op7_4, string Dt, Operand AddrMode> {<br>
def _fixed : NLdSt<0,0b10,0b0010, op7_4, (outs VecListFourD:$Vd, GPR:$wb),<br>
- (ins addrmode6:$Rn), IIC_VLD1x2u,<br>
+ (ins AddrMode:$Rn), IIC_VLD1x2u,<br>
"vld1", Dt, "$Vd, $Rn!",<br>
"$Rn.addr = $wb", []> {<br>
let Rm = 0b1101; // NLdSt will assign to the right encoding bits.<br>
@@ -749,7 +749,7 @@ multiclass VLD1D4WB<bits<4> op7_4, strin<br>
let DecoderMethod = "DecodeVLDST1Instruction";<br>
}<br>
def _register : NLdSt<0,0b10,0b0010,op7_4, (outs VecListFourD:$Vd, GPR:$wb),<br>
- (ins addrmode6:$Rn, rGPR:$Rm), IIC_VLD1x2u,<br>
+ (ins AddrMode:$Rn, rGPR:$Rm), IIC_VLD1x2u,<br>
"vld1", Dt, "$Vd, $Rn, $Rm",<br>
"$Rn.addr = $wb", []> {<br>
let Inst{5-4} = Rn{5-4};<br>
@@ -757,15 +757,15 @@ multiclass VLD1D4WB<bits<4> op7_4, strin<br>
}<br>
}<br>
<br>
-def VLD1d8Q : VLD1D4<{0,0,?,?}, "8">;<br>
-def VLD1d16Q : VLD1D4<{0,1,?,?}, "16">;<br>
-def VLD1d32Q : VLD1D4<{1,0,?,?}, "32">;<br>
-def VLD1d64Q : VLD1D4<{1,1,?,?}, "64">;<br>
-<br>
-defm VLD1d8Qwb : VLD1D4WB<{0,0,?,?}, "8">;<br>
-defm VLD1d16Qwb : VLD1D4WB<{0,1,?,?}, "16">;<br>
-defm VLD1d32Qwb : VLD1D4WB<{1,0,?,?}, "32">;<br>
-defm VLD1d64Qwb : VLD1D4WB<{1,1,?,?}, "64">;<br>
+def VLD1d8Q : VLD1D4<{0,0,?,?}, "8", addrmode6align64or128or256>;<br>
+def VLD1d16Q : VLD1D4<{0,1,?,?}, "16", addrmode6align64or128or256>;<br>
+def VLD1d32Q : VLD1D4<{1,0,?,?}, "32", addrmode6align64or128or256>;<br>
+def VLD1d64Q : VLD1D4<{1,1,?,?}, "64", addrmode6align64or128or256>;<br>
+<br>
+defm VLD1d8Qwb : VLD1D4WB<{0,0,?,?}, "8", addrmode6align64or128or256>;<br>
+defm VLD1d16Qwb : VLD1D4WB<{0,1,?,?}, "16", addrmode6align64or128or256>;<br>
+defm VLD1d32Qwb : VLD1D4WB<{1,0,?,?}, "32", addrmode6align64or128or256>;<br>
+defm VLD1d64Qwb : VLD1D4WB<{1,1,?,?}, "64", addrmode6align64or128or256>;<br>
<br>
def VLD1d64QPseudo : VLDQQPseudo<IIC_VLD1x4>;<br>
def VLD1d64QPseudoWB_fixed : VLDQQWBfixedPseudo<IIC_VLD1x4>;<br>
@@ -773,22 +773,28 @@ def VLD1d64QPseudoWB_register : VLDQQWBr<br>
<br>
// VLD2 : Vector Load (multiple 2-element structures)<br>
class VLD2<bits<4> op11_8, bits<4> op7_4, string Dt, RegisterOperand VdTy,<br>
- InstrItinClass itin><br>
+ InstrItinClass itin, Operand AddrMode><br>
: NLdSt<0, 0b10, op11_8, op7_4, (outs VdTy:$Vd),<br>
- (ins addrmode6:$Rn), itin,<br>
+ (ins AddrMode:$Rn), itin,<br>
"vld2", Dt, "$Vd, $Rn", "", []> {<br>
let Rm = 0b1111;<br>
let Inst{5-4} = Rn{5-4};<br>
let DecoderMethod = "DecodeVLDST2Instruction";<br>
}<br>
<br>
-def VLD2d8 : VLD2<0b1000, {0,0,?,?}, "8", VecListDPair, IIC_VLD2>;<br>
-def VLD2d16 : VLD2<0b1000, {0,1,?,?}, "16", VecListDPair, IIC_VLD2>;<br>
-def VLD2d32 : VLD2<0b1000, {1,0,?,?}, "32", VecListDPair, IIC_VLD2>;<br>
-<br>
-def VLD2q8 : VLD2<0b0011, {0,0,?,?}, "8", VecListFourD, IIC_VLD2x2>;<br>
-def VLD2q16 : VLD2<0b0011, {0,1,?,?}, "16", VecListFourD, IIC_VLD2x2>;<br>
-def VLD2q32 : VLD2<0b0011, {1,0,?,?}, "32", VecListFourD, IIC_VLD2x2>;<br>
+def VLD2d8 : VLD2<0b1000, {0,0,?,?}, "8", VecListDPair, IIC_VLD2,<br>
+ addrmode6align64or128>;<br>
+def VLD2d16 : VLD2<0b1000, {0,1,?,?}, "16", VecListDPair, IIC_VLD2,<br>
+ addrmode6align64or128>;<br>
+def VLD2d32 : VLD2<0b1000, {1,0,?,?}, "32", VecListDPair, IIC_VLD2,<br>
+ addrmode6align64or128>;<br>
+<br>
+def VLD2q8 : VLD2<0b0011, {0,0,?,?}, "8", VecListFourD, IIC_VLD2x2,<br>
+ addrmode6align64or128or256>;<br>
+def VLD2q16 : VLD2<0b0011, {0,1,?,?}, "16", VecListFourD, IIC_VLD2x2,<br>
+ addrmode6align64or128or256>;<br>
+def VLD2q32 : VLD2<0b0011, {1,0,?,?}, "32", VecListFourD, IIC_VLD2x2,<br>
+ addrmode6align64or128or256>;<br>
<br>
def VLD2q8Pseudo : VLDQQPseudo<IIC_VLD2x2>;<br>
def VLD2q16Pseudo : VLDQQPseudo<IIC_VLD2x2>;<br>
@@ -796,9 +802,9 @@ def VLD2q32Pseudo : VLDQQPseudo<IIC_VLD<br>
<br>
// ...with address register writeback:<br>
multiclass VLD2WB<bits<4> op11_8, bits<4> op7_4, string Dt,<br>
- RegisterOperand VdTy, InstrItinClass itin> {<br>
+ RegisterOperand VdTy, InstrItinClass itin, Operand AddrMode> {<br>
def _fixed : NLdSt<0, 0b10, op11_8, op7_4, (outs VdTy:$Vd, GPR:$wb),<br>
- (ins addrmode6:$Rn), itin,<br>
+ (ins AddrMode:$Rn), itin,<br>
"vld2", Dt, "$Vd, $Rn!",<br>
"$Rn.addr = $wb", []> {<br>
let Rm = 0b1101; // NLdSt will assign to the right encoding bits.<br>
@@ -806,7 +812,7 @@ multiclass VLD2WB<bits<4> op11_8, bits<4<br>
let DecoderMethod = "DecodeVLDST2Instruction";<br>
}<br>
def _register : NLdSt<0, 0b10, op11_8, op7_4, (outs VdTy:$Vd, GPR:$wb),<br>
- (ins addrmode6:$Rn, rGPR:$Rm), itin,<br>
+ (ins AddrMode:$Rn, rGPR:$Rm), itin,<br>
"vld2", Dt, "$Vd, $Rn, $Rm",<br>
"$Rn.addr = $wb", []> {<br>
let Inst{5-4} = Rn{5-4};<br>
@@ -814,13 +820,19 @@ multiclass VLD2WB<bits<4> op11_8, bits<4<br>
}<br>
}<br>
<br>
-defm VLD2d8wb : VLD2WB<0b1000, {0,0,?,?}, "8", VecListDPair, IIC_VLD2u>;<br>
-defm VLD2d16wb : VLD2WB<0b1000, {0,1,?,?}, "16", VecListDPair, IIC_VLD2u>;<br>
-defm VLD2d32wb : VLD2WB<0b1000, {1,0,?,?}, "32", VecListDPair, IIC_VLD2u>;<br>
-<br>
-defm VLD2q8wb : VLD2WB<0b0011, {0,0,?,?}, "8", VecListFourD, IIC_VLD2x2u>;<br>
-defm VLD2q16wb : VLD2WB<0b0011, {0,1,?,?}, "16", VecListFourD, IIC_VLD2x2u>;<br>
-defm VLD2q32wb : VLD2WB<0b0011, {1,0,?,?}, "32", VecListFourD, IIC_VLD2x2u>;<br>
+defm VLD2d8wb : VLD2WB<0b1000, {0,0,?,?}, "8", VecListDPair, IIC_VLD2u,<br>
+ addrmode6align64or128>;<br>
+defm VLD2d16wb : VLD2WB<0b1000, {0,1,?,?}, "16", VecListDPair, IIC_VLD2u,<br>
+ addrmode6align64or128>;<br>
+defm VLD2d32wb : VLD2WB<0b1000, {1,0,?,?}, "32", VecListDPair, IIC_VLD2u,<br>
+ addrmode6align64or128>;<br>
+<br>
+defm VLD2q8wb : VLD2WB<0b0011, {0,0,?,?}, "8", VecListFourD, IIC_VLD2x2u,<br>
+ addrmode6align64or128or256>;<br>
+defm VLD2q16wb : VLD2WB<0b0011, {0,1,?,?}, "16", VecListFourD, IIC_VLD2x2u,<br>
+ addrmode6align64or128or256>;<br>
+defm VLD2q32wb : VLD2WB<0b0011, {1,0,?,?}, "32", VecListFourD, IIC_VLD2x2u,<br>
+ addrmode6align64or128or256>;<br>
<br>
def VLD2q8PseudoWB_fixed : VLDQQWBfixedPseudo<IIC_VLD2x2u>;<br>
def VLD2q16PseudoWB_fixed : VLDQQWBfixedPseudo<IIC_VLD2x2u>;<br>
@@ -830,12 +842,18 @@ def VLD2q16PseudoWB_register : VLDQQWBre<br>
def VLD2q32PseudoWB_register : VLDQQWBregisterPseudo<IIC_VLD2x2u>;<br>
<br>
// ...with double-spaced registers<br>
-def VLD2b8 : VLD2<0b1001, {0,0,?,?}, "8", VecListDPairSpaced, IIC_VLD2>;<br>
-def VLD2b16 : VLD2<0b1001, {0,1,?,?}, "16", VecListDPairSpaced, IIC_VLD2>;<br>
-def VLD2b32 : VLD2<0b1001, {1,0,?,?}, "32", VecListDPairSpaced, IIC_VLD2>;<br>
-defm VLD2b8wb : VLD2WB<0b1001, {0,0,?,?}, "8", VecListDPairSpaced, IIC_VLD2u>;<br>
-defm VLD2b16wb : VLD2WB<0b1001, {0,1,?,?}, "16", VecListDPairSpaced, IIC_VLD2u>;<br>
-defm VLD2b32wb : VLD2WB<0b1001, {1,0,?,?}, "32", VecListDPairSpaced, IIC_VLD2u>;<br>
+def VLD2b8 : VLD2<0b1001, {0,0,?,?}, "8", VecListDPairSpaced, IIC_VLD2,<br>
+ addrmode6align64or128>;<br>
+def VLD2b16 : VLD2<0b1001, {0,1,?,?}, "16", VecListDPairSpaced, IIC_VLD2,<br>
+ addrmode6align64or128>;<br>
+def VLD2b32 : VLD2<0b1001, {1,0,?,?}, "32", VecListDPairSpaced, IIC_VLD2,<br>
+ addrmode6align64or128>;<br>
+defm VLD2b8wb : VLD2WB<0b1001, {0,0,?,?}, "8", VecListDPairSpaced, IIC_VLD2u,<br>
+ addrmode6align64or128>;<br>
+defm VLD2b16wb : VLD2WB<0b1001, {0,1,?,?}, "16", VecListDPairSpaced, IIC_VLD2u,<br>
+ addrmode6align64or128>;<br>
+defm VLD2b32wb : VLD2WB<0b1001, {1,0,?,?}, "32", VecListDPairSpaced, IIC_VLD2u,<br>
+ addrmode6align64or128>;<br>
<br>
// VLD3 : Vector Load (multiple 3-element structures)<br>
class VLD3D<bits<4> op11_8, bits<4> op7_4, string Dt><br>
@@ -1293,47 +1311,55 @@ def VLD4LNq32Pseudo_UPD : VLDQQQQLNWBPse<br>
} // mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1<br>
<br>
// VLD1DUP : Vector Load (single element to all lanes)<br>
-class VLD1DUP<bits<4> op7_4, string Dt, ValueType Ty, PatFrag LoadOp><br>
+class VLD1DUP<bits<4> op7_4, string Dt, ValueType Ty, PatFrag LoadOp,<br>
+ Operand AddrMode><br>
: NLdSt<1, 0b10, 0b1100, op7_4, (outs VecListOneDAllLanes:$Vd),<br>
- (ins addrmode6dup:$Rn),<br>
+ (ins AddrMode:$Rn),<br>
IIC_VLD1dup, "vld1", Dt, "$Vd, $Rn", "",<br>
[(set VecListOneDAllLanes:$Vd,<br>
- (Ty (NEONvdup (i32 (LoadOp addrmode6dup:$Rn)))))]> {<br>
+ (Ty (NEONvdup (i32 (LoadOp AddrMode:$Rn)))))]> {<br>
let Rm = 0b1111;<br>
let Inst{4} = Rn{4};<br>
let DecoderMethod = "DecodeVLD1DupInstruction";<br>
}<br>
-def VLD1DUPd8 : VLD1DUP<{0,0,0,?}, "8", v8i8, extloadi8>;<br>
-def VLD1DUPd16 : VLD1DUP<{0,1,0,?}, "16", v4i16, extloadi16>;<br>
-def VLD1DUPd32 : VLD1DUP<{1,0,0,?}, "32", v2i32, load>;<br>
+def VLD1DUPd8 : VLD1DUP<{0,0,0,?}, "8", v8i8, extloadi8,<br>
+ addrmode6dupalignNone>;<br>
+def VLD1DUPd16 : VLD1DUP<{0,1,0,?}, "16", v4i16, extloadi16,<br>
+ addrmode6dupalign16>;<br>
+def VLD1DUPd32 : VLD1DUP<{1,0,0,?}, "32", v2i32, load,<br>
+ addrmode6dupalign32>;<br>
<br>
def : Pat<(v2f32 (NEONvdup (f32 (load addrmode6dup:$addr)))),<br>
(VLD1DUPd32 addrmode6:$addr)>;<br>
<br>
-class VLD1QDUP<bits<4> op7_4, string Dt, ValueType Ty, PatFrag LoadOp><br>
+class VLD1QDUP<bits<4> op7_4, string Dt, ValueType Ty, PatFrag LoadOp,<br>
+ Operand AddrMode><br>
: NLdSt<1, 0b10, 0b1100, op7_4, (outs VecListDPairAllLanes:$Vd),<br>
- (ins addrmode6dup:$Rn), IIC_VLD1dup,<br>
+ (ins AddrMode:$Rn), IIC_VLD1dup,<br>
"vld1", Dt, "$Vd, $Rn", "",<br>
[(set VecListDPairAllLanes:$Vd,<br>
- (Ty (NEONvdup (i32 (LoadOp addrmode6dup:$Rn)))))]> {<br>
+ (Ty (NEONvdup (i32 (LoadOp AddrMode:$Rn)))))]> {<br>
let Rm = 0b1111;<br>
let Inst{4} = Rn{4};<br>
let DecoderMethod = "DecodeVLD1DupInstruction";<br>
}<br>
<br>
-def VLD1DUPq8 : VLD1QDUP<{0,0,1,0}, "8", v16i8, extloadi8>;<br>
-def VLD1DUPq16 : VLD1QDUP<{0,1,1,?}, "16", v8i16, extloadi16>;<br>
-def VLD1DUPq32 : VLD1QDUP<{1,0,1,?}, "32", v4i32, load>;<br>
+def VLD1DUPq8 : VLD1QDUP<{0,0,1,0}, "8", v16i8, extloadi8,<br>
+ addrmode6dupalignNone>;<br>
+def VLD1DUPq16 : VLD1QDUP<{0,1,1,?}, "16", v8i16, extloadi16,<br>
+ addrmode6dupalign16>;<br>
+def VLD1DUPq32 : VLD1QDUP<{1,0,1,?}, "32", v4i32, load,<br>
+ addrmode6dupalign32>;<br>
<br>
def : Pat<(v4f32 (NEONvdup (f32 (load addrmode6dup:$addr)))),<br>
(VLD1DUPq32 addrmode6:$addr)>;<br>
<br>
let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {<br>
// ...with address register writeback:<br>
-multiclass VLD1DUPWB<bits<4> op7_4, string Dt> {<br>
+multiclass VLD1DUPWB<bits<4> op7_4, string Dt, Operand AddrMode> {<br>
def _fixed : NLdSt<1, 0b10, 0b1100, op7_4,<br>
(outs VecListOneDAllLanes:$Vd, GPR:$wb),<br>
- (ins addrmode6dup:$Rn), IIC_VLD1dupu,<br>
+ (ins AddrMode:$Rn), IIC_VLD1dupu,<br>
"vld1", Dt, "$Vd, $Rn!",<br>
"$Rn.addr = $wb", []> {<br>
let Rm = 0b1101; // NLdSt will assign to the right encoding bits.<br>
@@ -1342,17 +1368,17 @@ multiclass VLD1DUPWB<bits<4> op7_4, stri<br>
}<br>
def _register : NLdSt<1, 0b10, 0b1100, op7_4,<br>
(outs VecListOneDAllLanes:$Vd, GPR:$wb),<br>
- (ins addrmode6dup:$Rn, rGPR:$Rm), IIC_VLD1dupu,<br>
+ (ins AddrMode:$Rn, rGPR:$Rm), IIC_VLD1dupu,<br>
"vld1", Dt, "$Vd, $Rn, $Rm",<br>
"$Rn.addr = $wb", []> {<br>
let Inst{4} = Rn{4};<br>
let DecoderMethod = "DecodeVLD1DupInstruction";<br>
}<br>
}<br>
-multiclass VLD1QDUPWB<bits<4> op7_4, string Dt> {<br>
+multiclass VLD1QDUPWB<bits<4> op7_4, string Dt, Operand AddrMode> {<br>
def _fixed : NLdSt<1, 0b10, 0b1100, op7_4,<br>
(outs VecListDPairAllLanes:$Vd, GPR:$wb),<br>
- (ins addrmode6dup:$Rn), IIC_VLD1dupu,<br>
+ (ins AddrMode:$Rn), IIC_VLD1dupu,<br>
"vld1", Dt, "$Vd, $Rn!",<br>
"$Rn.addr = $wb", []> {<br>
let Rm = 0b1101; // NLdSt will assign to the right encoding bits.<br>
@@ -1361,7 +1387,7 @@ multiclass VLD1QDUPWB<bits<4> op7_4, str<br>
}<br>
def _register : NLdSt<1, 0b10, 0b1100, op7_4,<br>
(outs VecListDPairAllLanes:$Vd, GPR:$wb),<br>
- (ins addrmode6dup:$Rn, rGPR:$Rm), IIC_VLD1dupu,<br>
+ (ins AddrMode:$Rn, rGPR:$Rm), IIC_VLD1dupu,<br>
"vld1", Dt, "$Vd, $Rn, $Rm",<br>
"$Rn.addr = $wb", []> {<br>
let Inst{4} = Rn{4};<br>
@@ -1369,38 +1395,47 @@ multiclass VLD1QDUPWB<bits<4> op7_4, str<br>
}<br>
}<br>
<br>
-defm VLD1DUPd8wb : VLD1DUPWB<{0,0,0,0}, "8">;<br>
-defm VLD1DUPd16wb : VLD1DUPWB<{0,1,0,?}, "16">;<br>
-defm VLD1DUPd32wb : VLD1DUPWB<{1,0,0,?}, "32">;<br>
-<br>
-defm VLD1DUPq8wb : VLD1QDUPWB<{0,0,1,0}, "8">;<br>
-defm VLD1DUPq16wb : VLD1QDUPWB<{0,1,1,?}, "16">;<br>
-defm VLD1DUPq32wb : VLD1QDUPWB<{1,0,1,?}, "32">;<br>
+defm VLD1DUPd8wb : VLD1DUPWB<{0,0,0,0}, "8", addrmode6dupalignNone>;<br>
+defm VLD1DUPd16wb : VLD1DUPWB<{0,1,0,?}, "16", addrmode6dupalign16>;<br>
+defm VLD1DUPd32wb : VLD1DUPWB<{1,0,0,?}, "32", addrmode6dupalign32>;<br>
+<br>
+defm VLD1DUPq8wb : VLD1QDUPWB<{0,0,1,0}, "8", addrmode6dupalignNone>;<br>
+defm VLD1DUPq16wb : VLD1QDUPWB<{0,1,1,?}, "16", addrmode6dupalign16>;<br>
+defm VLD1DUPq32wb : VLD1QDUPWB<{1,0,1,?}, "32", addrmode6dupalign32>;<br>
<br>
// VLD2DUP : Vector Load (single 2-element structure to all lanes)<br>
-class VLD2DUP<bits<4> op7_4, string Dt, RegisterOperand VdTy><br>
+class VLD2DUP<bits<4> op7_4, string Dt, RegisterOperand VdTy, Operand AddrMode><br>
: NLdSt<1, 0b10, 0b1101, op7_4, (outs VdTy:$Vd),<br>
- (ins addrmode6dup:$Rn), IIC_VLD2dup,<br>
+ (ins AddrMode:$Rn), IIC_VLD2dup,<br>
"vld2", Dt, "$Vd, $Rn", "", []> {<br>
let Rm = 0b1111;<br>
let Inst{4} = Rn{4};<br>
let DecoderMethod = "DecodeVLD2DupInstruction";<br>
}<br>
<br>
-def VLD2DUPd8 : VLD2DUP<{0,0,0,?}, "8", VecListDPairAllLanes>;<br>
-def VLD2DUPd16 : VLD2DUP<{0,1,0,?}, "16", VecListDPairAllLanes>;<br>
-def VLD2DUPd32 : VLD2DUP<{1,0,0,?}, "32", VecListDPairAllLanes>;<br>
+def VLD2DUPd8 : VLD2DUP<{0,0,0,?}, "8", VecListDPairAllLanes,<br>
+ addrmode6dupalign16>;<br>
+def VLD2DUPd16 : VLD2DUP<{0,1,0,?}, "16", VecListDPairAllLanes,<br>
+ addrmode6dupalign32>;<br>
+def VLD2DUPd32 : VLD2DUP<{1,0,0,?}, "32", VecListDPairAllLanes,<br>
+ addrmode6dupalign64>;<br>
<br>
+// HACK this one, VLD2DUPd8x2 must be changed at the same time with VLD2b8 or<br>
+// "vld2.8 {d0[], d2[]}, [r4:32]" will become "vld2.8 {d0, d2}, [r4:32]".<br>
// ...with double-spaced registers<br>
-def VLD2DUPd8x2 : VLD2DUP<{0,0,1,?}, "8", VecListDPairSpacedAllLanes>;<br>
-def VLD2DUPd16x2 : VLD2DUP<{0,1,1,?}, "16", VecListDPairSpacedAllLanes>;<br>
-def VLD2DUPd32x2 : VLD2DUP<{1,0,1,?}, "32", VecListDPairSpacedAllLanes>;<br>
+def VLD2DUPd8x2 : VLD2DUP<{0,0,1,?}, "8", VecListDPairSpacedAllLanes,<br>
+ addrmode6dupalign16>;<br>
+def VLD2DUPd16x2 : VLD2DUP<{0,1,1,?}, "16", VecListDPairSpacedAllLanes,<br>
+ addrmode6dupalign32>;<br>
+def VLD2DUPd32x2 : VLD2DUP<{1,0,1,?}, "32", VecListDPairSpacedAllLanes,<br>
+ addrmode6dupalign64>;<br>
<br>
// ...with address register writeback:<br>
-multiclass VLD2DUPWB<bits<4> op7_4, string Dt, RegisterOperand VdTy> {<br>
+multiclass VLD2DUPWB<bits<4> op7_4, string Dt, RegisterOperand VdTy,<br>
+ Operand AddrMode> {<br>
def _fixed : NLdSt<1, 0b10, 0b1101, op7_4,<br>
(outs VdTy:$Vd, GPR:$wb),<br>
- (ins addrmode6dup:$Rn), IIC_VLD2dupu,<br>
+ (ins AddrMode:$Rn), IIC_VLD2dupu,<br>
"vld2", Dt, "$Vd, $Rn!",<br>
"$Rn.addr = $wb", []> {<br>
let Rm = 0b1101; // NLdSt will assign to the right encoding bits.<br>
@@ -1409,7 +1444,7 @@ multiclass VLD2DUPWB<bits<4> op7_4, stri<br>
}<br>
def _register : NLdSt<1, 0b10, 0b1101, op7_4,<br>
(outs VdTy:$Vd, GPR:$wb),<br>
- (ins addrmode6dup:$Rn, rGPR:$Rm), IIC_VLD2dupu,<br>
+ (ins AddrMode:$Rn, rGPR:$Rm), IIC_VLD2dupu,<br>
"vld2", Dt, "$Vd, $Rn, $Rm",<br>
"$Rn.addr = $wb", []> {<br>
let Inst{4} = Rn{4};<br>
@@ -1417,13 +1452,19 @@ multiclass VLD2DUPWB<bits<4> op7_4, stri<br>
}<br>
}<br>
<br>
-defm VLD2DUPd8wb : VLD2DUPWB<{0,0,0,0}, "8", VecListDPairAllLanes>;<br>
-defm VLD2DUPd16wb : VLD2DUPWB<{0,1,0,?}, "16", VecListDPairAllLanes>;<br>
-defm VLD2DUPd32wb : VLD2DUPWB<{1,0,0,?}, "32", VecListDPairAllLanes>;<br>
-<br>
-defm VLD2DUPd8x2wb : VLD2DUPWB<{0,0,1,0}, "8", VecListDPairSpacedAllLanes>;<br>
-defm VLD2DUPd16x2wb : VLD2DUPWB<{0,1,1,?}, "16", VecListDPairSpacedAllLanes>;<br>
-defm VLD2DUPd32x2wb : VLD2DUPWB<{1,0,1,?}, "32", VecListDPairSpacedAllLanes>;<br>
+defm VLD2DUPd8wb : VLD2DUPWB<{0,0,0,0}, "8", VecListDPairAllLanes,<br>
+ addrmode6dupalign16>;<br>
+defm VLD2DUPd16wb : VLD2DUPWB<{0,1,0,?}, "16", VecListDPairAllLanes,<br>
+ addrmode6dupalign32>;<br>
+defm VLD2DUPd32wb : VLD2DUPWB<{1,0,0,?}, "32", VecListDPairAllLanes,<br>
+ addrmode6dupalign64>;<br>
+<br>
+defm VLD2DUPd8x2wb : VLD2DUPWB<{0,0,1,0}, "8", VecListDPairSpacedAllLanes,<br>
+ addrmode6dupalign16>;<br>
+defm VLD2DUPd16x2wb : VLD2DUPWB<{0,1,1,?}, "16", VecListDPairSpacedAllLanes,<br>
+ addrmode6dupalign32>;<br>
+defm VLD2DUPd32x2wb : VLD2DUPWB<{1,0,1,?}, "32", VecListDPairSpacedAllLanes,<br>
+ addrmode6dupalign64>;<br>
<br>
// VLD3DUP : Vector Load (single 3-element structure to all lanes)<br>
class VLD3DUP<bits<4> op7_4, string Dt><br>
@@ -1449,22 +1490,22 @@ def VLD3DUPq16 : VLD3DUP<{0,1,1,?}, "16"<br>
def VLD3DUPq32 : VLD3DUP<{1,0,1,?}, "32">;<br>
<br>
// ...with address register writeback:<br>
-class VLD3DUPWB<bits<4> op7_4, string Dt><br>
+class VLD3DUPWB<bits<4> op7_4, string Dt, Operand AddrMode><br>
: NLdSt<1, 0b10, 0b1110, op7_4, (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, GPR:$wb),<br>
- (ins addrmode6dup:$Rn, am6offset:$Rm), IIC_VLD3dupu,<br>
+ (ins AddrMode:$Rn, am6offset:$Rm), IIC_VLD3dupu,<br>
"vld3", Dt, "\\{$Vd[], $dst2[], $dst3[]\\}, $Rn$Rm",<br>
"$Rn.addr = $wb", []> {<br>
let Inst{4} = 0;<br>
let DecoderMethod = "DecodeVLD3DupInstruction";<br>
}<br>
<br>
-def VLD3DUPd8_UPD : VLD3DUPWB<{0,0,0,0}, "8">;<br>
-def VLD3DUPd16_UPD : VLD3DUPWB<{0,1,0,?}, "16">;<br>
-def VLD3DUPd32_UPD : VLD3DUPWB<{1,0,0,?}, "32">;<br>
-<br>
-def VLD3DUPq8_UPD : VLD3DUPWB<{0,0,1,0}, "8">;<br>
-def VLD3DUPq16_UPD : VLD3DUPWB<{0,1,1,?}, "16">;<br>
-def VLD3DUPq32_UPD : VLD3DUPWB<{1,0,1,?}, "32">;<br>
+def VLD3DUPd8_UPD : VLD3DUPWB<{0,0,0,0}, "8", addrmode6dupalign64>;<br>
+def VLD3DUPd16_UPD : VLD3DUPWB<{0,1,0,?}, "16", addrmode6dupalign64>;<br>
+def VLD3DUPd32_UPD : VLD3DUPWB<{1,0,0,?}, "32", addrmode6dupalign64>;<br>
+<br>
+def VLD3DUPq8_UPD : VLD3DUPWB<{0,0,1,0}, "8", addrmode6dupalign64>;<br>
+def VLD3DUPq16_UPD : VLD3DUPWB<{0,1,1,?}, "16", addrmode6dupalign64>;<br>
+def VLD3DUPq32_UPD : VLD3DUPWB<{1,0,1,?}, "32", addrmode6dupalign64>;<br>
<br>
def VLD3DUPd8Pseudo_UPD : VLDQQWBPseudo<IIC_VLD3dupu>;<br>
def VLD3DUPd16Pseudo_UPD : VLDQQWBPseudo<IIC_VLD3dupu>;<br>
@@ -1560,35 +1601,35 @@ class VSTQQQQWBPseudo<InstrItinClass iti<br>
"$addr.addr = $wb">;<br>
<br>
// VST1 : Vector Store (multiple single elements)<br>
-class VST1D<bits<4> op7_4, string Dt><br>
- : NLdSt<0,0b00,0b0111,op7_4, (outs), (ins addrmode6:$Rn, VecListOneD:$Vd),<br>
+class VST1D<bits<4> op7_4, string Dt, Operand AddrMode><br>
+ : NLdSt<0,0b00,0b0111,op7_4, (outs), (ins AddrMode:$Rn, VecListOneD:$Vd),<br>
IIC_VST1, "vst1", Dt, "$Vd, $Rn", "", []> {<br>
let Rm = 0b1111;<br>
let Inst{4} = Rn{4};<br>
let DecoderMethod = "DecodeVLDST1Instruction";<br>
}<br>
-class VST1Q<bits<4> op7_4, string Dt><br>
- : NLdSt<0,0b00,0b1010,op7_4, (outs), (ins addrmode6:$Rn, VecListDPair:$Vd),<br>
+class VST1Q<bits<4> op7_4, string Dt, Operand AddrMode><br>
+ : NLdSt<0,0b00,0b1010,op7_4, (outs), (ins AddrMode:$Rn, VecListDPair:$Vd),<br>
IIC_VST1x2, "vst1", Dt, "$Vd, $Rn", "", []> {<br>
let Rm = 0b1111;<br>
let Inst{5-4} = Rn{5-4};<br>
let DecoderMethod = "DecodeVLDST1Instruction";<br>
}<br>
<br>
-def VST1d8 : VST1D<{0,0,0,?}, "8">;<br>
-def VST1d16 : VST1D<{0,1,0,?}, "16">;<br>
-def VST1d32 : VST1D<{1,0,0,?}, "32">;<br>
-def VST1d64 : VST1D<{1,1,0,?}, "64">;<br>
-<br>
-def VST1q8 : VST1Q<{0,0,?,?}, "8">;<br>
-def VST1q16 : VST1Q<{0,1,?,?}, "16">;<br>
-def VST1q32 : VST1Q<{1,0,?,?}, "32">;<br>
-def VST1q64 : VST1Q<{1,1,?,?}, "64">;<br>
+def VST1d8 : VST1D<{0,0,0,?}, "8", addrmode6align64>;<br>
+def VST1d16 : VST1D<{0,1,0,?}, "16", addrmode6align64>;<br>
+def VST1d32 : VST1D<{1,0,0,?}, "32", addrmode6align64>;<br>
+def VST1d64 : VST1D<{1,1,0,?}, "64", addrmode6align64>;<br>
+<br>
+def VST1q8 : VST1Q<{0,0,?,?}, "8", addrmode6align64or128>;<br>
+def VST1q16 : VST1Q<{0,1,?,?}, "16", addrmode6align64or128>;<br>
+def VST1q32 : VST1Q<{1,0,?,?}, "32", addrmode6align64or128>;<br>
+def VST1q64 : VST1Q<{1,1,?,?}, "64", addrmode6align64or128>;<br>
<br>
// ...with address register writeback:<br>
-multiclass VST1DWB<bits<4> op7_4, string Dt> {<br>
+multiclass VST1DWB<bits<4> op7_4, string Dt, Operand AddrMode> {<br>
def _fixed : NLdSt<0,0b00, 0b0111,op7_4, (outs GPR:$wb),<br>
- (ins addrmode6:$Rn, VecListOneD:$Vd), IIC_VLD1u,<br>
+ (ins AddrMode:$Rn, VecListOneD:$Vd), IIC_VLD1u,<br>
"vst1", Dt, "$Vd, $Rn!",<br>
"$Rn.addr = $wb", []> {<br>
let Rm = 0b1101; // NLdSt will assign to the right encoding bits.<br>
@@ -1596,7 +1637,7 @@ multiclass VST1DWB<bits<4> op7_4, string<br>
let DecoderMethod = "DecodeVLDST1Instruction";<br>
}<br>
def _register : NLdSt<0,0b00,0b0111,op7_4, (outs GPR:$wb),<br>
- (ins addrmode6:$Rn, rGPR:$Rm, VecListOneD:$Vd),<br>
+ (ins AddrMode:$Rn, rGPR:$Rm, VecListOneD:$Vd),<br>
IIC_VLD1u,<br>
"vst1", Dt, "$Vd, $Rn, $Rm",<br>
"$Rn.addr = $wb", []> {<br>
@@ -1604,9 +1645,9 @@ multiclass VST1DWB<bits<4> op7_4, string<br>
let DecoderMethod = "DecodeVLDST1Instruction";<br>
}<br>
}<br>
-multiclass VST1QWB<bits<4> op7_4, string Dt> {<br>
+multiclass VST1QWB<bits<4> op7_4, string Dt, Operand AddrMode> {<br>
def _fixed : NLdSt<0,0b00,0b1010,op7_4, (outs GPR:$wb),<br>
- (ins addrmode6:$Rn, VecListDPair:$Vd), IIC_VLD1x2u,<br>
+ (ins AddrMode:$Rn, VecListDPair:$Vd), IIC_VLD1x2u,<br>
"vst1", Dt, "$Vd, $Rn!",<br>
"$Rn.addr = $wb", []> {<br>
let Rm = 0b1101; // NLdSt will assign to the right encoding bits.<br>
@@ -1614,7 +1655,7 @@ multiclass VST1QWB<bits<4> op7_4, string<br>
let DecoderMethod = "DecodeVLDST1Instruction";<br>
}<br>
def _register : NLdSt<0,0b00,0b1010,op7_4, (outs GPR:$wb),<br>
- (ins addrmode6:$Rn, rGPR:$Rm, VecListDPair:$Vd),<br>
+ (ins AddrMode:$Rn, rGPR:$Rm, VecListDPair:$Vd),<br>
IIC_VLD1x2u,<br>
"vst1", Dt, "$Vd, $Rn, $Rm",<br>
"$Rn.addr = $wb", []> {<br>
@@ -1623,28 +1664,28 @@ multiclass VST1QWB<bits<4> op7_4, string<br>
}<br>
}<br>
<br>
-defm VST1d8wb : VST1DWB<{0,0,0,?}, "8">;<br>
-defm VST1d16wb : VST1DWB<{0,1,0,?}, "16">;<br>
-defm VST1d32wb : VST1DWB<{1,0,0,?}, "32">;<br>
-defm VST1d64wb : VST1DWB<{1,1,0,?}, "64">;<br>
-<br>
-defm VST1q8wb : VST1QWB<{0,0,?,?}, "8">;<br>
-defm VST1q16wb : VST1QWB<{0,1,?,?}, "16">;<br>
-defm VST1q32wb : VST1QWB<{1,0,?,?}, "32">;<br>
-defm VST1q64wb : VST1QWB<{1,1,?,?}, "64">;<br>
+defm VST1d8wb : VST1DWB<{0,0,0,?}, "8", addrmode6align64>;<br>
+defm VST1d16wb : VST1DWB<{0,1,0,?}, "16", addrmode6align64>;<br>
+defm VST1d32wb : VST1DWB<{1,0,0,?}, "32", addrmode6align64>;<br>
+defm VST1d64wb : VST1DWB<{1,1,0,?}, "64", addrmode6align64>;<br>
+<br>
+defm VST1q8wb : VST1QWB<{0,0,?,?}, "8", addrmode6align64or128>;<br>
+defm VST1q16wb : VST1QWB<{0,1,?,?}, "16", addrmode6align64or128>;<br>
+defm VST1q32wb : VST1QWB<{1,0,?,?}, "32", addrmode6align64or128>;<br>
+defm VST1q64wb : VST1QWB<{1,1,?,?}, "64", addrmode6align64or128>;<br>
<br>
// ...with 3 registers<br>
-class VST1D3<bits<4> op7_4, string Dt><br>
+class VST1D3<bits<4> op7_4, string Dt, Operand AddrMode><br>
: NLdSt<0, 0b00, 0b0110, op7_4, (outs),<br>
- (ins addrmode6:$Rn, VecListThreeD:$Vd),<br>
+ (ins AddrMode:$Rn, VecListThreeD:$Vd),<br>
IIC_VST1x3, "vst1", Dt, "$Vd, $Rn", "", []> {<br>
let Rm = 0b1111;<br>
let Inst{4} = Rn{4};<br>
let DecoderMethod = "DecodeVLDST1Instruction";<br>
}<br>
-multiclass VST1D3WB<bits<4> op7_4, string Dt> {<br>
+multiclass VST1D3WB<bits<4> op7_4, string Dt, Operand AddrMode> {<br>
def _fixed : NLdSt<0,0b00,0b0110,op7_4, (outs GPR:$wb),<br>
- (ins addrmode6:$Rn, VecListThreeD:$Vd), IIC_VLD1x3u,<br>
+ (ins AddrMode:$Rn, VecListThreeD:$Vd), IIC_VLD1x3u,<br>
"vst1", Dt, "$Vd, $Rn!",<br>
"$Rn.addr = $wb", []> {<br>
let Rm = 0b1101; // NLdSt will assign to the right encoding bits.<br>
@@ -1652,7 +1693,7 @@ multiclass VST1D3WB<bits<4> op7_4, strin<br>
let DecoderMethod = "DecodeVLDST1Instruction";<br>
}<br>
def _register : NLdSt<0,0b00,0b0110,op7_4, (outs GPR:$wb),<br>
- (ins addrmode6:$Rn, rGPR:$Rm, VecListThreeD:$Vd),<br>
+ (ins AddrMode:$Rn, rGPR:$Rm, VecListThreeD:$Vd),<br>
IIC_VLD1x3u,<br>
"vst1", Dt, "$Vd, $Rn, $Rm",<br>
"$Rn.addr = $wb", []> {<br>
@@ -1661,33 +1702,33 @@ multiclass VST1D3WB<bits<4> op7_4, strin<br>
}<br>
}<br>
<br>
-def VST1d8T : VST1D3<{0,0,0,?}, "8">;<br>
-def VST1d16T : VST1D3<{0,1,0,?}, "16">;<br>
-def VST1d32T : VST1D3<{1,0,0,?}, "32">;<br>
-def VST1d64T : VST1D3<{1,1,0,?}, "64">;<br>
-<br>
-defm VST1d8Twb : VST1D3WB<{0,0,0,?}, "8">;<br>
-defm VST1d16Twb : VST1D3WB<{0,1,0,?}, "16">;<br>
-defm VST1d32Twb : VST1D3WB<{1,0,0,?}, "32">;<br>
-defm VST1d64Twb : VST1D3WB<{1,1,0,?}, "64">;<br>
+def VST1d8T : VST1D3<{0,0,0,?}, "8", addrmode6align64>;<br>
+def VST1d16T : VST1D3<{0,1,0,?}, "16", addrmode6align64>;<br>
+def VST1d32T : VST1D3<{1,0,0,?}, "32", addrmode6align64>;<br>
+def VST1d64T : VST1D3<{1,1,0,?}, "64", addrmode6align64>;<br>
+<br>
+defm VST1d8Twb : VST1D3WB<{0,0,0,?}, "8", addrmode6align64>;<br>
+defm VST1d16Twb : VST1D3WB<{0,1,0,?}, "16", addrmode6align64>;<br>
+defm VST1d32Twb : VST1D3WB<{1,0,0,?}, "32", addrmode6align64>;<br>
+defm VST1d64Twb : VST1D3WB<{1,1,0,?}, "64", addrmode6align64>;<br>
<br>
def VST1d64TPseudo : VSTQQPseudo<IIC_VST1x3>;<br>
def VST1d64TPseudoWB_fixed : VSTQQWBfixedPseudo<IIC_VST1x3u>;<br>
def VST1d64TPseudoWB_register : VSTQQWBPseudo<IIC_VST1x3u>;<br>
<br>
// ...with 4 registers<br>
-class VST1D4<bits<4> op7_4, string Dt><br>
+class VST1D4<bits<4> op7_4, string Dt, Operand AddrMode><br>
: NLdSt<0, 0b00, 0b0010, op7_4, (outs),<br>
- (ins addrmode6:$Rn, VecListFourD:$Vd),<br>
+ (ins AddrMode:$Rn, VecListFourD:$Vd),<br>
IIC_VST1x4, "vst1", Dt, "$Vd, $Rn", "",<br>
[]> {<br>
let Rm = 0b1111;<br>
let Inst{5-4} = Rn{5-4};<br>
let DecoderMethod = "DecodeVLDST1Instruction";<br>
}<br>
-multiclass VST1D4WB<bits<4> op7_4, string Dt> {<br>
+multiclass VST1D4WB<bits<4> op7_4, string Dt, Operand AddrMode> {<br>
def _fixed : NLdSt<0,0b00,0b0010,op7_4, (outs GPR:$wb),<br>
- (ins addrmode6:$Rn, VecListFourD:$Vd), IIC_VLD1x4u,<br>
+ (ins AddrMode:$Rn, VecListFourD:$Vd), IIC_VLD1x4u,<br>
"vst1", Dt, "$Vd, $Rn!",<br>
"$Rn.addr = $wb", []> {<br>
let Rm = 0b1101; // NLdSt will assign to the right encoding bits.<br>
@@ -1695,7 +1736,7 @@ multiclass VST1D4WB<bits<4> op7_4, strin<br>
let DecoderMethod = "DecodeVLDST1Instruction";<br>
}<br>
def _register : NLdSt<0,0b00,0b0010,op7_4, (outs GPR:$wb),<br>
- (ins addrmode6:$Rn, rGPR:$Rm, VecListFourD:$Vd),<br>
+ (ins AddrMode:$Rn, rGPR:$Rm, VecListFourD:$Vd),<br>
IIC_VLD1x4u,<br>
"vst1", Dt, "$Vd, $Rn, $Rm",<br>
"$Rn.addr = $wb", []> {<br>
@@ -1704,15 +1745,15 @@ multiclass VST1D4WB<bits<4> op7_4, strin<br>
}<br>
}<br>
<br>
-def VST1d8Q : VST1D4<{0,0,?,?}, "8">;<br>
-def VST1d16Q : VST1D4<{0,1,?,?}, "16">;<br>
-def VST1d32Q : VST1D4<{1,0,?,?}, "32">;<br>
-def VST1d64Q : VST1D4<{1,1,?,?}, "64">;<br>
-<br>
-defm VST1d8Qwb : VST1D4WB<{0,0,?,?}, "8">;<br>
-defm VST1d16Qwb : VST1D4WB<{0,1,?,?}, "16">;<br>
-defm VST1d32Qwb : VST1D4WB<{1,0,?,?}, "32">;<br>
-defm VST1d64Qwb : VST1D4WB<{1,1,?,?}, "64">;<br>
+def VST1d8Q : VST1D4<{0,0,?,?}, "8", addrmode6align64or128or256>;<br>
+def VST1d16Q : VST1D4<{0,1,?,?}, "16", addrmode6align64or128or256>;<br>
+def VST1d32Q : VST1D4<{1,0,?,?}, "32", addrmode6align64or128or256>;<br>
+def VST1d64Q : VST1D4<{1,1,?,?}, "64", addrmode6align64or128or256>;<br>
+<br>
+defm VST1d8Qwb : VST1D4WB<{0,0,?,?}, "8", addrmode6align64or128or256>;<br>
+defm VST1d16Qwb : VST1D4WB<{0,1,?,?}, "16", addrmode6align64or128or256>;<br>
+defm VST1d32Qwb : VST1D4WB<{1,0,?,?}, "32", addrmode6align64or128or256>;<br>
+defm VST1d64Qwb : VST1D4WB<{1,1,?,?}, "64", addrmode6align64or128or256>;<br>
<br>
def VST1d64QPseudo : VSTQQPseudo<IIC_VST1x4>;<br>
def VST1d64QPseudoWB_fixed : VSTQQWBfixedPseudo<IIC_VST1x4u>;<br>
@@ -1720,21 +1761,27 @@ def VST1d64QPseudoWB_register : VSTQQWBP<br>
<br>
// VST2 : Vector Store (multiple 2-element structures)<br>
class VST2<bits<4> op11_8, bits<4> op7_4, string Dt, RegisterOperand VdTy,<br>
- InstrItinClass itin><br>
- : NLdSt<0, 0b00, op11_8, op7_4, (outs), (ins addrmode6:$Rn, VdTy:$Vd),<br>
+ InstrItinClass itin, Operand AddrMode><br>
+ : NLdSt<0, 0b00, op11_8, op7_4, (outs), (ins AddrMode:$Rn, VdTy:$Vd),<br>
itin, "vst2", Dt, "$Vd, $Rn", "", []> {<br>
let Rm = 0b1111;<br>
let Inst{5-4} = Rn{5-4};<br>
let DecoderMethod = "DecodeVLDST2Instruction";<br>
}<br>
<br>
-def VST2d8 : VST2<0b1000, {0,0,?,?}, "8", VecListDPair, IIC_VST2>;<br>
-def VST2d16 : VST2<0b1000, {0,1,?,?}, "16", VecListDPair, IIC_VST2>;<br>
-def VST2d32 : VST2<0b1000, {1,0,?,?}, "32", VecListDPair, IIC_VST2>;<br>
-<br>
-def VST2q8 : VST2<0b0011, {0,0,?,?}, "8", VecListFourD, IIC_VST2x2>;<br>
-def VST2q16 : VST2<0b0011, {0,1,?,?}, "16", VecListFourD, IIC_VST2x2>;<br>
-def VST2q32 : VST2<0b0011, {1,0,?,?}, "32", VecListFourD, IIC_VST2x2>;<br>
+def VST2d8 : VST2<0b1000, {0,0,?,?}, "8", VecListDPair, IIC_VST2,<br>
+ addrmode6align64or128>;<br>
+def VST2d16 : VST2<0b1000, {0,1,?,?}, "16", VecListDPair, IIC_VST2,<br>
+ addrmode6align64or128>;<br>
+def VST2d32 : VST2<0b1000, {1,0,?,?}, "32", VecListDPair, IIC_VST2,<br>
+ addrmode6align64or128>;<br>
+<br>
+def VST2q8 : VST2<0b0011, {0,0,?,?}, "8", VecListFourD, IIC_VST2x2,<br>
+ addrmode6align64or128or256>;<br>
+def VST2q16 : VST2<0b0011, {0,1,?,?}, "16", VecListFourD, IIC_VST2x2,<br>
+ addrmode6align64or128or256>;<br>
+def VST2q32 : VST2<0b0011, {1,0,?,?}, "32", VecListFourD, IIC_VST2x2,<br>
+ addrmode6align64or128or256>;<br>
<br>
def VST2q8Pseudo : VSTQQPseudo<IIC_VST2x2>;<br>
def VST2q16Pseudo : VSTQQPseudo<IIC_VST2x2>;<br>
@@ -1742,9 +1789,9 @@ def VST2q32Pseudo : VSTQQPseudo<IIC_VST<br>
<br>
// ...with address register writeback:<br>
multiclass VST2DWB<bits<4> op11_8, bits<4> op7_4, string Dt,<br>
- RegisterOperand VdTy> {<br>
+ RegisterOperand VdTy, Operand AddrMode> {<br>
def _fixed : NLdSt<0, 0b00, op11_8, op7_4, (outs GPR:$wb),<br>
- (ins addrmode6:$Rn, VdTy:$Vd), IIC_VLD1u,<br>
+ (ins AddrMode:$Rn, VdTy:$Vd), IIC_VLD1u,<br>
"vst2", Dt, "$Vd, $Rn!",<br>
"$Rn.addr = $wb", []> {<br>
let Rm = 0b1101; // NLdSt will assign to the right encoding bits.<br>
@@ -1752,16 +1799,16 @@ multiclass VST2DWB<bits<4> op11_8, bits<<br>
let DecoderMethod = "DecodeVLDST2Instruction";<br>
}<br>
def _register : NLdSt<0, 0b00, op11_8, op7_4, (outs GPR:$wb),<br>
- (ins addrmode6:$Rn, rGPR:$Rm, VdTy:$Vd), IIC_VLD1u,<br>
+ (ins AddrMode:$Rn, rGPR:$Rm, VdTy:$Vd), IIC_VLD1u,<br>
"vst2", Dt, "$Vd, $Rn, $Rm",<br>
"$Rn.addr = $wb", []> {<br>
let Inst{5-4} = Rn{5-4};<br>
let DecoderMethod = "DecodeVLDST2Instruction";<br>
}<br>
}<br>
-multiclass VST2QWB<bits<4> op7_4, string Dt> {<br>
+multiclass VST2QWB<bits<4> op7_4, string Dt, Operand AddrMode> {<br>
def _fixed : NLdSt<0, 0b00, 0b0011, op7_4, (outs GPR:$wb),<br>
- (ins addrmode6:$Rn, VecListFourD:$Vd), IIC_VLD1u,<br>
+ (ins AddrMode:$Rn, VecListFourD:$Vd), IIC_VLD1u,<br>
"vst2", Dt, "$Vd, $Rn!",<br>
"$Rn.addr = $wb", []> {<br>
let Rm = 0b1101; // NLdSt will assign to the right encoding bits.<br>
@@ -1769,7 +1816,7 @@ multiclass VST2QWB<bits<4> op7_4, string<br>
let DecoderMethod = "DecodeVLDST2Instruction";<br>
}<br>
def _register : NLdSt<0, 0b00, 0b0011, op7_4, (outs GPR:$wb),<br>
- (ins addrmode6:$Rn, rGPR:$Rm, VecListFourD:$Vd),<br>
+ (ins AddrMode:$Rn, rGPR:$Rm, VecListFourD:$Vd),<br>
IIC_VLD1u,<br>
"vst2", Dt, "$Vd, $Rn, $Rm",<br>
"$Rn.addr = $wb", []> {<br>
@@ -1778,13 +1825,16 @@ multiclass VST2QWB<bits<4> op7_4, string<br>
}<br>
}<br>
<br>
-defm VST2d8wb : VST2DWB<0b1000, {0,0,?,?}, "8", VecListDPair>;<br>
-defm VST2d16wb : VST2DWB<0b1000, {0,1,?,?}, "16", VecListDPair>;<br>
-defm VST2d32wb : VST2DWB<0b1000, {1,0,?,?}, "32", VecListDPair>;<br>
-<br>
-defm VST2q8wb : VST2QWB<{0,0,?,?}, "8">;<br>
-defm VST2q16wb : VST2QWB<{0,1,?,?}, "16">;<br>
-defm VST2q32wb : VST2QWB<{1,0,?,?}, "32">;<br>
+defm VST2d8wb : VST2DWB<0b1000, {0,0,?,?}, "8", VecListDPair,<br>
+ addrmode6align64or128>;<br>
+defm VST2d16wb : VST2DWB<0b1000, {0,1,?,?}, "16", VecListDPair,<br>
+ addrmode6align64or128>;<br>
+defm VST2d32wb : VST2DWB<0b1000, {1,0,?,?}, "32", VecListDPair,<br>
+ addrmode6align64or128>;<br>
+<br>
+defm VST2q8wb : VST2QWB<{0,0,?,?}, "8", addrmode6align64or128or256>;<br>
+defm VST2q16wb : VST2QWB<{0,1,?,?}, "16", addrmode6align64or128or256>;<br>
+defm VST2q32wb : VST2QWB<{1,0,?,?}, "32", addrmode6align64or128or256>;<br>
<br>
def VST2q8PseudoWB_fixed : VSTQQWBfixedPseudo<IIC_VST2x2u>;<br>
def VST2q16PseudoWB_fixed : VSTQQWBfixedPseudo<IIC_VST2x2u>;<br>
@@ -1794,12 +1844,18 @@ def VST2q16PseudoWB_register : VSTQQWBre<br>
def VST2q32PseudoWB_register : VSTQQWBregisterPseudo<IIC_VST2x2u>;<br>
<br>
// ...with double-spaced registers<br>
-def VST2b8 : VST2<0b1001, {0,0,?,?}, "8", VecListDPairSpaced, IIC_VST2>;<br>
-def VST2b16 : VST2<0b1001, {0,1,?,?}, "16", VecListDPairSpaced, IIC_VST2>;<br>
-def VST2b32 : VST2<0b1001, {1,0,?,?}, "32", VecListDPairSpaced, IIC_VST2>;<br>
-defm VST2b8wb : VST2DWB<0b1001, {0,0,?,?}, "8", VecListDPairSpaced>;<br>
-defm VST2b16wb : VST2DWB<0b1001, {0,1,?,?}, "16", VecListDPairSpaced>;<br>
-defm VST2b32wb : VST2DWB<0b1001, {1,0,?,?}, "32", VecListDPairSpaced>;<br>
+def VST2b8 : VST2<0b1001, {0,0,?,?}, "8", VecListDPairSpaced, IIC_VST2,<br>
+ addrmode6align64or128>;<br>
+def VST2b16 : VST2<0b1001, {0,1,?,?}, "16", VecListDPairSpaced, IIC_VST2,<br>
+ addrmode6align64or128>;<br>
+def VST2b32 : VST2<0b1001, {1,0,?,?}, "32", VecListDPairSpaced, IIC_VST2,<br>
+ addrmode6align64or128>;<br>
+defm VST2b8wb : VST2DWB<0b1001, {0,0,?,?}, "8", VecListDPairSpaced,<br>
+ addrmode6align64or128>;<br>
+defm VST2b16wb : VST2DWB<0b1001, {0,1,?,?}, "16", VecListDPairSpaced,<br>
+ addrmode6align64or128>;<br>
+defm VST2b32wb : VST2DWB<0b1001, {1,0,?,?}, "32", VecListDPairSpaced,<br>
+ addrmode6align64or128>;<br>
<br>
// VST3 : Vector Store (multiple 3-element structures)<br>
class VST3D<bits<4> op11_8, bits<4> op7_4, string Dt><br>
@@ -6311,379 +6367,442 @@ defm : NEONDTAnyInstAlias<"vorr${p}", "$<br>
// VLD1 single-lane pseudo-instructions. These need special handling for<br>
// the lane index that an InstAlias can't handle, so we use these instead.<br>
def VLD1LNdAsm_8 : NEONDataTypeAsmPseudoInst<"vld1${p}", ".8", "$list, $addr",<br>
- (ins VecListOneDByteIndexed:$list, addrmode6:$addr, pred:$p)>;<br>
+ (ins VecListOneDByteIndexed:$list, addrmode6alignNone:$addr,<br>
+ pred:$p)>;<br>
def VLD1LNdAsm_16 : NEONDataTypeAsmPseudoInst<"vld1${p}", ".16", "$list, $addr",<br>
- (ins VecListOneDHWordIndexed:$list, addrmode6:$addr, pred:$p)>;<br>
+ (ins VecListOneDHWordIndexed:$list, addrmode6align16:$addr,<br>
+ pred:$p)>;<br>
def VLD1LNdAsm_32 : NEONDataTypeAsmPseudoInst<"vld1${p}", ".32", "$list, $addr",<br>
- (ins VecListOneDWordIndexed:$list, addrmode6:$addr, pred:$p)>;<br>
+ (ins VecListOneDWordIndexed:$list, addrmode6align32:$addr,<br>
+ pred:$p)>;<br>
<br>
def VLD1LNdWB_fixed_Asm_8 :<br>
NEONDataTypeAsmPseudoInst<"vld1${p}", ".8", "$list, $addr!",<br>
- (ins VecListOneDByteIndexed:$list, addrmode6:$addr, pred:$p)>;<br>
+ (ins VecListOneDByteIndexed:$list, addrmode6alignNone:$addr,<br>
+ pred:$p)>;<br>
def VLD1LNdWB_fixed_Asm_16 :<br>
NEONDataTypeAsmPseudoInst<"vld1${p}", ".16", "$list, $addr!",<br>
- (ins VecListOneDHWordIndexed:$list, addrmode6:$addr, pred:$p)>;<br>
+ (ins VecListOneDHWordIndexed:$list, addrmode6align16:$addr,<br>
+ pred:$p)>;<br>
def VLD1LNdWB_fixed_Asm_32 :<br>
NEONDataTypeAsmPseudoInst<"vld1${p}", ".32", "$list, $addr!",<br>
- (ins VecListOneDWordIndexed:$list, addrmode6:$addr, pred:$p)>;<br>
+ (ins VecListOneDWordIndexed:$list, addrmode6align32:$addr,<br>
+ pred:$p)>;<br>
def VLD1LNdWB_register_Asm_8 :<br>
NEONDataTypeAsmPseudoInst<"vld1${p}", ".8", "$list, $addr, $Rm",<br>
- (ins VecListOneDByteIndexed:$list, addrmode6:$addr,<br>
+ (ins VecListOneDByteIndexed:$list, addrmode6alignNone:$addr,<br>
rGPR:$Rm, pred:$p)>;<br>
def VLD1LNdWB_register_Asm_16 :<br>
NEONDataTypeAsmPseudoInst<"vld1${p}", ".16", "$list, $addr, $Rm",<br>
- (ins VecListOneDHWordIndexed:$list, addrmode6:$addr,<br>
+ (ins VecListOneDHWordIndexed:$list, addrmode6align16:$addr,<br>
rGPR:$Rm, pred:$p)>;<br>
def VLD1LNdWB_register_Asm_32 :<br>
NEONDataTypeAsmPseudoInst<"vld1${p}", ".32", "$list, $addr, $Rm",<br>
- (ins VecListOneDWordIndexed:$list, addrmode6:$addr,<br>
+ (ins VecListOneDWordIndexed:$list, addrmode6align32:$addr,<br>
rGPR:$Rm, pred:$p)>;<br>
<br>
<br>
// VST1 single-lane pseudo-instructions. These need special handling for<br>
// the lane index that an InstAlias can't handle, so we use these instead.<br>
def VST1LNdAsm_8 : NEONDataTypeAsmPseudoInst<"vst1${p}", ".8", "$list, $addr",<br>
- (ins VecListOneDByteIndexed:$list, addrmode6:$addr, pred:$p)>;<br>
+ (ins VecListOneDByteIndexed:$list, addrmode6alignNone:$addr,<br>
+ pred:$p)>;<br>
def VST1LNdAsm_16 : NEONDataTypeAsmPseudoInst<"vst1${p}", ".16", "$list, $addr",<br>
- (ins VecListOneDHWordIndexed:$list, addrmode6:$addr, pred:$p)>;<br>
+ (ins VecListOneDHWordIndexed:$list, addrmode6align16:$addr,<br>
+ pred:$p)>;<br>
def VST1LNdAsm_32 : NEONDataTypeAsmPseudoInst<"vst1${p}", ".32", "$list, $addr",<br>
- (ins VecListOneDWordIndexed:$list, addrmode6:$addr, pred:$p)>;<br>
+ (ins VecListOneDWordIndexed:$list, addrmode6align32:$addr,<br>
+ pred:$p)>;<br>
<br>
def VST1LNdWB_fixed_Asm_8 :<br>
NEONDataTypeAsmPseudoInst<"vst1${p}", ".8", "$list, $addr!",<br>
- (ins VecListOneDByteIndexed:$list, addrmode6:$addr, pred:$p)>;<br>
+ (ins VecListOneDByteIndexed:$list, addrmode6alignNone:$addr,<br>
+ pred:$p)>;<br>
def VST1LNdWB_fixed_Asm_16 :<br>
NEONDataTypeAsmPseudoInst<"vst1${p}", ".16", "$list, $addr!",<br>
- (ins VecListOneDHWordIndexed:$list, addrmode6:$addr, pred:$p)>;<br>
+ (ins VecListOneDHWordIndexed:$list, addrmode6align16:$addr,<br>
+ pred:$p)>;<br>
def VST1LNdWB_fixed_Asm_32 :<br>
NEONDataTypeAsmPseudoInst<"vst1${p}", ".32", "$list, $addr!",<br>
- (ins VecListOneDWordIndexed:$list, addrmode6:$addr, pred:$p)>;<br>
+ (ins VecListOneDWordIndexed:$list, addrmode6align32:$addr,<br>
+ pred:$p)>;<br>
def VST1LNdWB_register_Asm_8 :<br>
NEONDataTypeAsmPseudoInst<"vst1${p}", ".8", "$list, $addr, $Rm",<br>
- (ins VecListOneDByteIndexed:$list, addrmode6:$addr,<br>
+ (ins VecListOneDByteIndexed:$list, addrmode6alignNone:$addr,<br>
rGPR:$Rm, pred:$p)>;<br>
def VST1LNdWB_register_Asm_16 :<br>
NEONDataTypeAsmPseudoInst<"vst1${p}", ".16", "$list, $addr, $Rm",<br>
- (ins VecListOneDHWordIndexed:$list, addrmode6:$addr,<br>
+ (ins VecListOneDHWordIndexed:$list, addrmode6align16:$addr,<br>
rGPR:$Rm, pred:$p)>;<br>
def VST1LNdWB_register_Asm_32 :<br>
NEONDataTypeAsmPseudoInst<"vst1${p}", ".32", "$list, $addr, $Rm",<br>
- (ins VecListOneDWordIndexed:$list, addrmode6:$addr,<br>
+ (ins VecListOneDWordIndexed:$list, addrmode6align32:$addr,<br>
rGPR:$Rm, pred:$p)>;<br>
<br>
// VLD2 single-lane pseudo-instructions. These need special handling for<br>
// the lane index that an InstAlias can't handle, so we use these instead.<br>
def VLD2LNdAsm_8 : NEONDataTypeAsmPseudoInst<"vld2${p}", ".8", "$list, $addr",<br>
- (ins VecListTwoDByteIndexed:$list, addrmode6:$addr, pred:$p)>;<br>
+ (ins VecListTwoDByteIndexed:$list, addrmode6align16:$addr,<br>
+ pred:$p)>;<br>
def VLD2LNdAsm_16 : NEONDataTypeAsmPseudoInst<"vld2${p}", ".16", "$list, $addr",<br>
- (ins VecListTwoDHWordIndexed:$list, addrmode6:$addr, pred:$p)>;<br>
+ (ins VecListTwoDHWordIndexed:$list, addrmode6align32:$addr,<br>
+ pred:$p)>;<br>
def VLD2LNdAsm_32 : NEONDataTypeAsmPseudoInst<"vld2${p}", ".32", "$list, $addr",<br>
- (ins VecListTwoDWordIndexed:$list, addrmode6:$addr, pred:$p)>;<br>
+ (ins VecListTwoDWordIndexed:$list, addrmode6align64:$addr, pred:$p)>;<br>
def VLD2LNqAsm_16 : NEONDataTypeAsmPseudoInst<"vld2${p}", ".16", "$list, $addr",<br>
- (ins VecListTwoQHWordIndexed:$list, addrmode6:$addr, pred:$p)>;<br>
+ (ins VecListTwoQHWordIndexed:$list, addrmode6align32:$addr,<br>
+ pred:$p)>;<br>
def VLD2LNqAsm_32 : NEONDataTypeAsmPseudoInst<"vld2${p}", ".32", "$list, $addr",<br>
- (ins VecListTwoQWordIndexed:$list, addrmode6:$addr, pred:$p)>;<br>
+ (ins VecListTwoQWordIndexed:$list, addrmode6align64:$addr,<br>
+ pred:$p)>;<br>
<br>
def VLD2LNdWB_fixed_Asm_8 :<br>
NEONDataTypeAsmPseudoInst<"vld2${p}", ".8", "$list, $addr!",<br>
- (ins VecListTwoDByteIndexed:$list, addrmode6:$addr, pred:$p)>;<br>
+ (ins VecListTwoDByteIndexed:$list, addrmode6align16:$addr,<br>
+ pred:$p)>;<br>
def VLD2LNdWB_fixed_Asm_16 :<br>
NEONDataTypeAsmPseudoInst<"vld2${p}", ".16", "$list, $addr!",<br>
- (ins VecListTwoDHWordIndexed:$list, addrmode6:$addr, pred:$p)>;<br>
+ (ins VecListTwoDHWordIndexed:$list, addrmode6align32:$addr,<br>
+ pred:$p)>;<br>
def VLD2LNdWB_fixed_Asm_32 :<br>
NEONDataTypeAsmPseudoInst<"vld2${p}", ".32", "$list, $addr!",<br>
- (ins VecListTwoDWordIndexed:$list, addrmode6:$addr, pred:$p)>;<br>
+ (ins VecListTwoDWordIndexed:$list, addrmode6align64:$addr,<br>
+ pred:$p)>;<br>
def VLD2LNqWB_fixed_Asm_16 :<br>
NEONDataTypeAsmPseudoInst<"vld2${p}", ".16", "$list, $addr!",<br>
- (ins VecListTwoQHWordIndexed:$list, addrmode6:$addr, pred:$p)>;<br>
+ (ins VecListTwoQHWordIndexed:$list, addrmode6align32:$addr,<br>
+ pred:$p)>;<br>
def VLD2LNqWB_fixed_Asm_32 :<br>
NEONDataTypeAsmPseudoInst<"vld2${p}", ".32", "$list, $addr!",<br>
- (ins VecListTwoQWordIndexed:$list, addrmode6:$addr, pred:$p)>;<br>
+ (ins VecListTwoQWordIndexed:$list, addrmode6align64:$addr,<br>
+ pred:$p)>;<br>
def VLD2LNdWB_register_Asm_8 :<br>
NEONDataTypeAsmPseudoInst<"vld2${p}", ".8", "$list, $addr, $Rm",<br>
- (ins VecListTwoDByteIndexed:$list, addrmode6:$addr,<br>
+ (ins VecListTwoDByteIndexed:$list, addrmode6align16:$addr,<br>
rGPR:$Rm, pred:$p)>;<br>
def VLD2LNdWB_register_Asm_16 :<br>
NEONDataTypeAsmPseudoInst<"vld2${p}", ".16", "$list, $addr, $Rm",<br>
- (ins VecListTwoDHWordIndexed:$list, addrmode6:$addr,<br>
+ (ins VecListTwoDHWordIndexed:$list, addrmode6align32:$addr,<br>
rGPR:$Rm, pred:$p)>;<br>
def VLD2LNdWB_register_Asm_32 :<br>
NEONDataTypeAsmPseudoInst<"vld2${p}", ".32", "$list, $addr, $Rm",<br>
- (ins VecListTwoDWordIndexed:$list, addrmode6:$addr,<br>
+ (ins VecListTwoDWordIndexed:$list, addrmode6align64:$addr,<br>
rGPR:$Rm, pred:$p)>;<br>
def VLD2LNqWB_register_Asm_16 :<br>
NEONDataTypeAsmPseudoInst<"vld2${p}", ".16", "$list, $addr, $Rm",<br>
- (ins VecListTwoQHWordIndexed:$list, addrmode6:$addr,<br>
+ (ins VecListTwoQHWordIndexed:$list, addrmode6align32:$addr,<br>
rGPR:$Rm, pred:$p)>;<br>
def VLD2LNqWB_register_Asm_32 :<br>
NEONDataTypeAsmPseudoInst<"vld2${p}", ".32", "$list, $addr, $Rm",<br>
- (ins VecListTwoQWordIndexed:$list, addrmode6:$addr,<br>
+ (ins VecListTwoQWordIndexed:$list, addrmode6align64:$addr,<br>
rGPR:$Rm, pred:$p)>;<br>
<br>
<br>
// VST2 single-lane pseudo-instructions. These need special handling for<br>
// the lane index that an InstAlias can't handle, so we use these instead.<br>
def VST2LNdAsm_8 : NEONDataTypeAsmPseudoInst<"vst2${p}", ".8", "$list, $addr",<br>
- (ins VecListTwoDByteIndexed:$list, addrmode6:$addr, pred:$p)>;<br>
+ (ins VecListTwoDByteIndexed:$list, addrmode6align16:$addr,<br>
+ pred:$p)>;<br>
def VST2LNdAsm_16 : NEONDataTypeAsmPseudoInst<"vst2${p}", ".16", "$list, $addr",<br>
- (ins VecListTwoDHWordIndexed:$list, addrmode6:$addr, pred:$p)>;<br>
+ (ins VecListTwoDHWordIndexed:$list, addrmode6align32:$addr,<br>
+ pred:$p)>;<br>
def VST2LNdAsm_32 : NEONDataTypeAsmPseudoInst<"vst2${p}", ".32", "$list, $addr",<br>
- (ins VecListTwoDWordIndexed:$list, addrmode6:$addr, pred:$p)>;<br>
+ (ins VecListTwoDWordIndexed:$list, addrmode6align64:$addr,<br>
+ pred:$p)>;<br>
def VST2LNqAsm_16 : NEONDataTypeAsmPseudoInst<"vst2${p}", ".16", "$list, $addr",<br>
- (ins VecListTwoQHWordIndexed:$list, addrmode6:$addr, pred:$p)>;<br>
+ (ins VecListTwoQHWordIndexed:$list, addrmode6align32:$addr,<br>
+ pred:$p)>;<br>
def VST2LNqAsm_32 : NEONDataTypeAsmPseudoInst<"vst2${p}", ".32", "$list, $addr",<br>
- (ins VecListTwoQWordIndexed:$list, addrmode6:$addr, pred:$p)>;<br>
+ (ins VecListTwoQWordIndexed:$list, addrmode6align64:$addr,<br>
+ pred:$p)>;<br>
<br>
def VST2LNdWB_fixed_Asm_8 :<br>
NEONDataTypeAsmPseudoInst<"vst2${p}", ".8", "$list, $addr!",<br>
- (ins VecListTwoDByteIndexed:$list, addrmode6:$addr, pred:$p)>;<br>
+ (ins VecListTwoDByteIndexed:$list, addrmode6align16:$addr,<br>
+ pred:$p)>;<br>
def VST2LNdWB_fixed_Asm_16 :<br>
NEONDataTypeAsmPseudoInst<"vst2${p}", ".16", "$list, $addr!",<br>
- (ins VecListTwoDHWordIndexed:$list, addrmode6:$addr, pred:$p)>;<br>
+ (ins VecListTwoDHWordIndexed:$list, addrmode6align32:$addr,<br>
+ pred:$p)>;<br>
def VST2LNdWB_fixed_Asm_32 :<br>
NEONDataTypeAsmPseudoInst<"vst2${p}", ".32", "$list, $addr!",<br>
- (ins VecListTwoDWordIndexed:$list, addrmode6:$addr, pred:$p)>;<br>
+ (ins VecListTwoDWordIndexed:$list, addrmode6align64:$addr,<br>
+ pred:$p)>;<br>
def VST2LNqWB_fixed_Asm_16 :<br>
NEONDataTypeAsmPseudoInst<"vst2${p}", ".16", "$list, $addr!",<br>
- (ins VecListTwoQHWordIndexed:$list, addrmode6:$addr, pred:$p)>;<br>
+ (ins VecListTwoQHWordIndexed:$list, addrmode6align32:$addr,<br>
+ pred:$p)>;<br>
def VST2LNqWB_fixed_Asm_32 :<br>
NEONDataTypeAsmPseudoInst<"vst2${p}", ".32", "$list, $addr!",<br>
- (ins VecListTwoQWordIndexed:$list, addrmode6:$addr, pred:$p)>;<br>
+ (ins VecListTwoQWordIndexed:$list, addrmode6align64:$addr,<br>
+ pred:$p)>;<br>
def VST2LNdWB_register_Asm_8 :<br>
NEONDataTypeAsmPseudoInst<"vst2${p}", ".8", "$list, $addr, $Rm",<br>
- (ins VecListTwoDByteIndexed:$list, addrmode6:$addr,<br>
+ (ins VecListTwoDByteIndexed:$list, addrmode6align16:$addr,<br>
rGPR:$Rm, pred:$p)>;<br>
def VST2LNdWB_register_Asm_16 :<br>
NEONDataTypeAsmPseudoInst<"vst2${p}", ".16","$list, $addr, $Rm",<br>
- (ins VecListTwoDHWordIndexed:$list, addrmode6:$addr,<br>
+ (ins VecListTwoDHWordIndexed:$list, addrmode6align32:$addr,<br>
rGPR:$Rm, pred:$p)>;<br>
def VST2LNdWB_register_Asm_32 :<br>
NEONDataTypeAsmPseudoInst<"vst2${p}", ".32", "$list, $addr, $Rm",<br>
- (ins VecListTwoDWordIndexed:$list, addrmode6:$addr,<br>
+ (ins VecListTwoDWordIndexed:$list, addrmode6align64:$addr,<br>
rGPR:$Rm, pred:$p)>;<br>
def VST2LNqWB_register_Asm_16 :<br>
NEONDataTypeAsmPseudoInst<"vst2${p}", ".16","$list, $addr, $Rm",<br>
- (ins VecListTwoQHWordIndexed:$list, addrmode6:$addr,<br>
+ (ins VecListTwoQHWordIndexed:$list, addrmode6align32:$addr,<br>
rGPR:$Rm, pred:$p)>;<br>
def VST2LNqWB_register_Asm_32 :<br>
NEONDataTypeAsmPseudoInst<"vst2${p}", ".32", "$list, $addr, $Rm",<br>
- (ins VecListTwoQWordIndexed:$list, addrmode6:$addr,<br>
+ (ins VecListTwoQWordIndexed:$list, addrmode6align64:$addr,<br>
rGPR:$Rm, pred:$p)>;<br>
<br>
// VLD3 all-lanes pseudo-instructions. These need special handling for<br>
// the lane index that an InstAlias can't handle, so we use these instead.<br>
def VLD3DUPdAsm_8 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr",<br>
- (ins VecListThreeDAllLanes:$list, addrmode6:$addr, pred:$p)>;<br>
+ (ins VecListThreeDAllLanes:$list, addrmode6dupalignNone:$addr,<br>
+ pred:$p)>;<br>
def VLD3DUPdAsm_16: NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr",<br>
- (ins VecListThreeDAllLanes:$list, addrmode6:$addr, pred:$p)>;<br>
+ (ins VecListThreeDAllLanes:$list, addrmode6dupalignNone:$addr,<br>
+ pred:$p)>;<br>
def VLD3DUPdAsm_32: NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr",<br>
- (ins VecListThreeDAllLanes:$list, addrmode6:$addr, pred:$p)>;<br>
+ (ins VecListThreeDAllLanes:$list, addrmode6dupalignNone:$addr,<br>
+ pred:$p)>;<br>
def VLD3DUPqAsm_8 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr",<br>
- (ins VecListThreeQAllLanes:$list, addrmode6:$addr, pred:$p)>;<br>
+ (ins VecListThreeQAllLanes:$list, addrmode6dupalignNone:$addr,<br>
+ pred:$p)>;<br>
def VLD3DUPqAsm_16: NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr",<br>
- (ins VecListThreeQAllLanes:$list, addrmode6:$addr, pred:$p)>;<br>
+ (ins VecListThreeQAllLanes:$list, addrmode6dupalignNone:$addr,<br>
+ pred:$p)>;<br>
def VLD3DUPqAsm_32: NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr",<br>
- (ins VecListThreeQAllLanes:$list, addrmode6:$addr, pred:$p)>;<br>
+ (ins VecListThreeQAllLanes:$list, addrmode6dupalignNone:$addr,<br>
+ pred:$p)>;<br>
<br>
def VLD3DUPdWB_fixed_Asm_8 :<br>
NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr!",<br>
- (ins VecListThreeDAllLanes:$list, addrmode6:$addr, pred:$p)>;<br>
+ (ins VecListThreeDAllLanes:$list, addrmode6dupalignNone:$addr,<br>
+ pred:$p)>;<br>
def VLD3DUPdWB_fixed_Asm_16 :<br>
NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr!",<br>
- (ins VecListThreeDAllLanes:$list, addrmode6:$addr, pred:$p)>;<br>
+ (ins VecListThreeDAllLanes:$list, addrmode6dupalignNone:$addr,<br>
+ pred:$p)>;<br>
def VLD3DUPdWB_fixed_Asm_32 :<br>
NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr!",<br>
- (ins VecListThreeDAllLanes:$list, addrmode6:$addr, pred:$p)>;<br>
+ (ins VecListThreeDAllLanes:$list, addrmode6dupalignNone:$addr,<br>
+ pred:$p)>;<br>
def VLD3DUPqWB_fixed_Asm_8 :<br>
NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr!",<br>
- (ins VecListThreeQAllLanes:$list, addrmode6:$addr, pred:$p)>;<br>
+ (ins VecListThreeQAllLanes:$list, addrmode6dupalignNone:$addr,<br>
+ pred:$p)>;<br>
def VLD3DUPqWB_fixed_Asm_16 :<br>
NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr!",<br>
- (ins VecListThreeQAllLanes:$list, addrmode6:$addr, pred:$p)>;<br>
+ (ins VecListThreeQAllLanes:$list, addrmode6dupalignNone:$addr,<br>
+ pred:$p)>;<br>
def VLD3DUPqWB_fixed_Asm_32 :<br>
NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr!",<br>
- (ins VecListThreeQAllLanes:$list, addrmode6:$addr, pred:$p)>;<br>
+ (ins VecListThreeQAllLanes:$list, addrmode6dupalignNone:$addr,<br>
+ pred:$p)>;<br>
def VLD3DUPdWB_register_Asm_8 :<br>
NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr, $Rm",<br>
- (ins VecListThreeDAllLanes:$list, addrmode6:$addr,<br>
+ (ins VecListThreeDAllLanes:$list, addrmode6dupalignNone:$addr,<br>
rGPR:$Rm, pred:$p)>;<br>
def VLD3DUPdWB_register_Asm_16 :<br>
NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr, $Rm",<br>
- (ins VecListThreeDAllLanes:$list, addrmode6:$addr,<br>
+ (ins VecListThreeDAllLanes:$list, addrmode6dupalignNone:$addr,<br>
rGPR:$Rm, pred:$p)>;<br>
def VLD3DUPdWB_register_Asm_32 :<br>
NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr, $Rm",<br>
- (ins VecListThreeDAllLanes:$list, addrmode6:$addr,<br>
+ (ins VecListThreeDAllLanes:$list, addrmode6dupalignNone:$addr,<br>
rGPR:$Rm, pred:$p)>;<br>
def VLD3DUPqWB_register_Asm_8 :<br>
NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr, $Rm",<br>
- (ins VecListThreeQAllLanes:$list, addrmode6:$addr,<br>
+ (ins VecListThreeQAllLanes:$list, addrmode6dupalignNone:$addr,<br>
rGPR:$Rm, pred:$p)>;<br>
def VLD3DUPqWB_register_Asm_16 :<br>
NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr, $Rm",<br>
- (ins VecListThreeQAllLanes:$list, addrmode6:$addr,<br>
+ (ins VecListThreeQAllLanes:$list, addrmode6dupalignNone:$addr,<br>
rGPR:$Rm, pred:$p)>;<br>
def VLD3DUPqWB_register_Asm_32 :<br>
NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr, $Rm",<br>
- (ins VecListThreeQAllLanes:$list, addrmode6:$addr,<br>
+ (ins VecListThreeQAllLanes:$list, addrmode6dupalignNone:$addr,<br>
rGPR:$Rm, pred:$p)>;<br>
<br>
<br>
// VLD3 single-lane pseudo-instructions. These need special handling for<br>
// the lane index that an InstAlias can't handle, so we use these instead.<br>
def VLD3LNdAsm_8 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr",<br>
- (ins VecListThreeDByteIndexed:$list, addrmode6:$addr, pred:$p)>;<br>
+ (ins VecListThreeDByteIndexed:$list, addrmode6alignNone:$addr,<br>
+ pred:$p)>;<br>
def VLD3LNdAsm_16 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr",<br>
- (ins VecListThreeDHWordIndexed:$list, addrmode6:$addr, pred:$p)>;<br>
+ (ins VecListThreeDHWordIndexed:$list, addrmode6alignNone:$addr,<br>
+ pred:$p)>;<br>
def VLD3LNdAsm_32 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr",<br>
- (ins VecListThreeDWordIndexed:$list, addrmode6:$addr, pred:$p)>;<br>
+ (ins VecListThreeDWordIndexed:$list, addrmode6alignNone:$addr,<br>
+ pred:$p)>;<br>
def VLD3LNqAsm_16 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr",<br>
- (ins VecListThreeQHWordIndexed:$list, addrmode6:$addr, pred:$p)>;<br>
+ (ins VecListThreeQHWordIndexed:$list, addrmode6alignNone:$addr,<br>
+ pred:$p)>;<br>
def VLD3LNqAsm_32 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr",<br>
- (ins VecListThreeQWordIndexed:$list, addrmode6:$addr, pred:$p)>;<br>
+ (ins VecListThreeQWordIndexed:$list, addrmode6alignNone:$addr,<br>
+ pred:$p)>;<br>
<br>
def VLD3LNdWB_fixed_Asm_8 :<br>
NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr!",<br>
- (ins VecListThreeDByteIndexed:$list, addrmode6:$addr, pred:$p)>;<br>
+ (ins VecListThreeDByteIndexed:$list, addrmode6alignNone:$addr,<br>
+ pred:$p)>;<br>
def VLD3LNdWB_fixed_Asm_16 :<br>
NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr!",<br>
- (ins VecListThreeDHWordIndexed:$list, addrmode6:$addr, pred:$p)>;<br>
+ (ins VecListThreeDHWordIndexed:$list, addrmode6alignNone:$addr,<br>
+ pred:$p)>;<br>
def VLD3LNdWB_fixed_Asm_32 :<br>
NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr!",<br>
- (ins VecListThreeDWordIndexed:$list, addrmode6:$addr, pred:$p)>;<br>
+ (ins VecListThreeDWordIndexed:$list, addrmode6alignNone:$addr,<br>
+ pred:$p)>;<br>
def VLD3LNqWB_fixed_Asm_16 :<br>
NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr!",<br>
- (ins VecListThreeQHWordIndexed:$list, addrmode6:$addr, pred:$p)>;<br>
+ (ins VecListThreeQHWordIndexed:$list, addrmode6alignNone:$addr,<br>
+ pred:$p)>;<br>
def VLD3LNqWB_fixed_Asm_32 :<br>
NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr!",<br>
- (ins VecListThreeQWordIndexed:$list, addrmode6:$addr, pred:$p)>;<br>
+ (ins VecListThreeQWordIndexed:$list, addrmode6alignNone:$addr,<br>
+ pred:$p)>;<br>
def VLD3LNdWB_register_Asm_8 :<br>
NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr, $Rm",<br>
- (ins VecListThreeDByteIndexed:$list, addrmode6:$addr,<br>
+ (ins VecListThreeDByteIndexed:$list, addrmode6alignNone:$addr,<br>
rGPR:$Rm, pred:$p)>;<br>
def VLD3LNdWB_register_Asm_16 :<br>
NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr, $Rm",<br>
- (ins VecListThreeDHWordIndexed:$list, addrmode6:$addr,<br>
- rGPR:$Rm, pred:$p)>;<br>
+ (ins VecListThreeDHWordIndexed:$list,<br>
+ addrmode6alignNone:$addr, rGPR:$Rm, pred:$p)>;<br>
def VLD3LNdWB_register_Asm_32 :<br>
NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr, $Rm",<br>
- (ins VecListThreeDWordIndexed:$list, addrmode6:$addr,<br>
+ (ins VecListThreeDWordIndexed:$list, addrmode6alignNone:$addr,<br>
rGPR:$Rm, pred:$p)>;<br>
def VLD3LNqWB_register_Asm_16 :<br>
NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr, $Rm",<br>
- (ins VecListThreeQHWordIndexed:$list, addrmode6:$addr,<br>
- rGPR:$Rm, pred:$p)>;<br>
+ (ins VecListThreeQHWordIndexed:$list,<br>
+ addrmode6alignNone:$addr, rGPR:$Rm, pred:$p)>;<br>
def VLD3LNqWB_register_Asm_32 :<br>
NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr, $Rm",<br>
- (ins VecListThreeQWordIndexed:$list, addrmode6:$addr,<br>
+ (ins VecListThreeQWordIndexed:$list, addrmode6alignNone:$addr,<br>
rGPR:$Rm, pred:$p)>;<br>
<br>
// VLD3 multiple structure pseudo-instructions. These need special handling for<br>
// the vector operands that the normal instructions don't yet model.<br>
// FIXME: Remove these when the register classes and instructions are updated.<br>
def VLD3dAsm_8 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr",<br>
- (ins VecListThreeD:$list, addrmode6:$addr, pred:$p)>;<br>
+ (ins VecListThreeD:$list, addrmode6align64:$addr, pred:$p)>;<br>
def VLD3dAsm_16 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr",<br>
- (ins VecListThreeD:$list, addrmode6:$addr, pred:$p)>;<br>
+ (ins VecListThreeD:$list, addrmode6align64:$addr, pred:$p)>;<br>
def VLD3dAsm_32 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr",<br>
- (ins VecListThreeD:$list, addrmode6:$addr, pred:$p)>;<br>
+ (ins VecListThreeD:$list, addrmode6align64:$addr, pred:$p)>;<br>
def VLD3qAsm_8 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr",<br>
- (ins VecListThreeQ:$list, addrmode6:$addr, pred:$p)>;<br>
+ (ins VecListThreeQ:$list, addrmode6align64:$addr, pred:$p)>;<br>
def VLD3qAsm_16 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr",<br>
- (ins VecListThreeQ:$list, addrmode6:$addr, pred:$p)>;<br>
+ (ins VecListThreeQ:$list, addrmode6align64:$addr, pred:$p)>;<br>
def VLD3qAsm_32 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr",<br>
- (ins VecListThreeQ:$list, addrmode6:$addr, pred:$p)>;<br>
+ (ins VecListThreeQ:$list, addrmode6align64:$addr, pred:$p)>;<br>
<br>
def VLD3dWB_fixed_Asm_8 :<br>
NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr!",<br>
- (ins VecListThreeD:$list, addrmode6:$addr, pred:$p)>;<br>
+ (ins VecListThreeD:$list, addrmode6align64:$addr, pred:$p)>;<br>
def VLD3dWB_fixed_Asm_16 :<br>
NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr!",<br>
- (ins VecListThreeD:$list, addrmode6:$addr, pred:$p)>;<br>
+ (ins VecListThreeD:$list, addrmode6align64:$addr, pred:$p)>;<br>
def VLD3dWB_fixed_Asm_32 :<br>
NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr!",<br>
- (ins VecListThreeD:$list, addrmode6:$addr, pred:$p)>;<br>
+ (ins VecListThreeD:$list, addrmode6align64:$addr, pred:$p)>;<br>
def VLD3qWB_fixed_Asm_8 :<br>
NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr!",<br>
- (ins VecListThreeQ:$list, addrmode6:$addr, pred:$p)>;<br>
+ (ins VecListThreeQ:$list, addrmode6align64:$addr, pred:$p)>;<br>
def VLD3qWB_fixed_Asm_16 :<br>
NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr!",<br>
- (ins VecListThreeQ:$list, addrmode6:$addr, pred:$p)>;<br>
+ (ins VecListThreeQ:$list, addrmode6align64:$addr, pred:$p)>;<br>
def VLD3qWB_fixed_Asm_32 :<br>
NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr!",<br>
- (ins VecListThreeQ:$list, addrmode6:$addr, pred:$p)>;<br>
+ (ins VecListThreeQ:$list, addrmode6align64:$addr, pred:$p)>;<br>
def VLD3dWB_register_Asm_8 :<br>
NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr, $Rm",<br>
- (ins VecListThreeD:$list, addrmode6:$addr,<br>
+ (ins VecListThreeD:$list, addrmode6align64:$addr,<br>
rGPR:$Rm, pred:$p)>;<br>
def VLD3dWB_register_Asm_16 :<br>
NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr, $Rm",<br>
- (ins VecListThreeD:$list, addrmode6:$addr,<br>
+ (ins VecListThreeD:$list, addrmode6align64:$addr,<br>
rGPR:$Rm, pred:$p)>;<br>
def VLD3dWB_register_Asm_32 :<br>
NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr, $Rm",<br>
- (ins VecListThreeD:$list, addrmode6:$addr,<br>
+ (ins VecListThreeD:$list, addrmode6align64:$addr,<br>
rGPR:$Rm, pred:$p)>;<br>
def VLD3qWB_register_Asm_8 :<br>
NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr, $Rm",<br>
- (ins VecListThreeQ:$list, addrmode6:$addr,<br>
+ (ins VecListThreeQ:$list, addrmode6align64:$addr,<br>
rGPR:$Rm, pred:$p)>;<br>
def VLD3qWB_register_Asm_16 :<br>
NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr, $Rm",<br>
- (ins VecListThreeQ:$list, addrmode6:$addr,<br>
+ (ins VecListThreeQ:$list, addrmode6align64:$addr,<br>
rGPR:$Rm, pred:$p)>;<br>
def VLD3qWB_register_Asm_32 :<br>
NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr, $Rm",<br>
- (ins VecListThreeQ:$list, addrmode6:$addr,<br>
+ (ins VecListThreeQ:$list, addrmode6align64:$addr,<br>
rGPR:$Rm, pred:$p)>;<br>
<br>
// VST3 single-lane pseudo-instructions. These need special handling for<br>
// the lane index that an InstAlias can't handle, so we use these instead.<br>
def VST3LNdAsm_8 : NEONDataTypeAsmPseudoInst<"vst3${p}", ".8", "$list, $addr",<br>
- (ins VecListThreeDByteIndexed:$list, addrmode6:$addr, pred:$p)>;<br>
+ (ins VecListThreeDByteIndexed:$list, addrmode6alignNone:$addr,<br>
+ pred:$p)>;<br>
def VST3LNdAsm_16 : NEONDataTypeAsmPseudoInst<"vst3${p}", ".16", "$list, $addr",<br>
- (ins VecListThreeDHWordIndexed:$list, addrmode6:$addr, pred:$p)>;<br>
+ (ins VecListThreeDHWordIndexed:$list, addrmode6alignNone:$addr,<br>
+ pred:$p)>;<br>
def VST3LNdAsm_32 : NEONDataTypeAsmPseudoInst<"vst3${p}", ".32", "$list, $addr",<br>
- (ins VecListThreeDWordIndexed:$list, addrmode6:$addr, pred:$p)>;<br>
+ (ins VecListThreeDWordIndexed:$list, addrmode6alignNone:$addr,<br>
+ pred:$p)>;<br>
def VST3LNqAsm_16 : NEONDataTypeAsmPseudoInst<"vst3${p}", ".16", "$list, $addr",<br>
- (ins VecListThreeQHWordIndexed:$list, addrmode6:$addr, pred:$p)>;<br>
+ (ins VecListThreeQHWordIndexed:$list, addrmode6alignNone:$addr,<br>
+ pred:$p)>;<br>
def VST3LNqAsm_32 : NEONDataTypeAsmPseudoInst<"vst3${p}", ".32", "$list, $addr",<br>
- (ins VecListThreeQWordIndexed:$list, addrmode6:$addr, pred:$p)>;<br>
+ (ins VecListThreeQWordIndexed:$list, addrmode6alignNone:$addr,<br>
+ pred:$p)>;<br>
<br>
def VST3LNdWB_fixed_Asm_8 :<br>
NEONDataTypeAsmPseudoInst<"vst3${p}", ".8", "$list, $addr!",<br>
- (ins VecListThreeDByteIndexed:$list, addrmode6:$addr, pred:$p)>;<br>
+ (ins VecListThreeDByteIndexed:$list, addrmode6alignNone:$addr,<br>
+ pred:$p)>;<br>
def VST3LNdWB_fixed_Asm_16 :<br>
NEONDataTypeAsmPseudoInst<"vst3${p}", ".16", "$list, $addr!",<br>
- (ins VecListThreeDHWordIndexed:$list, addrmode6:$addr, pred:$p)>;<br>
+ (ins VecListThreeDHWordIndexed:$list, addrmode6alignNone:$addr,<br>
+ pred:$p)>;<br>
def VST3LNdWB_fixed_Asm_32 :<br>
NEONDataTypeAsmPseudoInst<"vst3${p}", ".32", "$list, $addr!",<br>
- (ins VecListThreeDWordIndexed:$list, addrmode6:$addr, pred:$p)>;<br>
+ (ins VecListThreeDWordIndexed:$list, addrmode6alignNone:$addr,<br>
+ pred:$p)>;<br>
def VST3LNqWB_fixed_Asm_16 :<br>
NEONDataTypeAsmPseudoInst<"vst3${p}", ".16", "$list, $addr!",<br>
- (ins VecListThreeQHWordIndexed:$list, addrmode6:$addr, pred:$p)>;<br>
+ (ins VecListThreeQHWordIndexed:$list, addrmode6alignNone:$addr,<br>
+ pred:$p)>;<br>
def VST3LNqWB_fixed_Asm_32 :<br>
NEONDataTypeAsmPseudoInst<"vst3${p}", ".32", "$list, $addr!",<br>
- (ins VecListThreeQWordIndexed:$list, addrmode6:$addr, pred:$p)>;<br>
+ (ins VecListThreeQWordIndexed:$list, addrmode6alignNone:$addr,<br>
+ pred:$p)>;<br>
def VST3LNdWB_register_Asm_8 :<br>
NEONDataTypeAsmPseudoInst<"vst3${p}", ".8", "$list, $addr, $Rm",<br>
- (ins VecListThreeDByteIndexed:$list, addrmode6:$addr,<br>
+ (ins VecListThreeDByteIndexed:$list, addrmode6alignNone:$addr,<br>
rGPR:$Rm, pred:$p)>;<br>
def VST3LNdWB_register_Asm_16 :<br>
NEONDataTypeAsmPseudoInst<"vst3${p}", ".16", "$list, $addr, $Rm",<br>
- (ins VecListThreeDHWordIndexed:$list, addrmode6:$addr,<br>
- rGPR:$Rm, pred:$p)>;<br>
+ (ins VecListThreeDHWordIndexed:$list,<br>
+ addrmode6alignNone:$addr, rGPR:$Rm, pred:$p)>;<br>
def VST3LNdWB_register_Asm_32 :<br>
NEONDataTypeAsmPseudoInst<"vst3${p}", ".32", "$list, $addr, $Rm",<br>
- (ins VecListThreeDWordIndexed:$list, addrmode6:$addr,<br>
+ (ins VecListThreeDWordIndexed:$list, addrmode6alignNone:$addr,<br>
rGPR:$Rm, pred:$p)>;<br>
def VST3LNqWB_register_Asm_16 :<br>
NEONDataTypeAsmPseudoInst<"vst3${p}", ".16", "$list, $addr, $Rm",<br>
- (ins VecListThreeQHWordIndexed:$list, addrmode6:$addr,<br>
- rGPR:$Rm, pred:$p)>;<br>
+ (ins VecListThreeQHWordIndexed:$list,<br>
+ addrmode6alignNone:$addr, rGPR:$Rm, pred:$p)>;<br>
def VST3LNqWB_register_Asm_32 :<br>
NEONDataTypeAsmPseudoInst<"vst3${p}", ".32", "$list, $addr, $Rm",<br>
- (ins VecListThreeQWordIndexed:$list, addrmode6:$addr,<br>
+ (ins VecListThreeQWordIndexed:$list, addrmode6alignNone:$addr,<br>
rGPR:$Rm, pred:$p)>;<br>
<br>
<br>
@@ -6691,168 +6810,190 @@ def VST3LNqWB_register_Asm_32 :<br>
// the vector operands that the normal instructions don't yet model.<br>
// FIXME: Remove these when the register classes and instructions are updated.<br>
def VST3dAsm_8 : NEONDataTypeAsmPseudoInst<"vst3${p}", ".8", "$list, $addr",<br>
- (ins VecListThreeD:$list, addrmode6:$addr, pred:$p)>;<br>
+ (ins VecListThreeD:$list, addrmode6align64:$addr, pred:$p)>;<br>
def VST3dAsm_16 : NEONDataTypeAsmPseudoInst<"vst3${p}", ".16", "$list, $addr",<br>
- (ins VecListThreeD:$list, addrmode6:$addr, pred:$p)>;<br>
+ (ins VecListThreeD:$list, addrmode6align64:$addr, pred:$p)>;<br>
def VST3dAsm_32 : NEONDataTypeAsmPseudoInst<"vst3${p}", ".32", "$list, $addr",<br>
- (ins VecListThreeD:$list, addrmode6:$addr, pred:$p)>;<br>
+ (ins VecListThreeD:$list, addrmode6align64:$addr, pred:$p)>;<br>
def VST3qAsm_8 : NEONDataTypeAsmPseudoInst<"vst3${p}", ".8", "$list, $addr",<br>
- (ins VecListThreeQ:$list, addrmode6:$addr, pred:$p)>;<br>
+ (ins VecListThreeQ:$list, addrmode6align64:$addr, pred:$p)>;<br>
def VST3qAsm_16 : NEONDataTypeAsmPseudoInst<"vst3${p}", ".16", "$list, $addr",<br>
- (ins VecListThreeQ:$list, addrmode6:$addr, pred:$p)>;<br>
+ (ins VecListThreeQ:$list, addrmode6align64:$addr, pred:$p)>;<br>
def VST3qAsm_32 : NEONDataTypeAsmPseudoInst<"vst3${p}", ".32", "$list, $addr",<br>
- (ins VecListThreeQ:$list, addrmode6:$addr, pred:$p)>;<br>
+ (ins VecListThreeQ:$list, addrmode6align64:$addr, pred:$p)>;<br>
<br>
def VST3dWB_fixed_Asm_8 :<br>
NEONDataTypeAsmPseudoInst<"vst3${p}", ".8", "$list, $addr!",<br>
- (ins VecListThreeD:$list, addrmode6:$addr, pred:$p)>;<br>
+ (ins VecListThreeD:$list, addrmode6align64:$addr, pred:$p)>;<br>
def VST3dWB_fixed_Asm_16 :<br>
NEONDataTypeAsmPseudoInst<"vst3${p}", ".16", "$list, $addr!",<br>
- (ins VecListThreeD:$list, addrmode6:$addr, pred:$p)>;<br>
+ (ins VecListThreeD:$list, addrmode6align64:$addr, pred:$p)>;<br>
def VST3dWB_fixed_Asm_32 :<br>
NEONDataTypeAsmPseudoInst<"vst3${p}", ".32", "$list, $addr!",<br>
- (ins VecListThreeD:$list, addrmode6:$addr, pred:$p)>;<br>
+ (ins VecListThreeD:$list, addrmode6align64:$addr, pred:$p)>;<br>
def VST3qWB_fixed_Asm_8 :<br>
NEONDataTypeAsmPseudoInst<"vst3${p}", ".8", "$list, $addr!",<br>
- (ins VecListThreeQ:$list, addrmode6:$addr, pred:$p)>;<br>
+ (ins VecListThreeQ:$list, addrmode6align64:$addr, pred:$p)>;<br>
def VST3qWB_fixed_Asm_16 :<br>
NEONDataTypeAsmPseudoInst<"vst3${p}", ".16", "$list, $addr!",<br>
- (ins VecListThreeQ:$list, addrmode6:$addr, pred:$p)>;<br>
+ (ins VecListThreeQ:$list, addrmode6align64:$addr, pred:$p)>;<br>
def VST3qWB_fixed_Asm_32 :<br>
NEONDataTypeAsmPseudoInst<"vst3${p}", ".32", "$list, $addr!",<br>
- (ins VecListThreeQ:$list, addrmode6:$addr, pred:$p)>;<br>
+ (ins VecListThreeQ:$list, addrmode6align64:$addr, pred:$p)>;<br>
def VST3dWB_register_Asm_8 :<br>
NEONDataTypeAsmPseudoInst<"vst3${p}", ".8", "$list, $addr, $Rm",<br>
- (ins VecListThreeD:$list, addrmode6:$addr,<br>
+ (ins VecListThreeD:$list, addrmode6align64:$addr,<br>
rGPR:$Rm, pred:$p)>;<br>
def VST3dWB_register_Asm_16 :<br>
NEONDataTypeAsmPseudoInst<"vst3${p}", ".16", "$list, $addr, $Rm",<br>
- (ins VecListThreeD:$list, addrmode6:$addr,<br>
+ (ins VecListThreeD:$list, addrmode6align64:$addr,<br>
rGPR:$Rm, pred:$p)>;<br>
def VST3dWB_register_Asm_32 :<br>
NEONDataTypeAsmPseudoInst<"vst3${p}", ".32", "$list, $addr, $Rm",<br>
- (ins VecListThreeD:$list, addrmode6:$addr,<br>
+ (ins VecListThreeD:$list, addrmode6align64:$addr,<br>
rGPR:$Rm, pred:$p)>;<br>
def VST3qWB_register_Asm_8 :<br>
NEONDataTypeAsmPseudoInst<"vst3${p}", ".8", "$list, $addr, $Rm",<br>
- (ins VecListThreeQ:$list, addrmode6:$addr,<br>
+ (ins VecListThreeQ:$list, addrmode6align64:$addr,<br>
rGPR:$Rm, pred:$p)>;<br>
def VST3qWB_register_Asm_16 :<br>
NEONDataTypeAsmPseudoInst<"vst3${p}", ".16", "$list, $addr, $Rm",<br>
- (ins VecListThreeQ:$list, addrmode6:$addr,<br>
+ (ins VecListThreeQ:$list, addrmode6align64:$addr,<br>
rGPR:$Rm, pred:$p)>;<br>
def VST3qWB_register_Asm_32 :<br>
NEONDataTypeAsmPseudoInst<"vst3${p}", ".32", "$list, $addr, $Rm",<br>
- (ins VecListThreeQ:$list, addrmode6:$addr,<br>
+ (ins VecListThreeQ:$list, addrmode6align64:$addr,<br>
rGPR:$Rm, pred:$p)>;<br>
<br>
// VLD4 all-lanes pseudo-instructions. These need special handling for<br>
// the lane index that an InstAlias can't handle, so we use these instead.<br>
def VLD4DUPdAsm_8 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr",<br>
- (ins VecListFourDAllLanes:$list, addrmode6:$addr, pred:$p)>;<br>
+ (ins VecListFourDAllLanes:$list, addrmode6dupalign32:$addr,<br>
+ pred:$p)>;<br>
def VLD4DUPdAsm_16: NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr",<br>
- (ins VecListFourDAllLanes:$list, addrmode6:$addr, pred:$p)>;<br>
+ (ins VecListFourDAllLanes:$list, addrmode6dupalign64:$addr,<br>
+ pred:$p)>;<br>
def VLD4DUPdAsm_32: NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr",<br>
- (ins VecListFourDAllLanes:$list, addrmode6:$addr, pred:$p)>;<br>
+ (ins VecListFourDAllLanes:$list, addrmode6dupalign64or128:$addr,<br>
+ pred:$p)>;<br>
def VLD4DUPqAsm_8 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr",<br>
- (ins VecListFourQAllLanes:$list, addrmode6:$addr, pred:$p)>;<br>
+ (ins VecListFourQAllLanes:$list, addrmode6dupalign32:$addr,<br>
+ pred:$p)>;<br>
def VLD4DUPqAsm_16: NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr",<br>
- (ins VecListFourQAllLanes:$list, addrmode6:$addr, pred:$p)>;<br>
+ (ins VecListFourQAllLanes:$list, addrmode6dupalign64:$addr,<br>
+ pred:$p)>;<br>
def VLD4DUPqAsm_32: NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr",<br>
- (ins VecListFourQAllLanes:$list, addrmode6:$addr, pred:$p)>;<br>
+ (ins VecListFourQAllLanes:$list, addrmode6dupalign64or128:$addr,<br>
+ pred:$p)>;<br>
<br>
def VLD4DUPdWB_fixed_Asm_8 :<br>
NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr!",<br>
- (ins VecListFourDAllLanes:$list, addrmode6:$addr, pred:$p)>;<br>
+ (ins VecListFourDAllLanes:$list, addrmode6dupalign32:$addr,<br>
+ pred:$p)>;<br>
def VLD4DUPdWB_fixed_Asm_16 :<br>
NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr!",<br>
- (ins VecListFourDAllLanes:$list, addrmode6:$addr, pred:$p)>;<br>
+ (ins VecListFourDAllLanes:$list, addrmode6dupalign64:$addr,<br>
+ pred:$p)>;<br>
def VLD4DUPdWB_fixed_Asm_32 :<br>
NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr!",<br>
- (ins VecListFourDAllLanes:$list, addrmode6:$addr, pred:$p)>;<br>
+ (ins VecListFourDAllLanes:$list, addrmode6dupalign64or128:$addr,<br>
+ pred:$p)>;<br>
def VLD4DUPqWB_fixed_Asm_8 :<br>
NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr!",<br>
- (ins VecListFourQAllLanes:$list, addrmode6:$addr, pred:$p)>;<br>
+ (ins VecListFourQAllLanes:$list, addrmode6dupalign32:$addr,<br>
+ pred:$p)>;<br>
def VLD4DUPqWB_fixed_Asm_16 :<br>
NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr!",<br>
- (ins VecListFourQAllLanes:$list, addrmode6:$addr, pred:$p)>;<br>
+ (ins VecListFourQAllLanes:$list, addrmode6dupalign64:$addr,<br>
+ pred:$p)>;<br>
def VLD4DUPqWB_fixed_Asm_32 :<br>
NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr!",<br>
- (ins VecListFourQAllLanes:$list, addrmode6:$addr, pred:$p)>;<br>
+ (ins VecListFourQAllLanes:$list, addrmode6dupalign64or128:$addr,<br>
+ pred:$p)>;<br>
def VLD4DUPdWB_register_Asm_8 :<br>
NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr, $Rm",<br>
- (ins VecListFourDAllLanes:$list, addrmode6:$addr,<br>
+ (ins VecListFourDAllLanes:$list, addrmode6dupalign32:$addr,<br>
rGPR:$Rm, pred:$p)>;<br>
def VLD4DUPdWB_register_Asm_16 :<br>
NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr, $Rm",<br>
- (ins VecListFourDAllLanes:$list, addrmode6:$addr,<br>
+ (ins VecListFourDAllLanes:$list, addrmode6dupalign64:$addr,<br>
rGPR:$Rm, pred:$p)>;<br>
def VLD4DUPdWB_register_Asm_32 :<br>
NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr, $Rm",<br>
- (ins VecListFourDAllLanes:$list, addrmode6:$addr,<br>
- rGPR:$Rm, pred:$p)>;<br>
+ (ins VecListFourDAllLanes:$list,<br>
+ addrmode6dupalign64or128:$addr, rGPR:$Rm, pred:$p)>;<br>
def VLD4DUPqWB_register_Asm_8 :<br>
NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr, $Rm",<br>
- (ins VecListFourQAllLanes:$list, addrmode6:$addr,<br>
+ (ins VecListFourQAllLanes:$list, addrmode6dupalign32:$addr,<br>
rGPR:$Rm, pred:$p)>;<br>
def VLD4DUPqWB_register_Asm_16 :<br>
NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr, $Rm",<br>
- (ins VecListFourQAllLanes:$list, addrmode6:$addr,<br>
+ (ins VecListFourQAllLanes:$list, addrmode6dupalign64:$addr,<br>
rGPR:$Rm, pred:$p)>;<br>
def VLD4DUPqWB_register_Asm_32 :<br>
NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr, $Rm",<br>
- (ins VecListFourQAllLanes:$list, addrmode6:$addr,<br>
- rGPR:$Rm, pred:$p)>;<br>
+ (ins VecListFourQAllLanes:$list,<br>
+ addrmode6dupalign64or128:$addr, rGPR:$Rm, pred:$p)>;<br>
<br>
<br>
// VLD4 single-lane pseudo-instructions. These need special handling for<br>
// the lane index that an InstAlias can't handle, so we use these instead.<br>
def VLD4LNdAsm_8 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr",<br>
- (ins VecListFourDByteIndexed:$list, addrmode6:$addr, pred:$p)>;<br>
+ (ins VecListFourDByteIndexed:$list, addrmode6align32:$addr,<br>
+ pred:$p)>;<br>
def VLD4LNdAsm_16 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr",<br>
- (ins VecListFourDHWordIndexed:$list, addrmode6:$addr, pred:$p)>;<br>
+ (ins VecListFourDHWordIndexed:$list, addrmode6align64:$addr,<br>
+ pred:$p)>;<br>
def VLD4LNdAsm_32 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr",<br>
- (ins VecListFourDWordIndexed:$list, addrmode6:$addr, pred:$p)>;<br>
+ (ins VecListFourDWordIndexed:$list, addrmode6align64or128:$addr,<br>
+ pred:$p)>;<br>
def VLD4LNqAsm_16 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr",<br>
- (ins VecListFourQHWordIndexed:$list, addrmode6:$addr, pred:$p)>;<br>
+ (ins VecListFourQHWordIndexed:$list, addrmode6align64:$addr,<br>
+ pred:$p)>;<br>
def VLD4LNqAsm_32 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr",<br>
- (ins VecListFourQWordIndexed:$list, addrmode6:$addr, pred:$p)>;<br>
+ (ins VecListFourQWordIndexed:$list, addrmode6align64or128:$addr,<br>
+ pred:$p)>;<br>
<br>
def VLD4LNdWB_fixed_Asm_8 :<br>
NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr!",<br>
- (ins VecListFourDByteIndexed:$list, addrmode6:$addr, pred:$p)>;<br>
+ (ins VecListFourDByteIndexed:$list, addrmode6align32:$addr,<br>
+ pred:$p)>;<br>
def VLD4LNdWB_fixed_Asm_16 :<br>
NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr!",<br>
- (ins VecListFourDHWordIndexed:$list, addrmode6:$addr, pred:$p)>;<br>
+ (ins VecListFourDHWordIndexed:$list, addrmode6align64:$addr,<br>
+ pred:$p)>;<br>
def VLD4LNdWB_fixed_Asm_32 :<br>
NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr!",<br>
- (ins VecListFourDWordIndexed:$list, addrmode6:$addr, pred:$p)>;<br>
+ (ins VecListFourDWordIndexed:$list, addrmode6align64or128:$addr,<br>
+ pred:$p)>;<br>
def VLD4LNqWB_fixed_Asm_16 :<br>
NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr!",<br>
- (ins VecListFourQHWordIndexed:$list, addrmode6:$addr, pred:$p)>;<br>
+ (ins VecListFourQHWordIndexed:$list, addrmode6align64:$addr,<br>
+ pred:$p)>;<br>
def VLD4LNqWB_fixed_Asm_32 :<br>
NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr!",<br>
- (ins VecListFourQWordIndexed:$list, addrmode6:$addr, pred:$p)>;<br>
+ (ins VecListFourQWordIndexed:$list, addrmode6align64or128:$addr,<br>
+ pred:$p)>;<br>
def VLD4LNdWB_register_Asm_8 :<br>
NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr, $Rm",<br>
- (ins VecListFourDByteIndexed:$list, addrmode6:$addr,<br>
+ (ins VecListFourDByteIndexed:$list, addrmode6align32:$addr,<br>
rGPR:$Rm, pred:$p)>;<br>
def VLD4LNdWB_register_Asm_16 :<br>
NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr, $Rm",<br>
- (ins VecListFourDHWordIndexed:$list, addrmode6:$addr,<br>
+ (ins VecListFourDHWordIndexed:$list, addrmode6align64:$addr,<br>
rGPR:$Rm, pred:$p)>;<br>
def VLD4LNdWB_register_Asm_32 :<br>
NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr, $Rm",<br>
- (ins VecListFourDWordIndexed:$list, addrmode6:$addr,<br>
- rGPR:$Rm, pred:$p)>;<br>
+ (ins VecListFourDWordIndexed:$list,<br>
+ addrmode6align64or128:$addr, rGPR:$Rm, pred:$p)>;<br>
def VLD4LNqWB_register_Asm_16 :<br>
NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr, $Rm",<br>
- (ins VecListFourQHWordIndexed:$list, addrmode6:$addr,<br>
+ (ins VecListFourQHWordIndexed:$list, addrmode6align64:$addr,<br>
rGPR:$Rm, pred:$p)>;<br>
def VLD4LNqWB_register_Asm_32 :<br>
NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr, $Rm",<br>
- (ins VecListFourQWordIndexed:$list, addrmode6:$addr,<br>
- rGPR:$Rm, pred:$p)>;<br>
+ (ins VecListFourQWordIndexed:$list,<br>
+ addrmode6align64or128:$addr, rGPR:$Rm, pred:$p)>;<br>
<br>
<br>
<br>
@@ -6860,168 +7001,202 @@ def VLD4LNqWB_register_Asm_32 :<br>
// the vector operands that the normal instructions don't yet model.<br>
// FIXME: Remove these when the register classes and instructions are updated.<br>
def VLD4dAsm_8 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr",<br>
- (ins VecListFourD:$list, addrmode6:$addr, pred:$p)>;<br>
+ (ins VecListFourD:$list, addrmode6align64or128or256:$addr,<br>
+ pred:$p)>;<br>
def VLD4dAsm_16 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr",<br>
- (ins VecListFourD:$list, addrmode6:$addr, pred:$p)>;<br>
+ (ins VecListFourD:$list, addrmode6align64or128or256:$addr,<br>
+ pred:$p)>;<br>
def VLD4dAsm_32 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr",<br>
- (ins VecListFourD:$list, addrmode6:$addr, pred:$p)>;<br>
+ (ins VecListFourD:$list, addrmode6align64or128or256:$addr,<br>
+ pred:$p)>;<br>
def VLD4qAsm_8 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr",<br>
- (ins VecListFourQ:$list, addrmode6:$addr, pred:$p)>;<br>
+ (ins VecListFourQ:$list, addrmode6align64or128or256:$addr,<br>
+ pred:$p)>;<br>
def VLD4qAsm_16 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr",<br>
- (ins VecListFourQ:$list, addrmode6:$addr, pred:$p)>;<br>
+ (ins VecListFourQ:$list, addrmode6align64or128or256:$addr,<br>
+ pred:$p)>;<br>
def VLD4qAsm_32 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr",<br>
- (ins VecListFourQ:$list, addrmode6:$addr, pred:$p)>;<br>
+ (ins VecListFourQ:$list, addrmode6align64or128or256:$addr,<br>
+ pred:$p)>;<br>
<br>
def VLD4dWB_fixed_Asm_8 :<br>
NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr!",<br>
- (ins VecListFourD:$list, addrmode6:$addr, pred:$p)>;<br>
+ (ins VecListFourD:$list, addrmode6align64or128or256:$addr,<br>
+ pred:$p)>;<br>
def VLD4dWB_fixed_Asm_16 :<br>
NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr!",<br>
- (ins VecListFourD:$list, addrmode6:$addr, pred:$p)>;<br>
+ (ins VecListFourD:$list, addrmode6align64or128or256:$addr,<br>
+ pred:$p)>;<br>
def VLD4dWB_fixed_Asm_32 :<br>
NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr!",<br>
- (ins VecListFourD:$list, addrmode6:$addr, pred:$p)>;<br>
+ (ins VecListFourD:$list, addrmode6align64or128or256:$addr,<br>
+ pred:$p)>;<br>
def VLD4qWB_fixed_Asm_8 :<br>
NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr!",<br>
- (ins VecListFourQ:$list, addrmode6:$addr, pred:$p)>;<br>
+ (ins VecListFourQ:$list, addrmode6align64or128or256:$addr,<br>
+ pred:$p)>;<br>
def VLD4qWB_fixed_Asm_16 :<br>
NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr!",<br>
- (ins VecListFourQ:$list, addrmode6:$addr, pred:$p)>;<br>
+ (ins VecListFourQ:$list, addrmode6align64or128or256:$addr,<br>
+ pred:$p)>;<br>
def VLD4qWB_fixed_Asm_32 :<br>
NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr!",<br>
- (ins VecListFourQ:$list, addrmode6:$addr, pred:$p)>;<br>
+ (ins VecListFourQ:$list, addrmode6align64or128or256:$addr,<br>
+ pred:$p)>;<br>
def VLD4dWB_register_Asm_8 :<br>
NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr, $Rm",<br>
- (ins VecListFourD:$list, addrmode6:$addr,<br>
+ (ins VecListFourD:$list, addrmode6align64or128or256:$addr,<br>
rGPR:$Rm, pred:$p)>;<br>
def VLD4dWB_register_Asm_16 :<br>
NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr, $Rm",<br>
- (ins VecListFourD:$list, addrmode6:$addr,<br>
+ (ins VecListFourD:$list, addrmode6align64or128or256:$addr,<br>
rGPR:$Rm, pred:$p)>;<br>
def VLD4dWB_register_Asm_32 :<br>
NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr, $Rm",<br>
- (ins VecListFourD:$list, addrmode6:$addr,<br>
+ (ins VecListFourD:$list, addrmode6align64or128or256:$addr,<br>
rGPR:$Rm, pred:$p)>;<br>
def VLD4qWB_register_Asm_8 :<br>
NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr, $Rm",<br>
- (ins VecListFourQ:$list, addrmode6:$addr,<br>
+ (ins VecListFourQ:$list, addrmode6align64or128or256:$addr,<br>
rGPR:$Rm, pred:$p)>;<br>
def VLD4qWB_register_Asm_16 :<br>
NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr, $Rm",<br>
- (ins VecListFourQ:$list, addrmode6:$addr,<br>
+ (ins VecListFourQ:$list, addrmode6align64or128or256:$addr,<br>
rGPR:$Rm, pred:$p)>;<br>
def VLD4qWB_register_Asm_32 :<br>
NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr, $Rm",<br>
- (ins VecListFourQ:$list, addrmode6:$addr,<br>
+ (ins VecListFourQ:$list, addrmode6align64or128or256:$addr,<br>
rGPR:$Rm, pred:$p)>;<br>
<br>
// VST4 single-lane pseudo-instructions. These need special handling for<br>
// the lane index that an InstAlias can't handle, so we use these instead.<br>
def VST4LNdAsm_8 : NEONDataTypeAsmPseudoInst<"vst4${p}", ".8", "$list, $addr",<br>
- (ins VecListFourDByteIndexed:$list, addrmode6:$addr, pred:$p)>;<br>
+ (ins VecListFourDByteIndexed:$list, addrmode6align32:$addr,<br>
+ pred:$p)>;<br>
def VST4LNdAsm_16 : NEONDataTypeAsmPseudoInst<"vst4${p}", ".16", "$list, $addr",<br>
- (ins VecListFourDHWordIndexed:$list, addrmode6:$addr, pred:$p)>;<br>
+ (ins VecListFourDHWordIndexed:$list, addrmode6align64:$addr,<br>
+ pred:$p)>;<br>
def VST4LNdAsm_32 : NEONDataTypeAsmPseudoInst<"vst4${p}", ".32", "$list, $addr",<br>
- (ins VecListFourDWordIndexed:$list, addrmode6:$addr, pred:$p)>;<br>
+ (ins VecListFourDWordIndexed:$list, addrmode6align64or128:$addr,<br>
+ pred:$p)>;<br>
def VST4LNqAsm_16 : NEONDataTypeAsmPseudoInst<"vst4${p}", ".16", "$list, $addr",<br>
- (ins VecListFourQHWordIndexed:$list, addrmode6:$addr, pred:$p)>;<br>
+ (ins VecListFourQHWordIndexed:$list, addrmode6align64:$addr,<br>
+ pred:$p)>;<br>
def VST4LNqAsm_32 : NEONDataTypeAsmPseudoInst<"vst4${p}", ".32", "$list, $addr",<br>
- (ins VecListFourQWordIndexed:$list, addrmode6:$addr, pred:$p)>;<br>
+ (ins VecListFourQWordIndexed:$list, addrmode6align64or128:$addr,<br>
+ pred:$p)>;<br>
<br>
def VST4LNdWB_fixed_Asm_8 :<br>
NEONDataTypeAsmPseudoInst<"vst4${p}", ".8", "$list, $addr!",<br>
- (ins VecListFourDByteIndexed:$list, addrmode6:$addr, pred:$p)>;<br>
+ (ins VecListFourDByteIndexed:$list, addrmode6align32:$addr,<br>
+ pred:$p)>;<br>
def VST4LNdWB_fixed_Asm_16 :<br>
NEONDataTypeAsmPseudoInst<"vst4${p}", ".16", "$list, $addr!",<br>
- (ins VecListFourDHWordIndexed:$list, addrmode6:$addr, pred:$p)>;<br>
+ (ins VecListFourDHWordIndexed:$list, addrmode6align64:$addr,<br>
+ pred:$p)>;<br>
def VST4LNdWB_fixed_Asm_32 :<br>
NEONDataTypeAsmPseudoInst<"vst4${p}", ".32", "$list, $addr!",<br>
- (ins VecListFourDWordIndexed:$list, addrmode6:$addr, pred:$p)>;<br>
+ (ins VecListFourDWordIndexed:$list, addrmode6align64or128:$addr,<br>
+ pred:$p)>;<br>
def VST4LNqWB_fixed_Asm_16 :<br>
NEONDataTypeAsmPseudoInst<"vst4${p}", ".16", "$list, $addr!",<br>
- (ins VecListFourQHWordIndexed:$list, addrmode6:$addr, pred:$p)>;<br>
+ (ins VecListFourQHWordIndexed:$list, addrmode6align64:$addr,<br>
+ pred:$p)>;<br>
def VST4LNqWB_fixed_Asm_32 :<br>
NEONDataTypeAsmPseudoInst<"vst4${p}", ".32", "$list, $addr!",<br>
- (ins VecListFourQWordIndexed:$list, addrmode6:$addr, pred:$p)>;<br>
+ (ins VecListFourQWordIndexed:$list, addrmode6align64or128:$addr,<br>
+ pred:$p)>;<br>
def VST4LNdWB_register_Asm_8 :<br>
NEONDataTypeAsmPseudoInst<"vst4${p}", ".8", "$list, $addr, $Rm",<br>
- (ins VecListFourDByteIndexed:$list, addrmode6:$addr,<br>
+ (ins VecListFourDByteIndexed:$list, addrmode6align32:$addr,<br>
rGPR:$Rm, pred:$p)>;<br>
def VST4LNdWB_register_Asm_16 :<br>
NEONDataTypeAsmPseudoInst<"vst4${p}", ".16", "$list, $addr, $Rm",<br>
- (ins VecListFourDHWordIndexed:$list, addrmode6:$addr,<br>
+ (ins VecListFourDHWordIndexed:$list, addrmode6align64:$addr,<br>
rGPR:$Rm, pred:$p)>;<br>
def VST4LNdWB_register_Asm_32 :<br>
NEONDataTypeAsmPseudoInst<"vst4${p}", ".32", "$list, $addr, $Rm",<br>
- (ins VecListFourDWordIndexed:$list, addrmode6:$addr,<br>
- rGPR:$Rm, pred:$p)>;<br>
+ (ins VecListFourDWordIndexed:$list,<br>
+ addrmode6align64or128:$addr, rGPR:$Rm, pred:$p)>;<br>
def VST4LNqWB_register_Asm_16 :<br>
NEONDataTypeAsmPseudoInst<"vst4${p}", ".16", "$list, $addr, $Rm",<br>
- (ins VecListFourQHWordIndexed:$list, addrmode6:$addr,<br>
+ (ins VecListFourQHWordIndexed:$list, addrmode6align64:$addr,<br>
rGPR:$Rm, pred:$p)>;<br>
def VST4LNqWB_register_Asm_32 :<br>
NEONDataTypeAsmPseudoInst<"vst4${p}", ".32", "$list, $addr, $Rm",<br>
- (ins VecListFourQWordIndexed:$list, addrmode6:$addr,<br>
- rGPR:$Rm, pred:$p)>;<br>
+ (ins VecListFourQWordIndexed:$list,<br>
+ addrmode6align64or128:$addr, rGPR:$Rm, pred:$p)>;<br>
<br>
<br>
// VST4 multiple structure pseudo-instructions. These need special handling for<br>
// the vector operands that the normal instructions don't yet model.<br>
// FIXME: Remove these when the register classes and instructions are updated.<br>
def VST4dAsm_8 : NEONDataTypeAsmPseudoInst<"vst4${p}", ".8", "$list, $addr",<br>
- (ins VecListFourD:$list, addrmode6:$addr, pred:$p)>;<br>
+ (ins VecListFourD:$list, addrmode6align64or128or256:$addr,<br>
+ pred:$p)>;<br>
def VST4dAsm_16 : NEONDataTypeAsmPseudoInst<"vst4${p}", ".16", "$list, $addr",<br>
- (ins VecListFourD:$list, addrmode6:$addr, pred:$p)>;<br>
+ (ins VecListFourD:$list, addrmode6align64or128or256:$addr,<br>
+ pred:$p)>;<br>
def VST4dAsm_32 : NEONDataTypeAsmPseudoInst<"vst4${p}", ".32", "$list, $addr",<br>
- (ins VecListFourD:$list, addrmode6:$addr, pred:$p)>;<br>
+ (ins VecListFourD:$list, addrmode6align64or128or256:$addr,<br>
+ pred:$p)>;<br>
def VST4qAsm_8 : NEONDataTypeAsmPseudoInst<"vst4${p}", ".8", "$list, $addr",<br>
- (ins VecListFourQ:$list, addrmode6:$addr, pred:$p)>;<br>
+ (ins VecListFourQ:$list, addrmode6align64or128or256:$addr,<br>
+ pred:$p)>;<br>
def VST4qAsm_16 : NEONDataTypeAsmPseudoInst<"vst4${p}", ".16", "$list, $addr",<br>
- (ins VecListFourQ:$list, addrmode6:$addr, pred:$p)>;<br>
+ (ins VecListFourQ:$list, addrmode6align64or128or256:$addr,<br>
+ pred:$p)>;<br>
def VST4qAsm_32 : NEONDataTypeAsmPseudoInst<"vst4${p}", ".32", "$list, $addr",<br>
- (ins VecListFourQ:$list, addrmode6:$addr, pred:$p)>;<br>
+ (ins VecListFourQ:$list, addrmode6align64or128or256:$addr,<br>
+ pred:$p)>;<br>
<br>
def VST4dWB_fixed_Asm_8 :<br>
NEONDataTypeAsmPseudoInst<"vst4${p}", ".8", "$list, $addr!",<br>
- (ins VecListFourD:$list, addrmode6:$addr, pred:$p)>;<br>
+ (ins VecListFourD:$list, addrmode6align64or128or256:$addr,<br>
+ pred:$p)>;<br>
def VST4dWB_fixed_Asm_16 :<br>
NEONDataTypeAsmPseudoInst<"vst4${p}", ".16", "$list, $addr!",<br>
- (ins VecListFourD:$list, addrmode6:$addr, pred:$p)>;<br>
+ (ins VecListFourD:$list, addrmode6align64or128or256:$addr,<br>
+ pred:$p)>;<br>
def VST4dWB_fixed_Asm_32 :<br>
NEONDataTypeAsmPseudoInst<"vst4${p}", ".32", "$list, $addr!",<br>
- (ins VecListFourD:$list, addrmode6:$addr, pred:$p)>;<br>
+ (ins VecListFourD:$list, addrmode6align64or128or256:$addr,<br>
+ pred:$p)>;<br>
def VST4qWB_fixed_Asm_8 :<br>
NEONDataTypeAsmPseudoInst<"vst4${p}", ".8", "$list, $addr!",<br>
- (ins VecListFourQ:$list, addrmode6:$addr, pred:$p)>;<br>
+ (ins VecListFourQ:$list, addrmode6align64or128or256:$addr,<br>
+ pred:$p)>;<br>
def VST4qWB_fixed_Asm_16 :<br>
NEONDataTypeAsmPseudoInst<"vst4${p}", ".16", "$list, $addr!",<br>
- (ins VecListFourQ:$list, addrmode6:$addr, pred:$p)>;<br>
+ (ins VecListFourQ:$list, addrmode6align64or128or256:$addr,<br>
+ pred:$p)>;<br>
def VST4qWB_fixed_Asm_32 :<br>
NEONDataTypeAsmPseudoInst<"vst4${p}", ".32", "$list, $addr!",<br>
- (ins VecListFourQ:$list, addrmode6:$addr, pred:$p)>;<br>
+ (ins VecListFourQ:$list, addrmode6align64or128or256:$addr,<br>
+ pred:$p)>;<br>
def VST4dWB_register_Asm_8 :<br>
NEONDataTypeAsmPseudoInst<"vst4${p}", ".8", "$list, $addr, $Rm",<br>
- (ins VecListFourD:$list, addrmode6:$addr,<br>
+ (ins VecListFourD:$list, addrmode6align64or128or256:$addr,<br>
rGPR:$Rm, pred:$p)>;<br>
def VST4dWB_register_Asm_16 :<br>
NEONDataTypeAsmPseudoInst<"vst4${p}", ".16", "$list, $addr, $Rm",<br>
- (ins VecListFourD:$list, addrmode6:$addr,<br>
+ (ins VecListFourD:$list, addrmode6align64or128or256:$addr,<br>
rGPR:$Rm, pred:$p)>;<br>
def VST4dWB_register_Asm_32 :<br>
NEONDataTypeAsmPseudoInst<"vst4${p}", ".32", "$list, $addr, $Rm",<br>
- (ins VecListFourD:$list, addrmode6:$addr,<br>
+ (ins VecListFourD:$list, addrmode6align64or128or256:$addr,<br>
rGPR:$Rm, pred:$p)>;<br>
def VST4qWB_register_Asm_8 :<br>
NEONDataTypeAsmPseudoInst<"vst4${p}", ".8", "$list, $addr, $Rm",<br>
- (ins VecListFourQ:$list, addrmode6:$addr,<br>
+ (ins VecListFourQ:$list, addrmode6align64or128or256:$addr,<br>
rGPR:$Rm, pred:$p)>;<br>
def VST4qWB_register_Asm_16 :<br>
NEONDataTypeAsmPseudoInst<"vst4${p}", ".16", "$list, $addr, $Rm",<br>
- (ins VecListFourQ:$list, addrmode6:$addr,<br>
+ (ins VecListFourQ:$list, addrmode6align64or128or256:$addr,<br>
rGPR:$Rm, pred:$p)>;<br>
def VST4qWB_register_Asm_32 :<br>
NEONDataTypeAsmPseudoInst<"vst4${p}", ".32", "$list, $addr, $Rm",<br>
- (ins VecListFourQ:$list, addrmode6:$addr,<br>
+ (ins VecListFourQ:$list, addrmode6align64or128or256:$addr,<br>
rGPR:$Rm, pred:$p)>;<br>
<br>
// VMOV/VMVN takes an optional datatype suffix<br>
<br>
Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=205930&r1=205929&r2=205930&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=205930&r1=205929&r2=205930&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original)<br>
+++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Wed Apr 9 16:32:59 2014<br>
@@ -486,6 +486,7 @@ class ARMOperand : public MCParsedAsmOpe<br>
ARM_AM::ShiftOpc ShiftType; // Shift type for OffsetReg<br>
unsigned ShiftImm; // shift for OffsetReg.<br>
unsigned Alignment; // 0 = no alignment specified<br>
+ SMLoc AlignmentLoc; // for error reporting if needed.<br>
// n = alignment in bytes (2, 4, 8, 16, or 32)<br>
unsigned isNegative : 1; // Negated OffsetReg? (~'U' bit)<br>
};<br>
@@ -633,6 +634,12 @@ public:<br>
/// operand.<br>
SMRange getLocRange() const { return SMRange(StartLoc, EndLoc); }<br>
<br>
+ /// getAlignmentLoc - Get the location of the Alignment token of this operand.<br>
+ SMLoc getAlignmentLoc() const {<br>
+ assert(Kind == k_Memory && "Invalid access!");<br>
+ return Memory.AlignmentLoc;<br>
+ }<br>
+<br>
ARMCC::CondCodes getCondCode() const {<br>
assert(Kind == k_CondCode && "Invalid access!");<br>
return CC.Val;<br>
@@ -1089,12 +1096,12 @@ public:<br>
bool isPostIdxReg() const {<br>
return Kind == k_PostIndexRegister && PostIdxReg.ShiftTy ==ARM_AM::no_shift;<br>
}<br>
- bool isMemNoOffset(bool alignOK = false) const {<br>
+ bool isMemNoOffset(bool alignOK = false, unsigned Alignment = 0) const {<br>
if (!isMem())<br>
return false;<br>
// No offset of any kind.<br>
return Memory.OffsetRegNum == 0 && Memory.OffsetImm == 0 &&<br>
- (alignOK || Memory.Alignment == 0);<br>
+ (alignOK || Memory.Alignment == Alignment);<br>
}<br>
bool isMemPCRelImm12() const {<br>
if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)<br>
@@ -1110,6 +1117,65 @@ public:<br>
bool isAlignedMemory() const {<br>
return isMemNoOffset(true);<br>
}<br>
+ bool isAlignedMemoryNone() const {<br>
+ return isMemNoOffset(false, 0);<br>
+ }<br>
+ bool isDupAlignedMemoryNone() const {<br>
+ return isMemNoOffset(false, 0);<br>
+ }<br>
+ bool isAlignedMemory16() const {<br>
+ if (isMemNoOffset(false, 2)) // alignment in bytes for 16-bits is 2.<br>
+ return true;<br>
+ return isMemNoOffset(false, 0);<br>
+ }<br>
+ bool isDupAlignedMemory16() const {<br>
+ if (isMemNoOffset(false, 2)) // alignment in bytes for 16-bits is 2.<br>
+ return true;<br>
+ return isMemNoOffset(false, 0);<br>
+ }<br>
+ bool isAlignedMemory32() const {<br>
+ if (isMemNoOffset(false, 4)) // alignment in bytes for 32-bits is 4.<br>
+ return true;<br>
+ return isMemNoOffset(false, 0);<br>
+ }<br>
+ bool isDupAlignedMemory32() const {<br>
+ if (isMemNoOffset(false, 4)) // alignment in bytes for 32-bits is 4.<br>
+ return true;<br>
+ return isMemNoOffset(false, 0);<br>
+ }<br>
+ bool isAlignedMemory64() const {<br>
+ if (isMemNoOffset(false, 8)) // alignment in bytes for 64-bits is 8.<br>
+ return true;<br>
+ return isMemNoOffset(false, 0);<br>
+ }<br>
+ bool isDupAlignedMemory64() const {<br>
+ if (isMemNoOffset(false, 8)) // alignment in bytes for 64-bits is 8.<br>
+ return true;<br>
+ return isMemNoOffset(false, 0);<br>
+ }<br>
+ bool isAlignedMemory64or128() const {<br>
+ if (isMemNoOffset(false, 8)) // alignment in bytes for 64-bits is 8.<br>
+ return true;<br>
+ if (isMemNoOffset(false, 16)) // alignment in bytes for 128-bits is 16.<br>
+ return true;<br>
+ return isMemNoOffset(false, 0);<br>
+ }<br>
+ bool isDupAlignedMemory64or128() const {<br>
+ if (isMemNoOffset(false, 8)) // alignment in bytes for 64-bits is 8.<br>
+ return true;<br>
+ if (isMemNoOffset(false, 16)) // alignment in bytes for 128-bits is 16.<br>
+ return true;<br>
+ return isMemNoOffset(false, 0);<br>
+ }<br>
+ bool isAlignedMemory64or128or256() const {<br>
+ if (isMemNoOffset(false, 8)) // alignment in bytes for 64-bits is 8.<br>
+ return true;<br>
+ if (isMemNoOffset(false, 16)) // alignment in bytes for 128-bits is 16.<br>
+ return true;<br>
+ if (isMemNoOffset(false, 32)) // alignment in bytes for 256-bits is 32.<br>
+ return true;<br>
+ return isMemNoOffset(false, 0);<br>
+ }<br>
bool isAddrMode2() const {<br>
if (!isMem() || Memory.Alignment != 0) return false;<br>
// Check for register offset.<br>
@@ -1926,6 +1992,50 @@ public:<br>
Inst.addOperand(MCOperand::CreateImm(Memory.Alignment));<br>
}<br>
<br>
+ void addDupAlignedMemoryNoneOperands(MCInst &Inst, unsigned N) const {<br>
+ addAlignedMemoryOperands(Inst, N);<br>
+ }<br>
+<br>
+ void addAlignedMemoryNoneOperands(MCInst &Inst, unsigned N) const {<br>
+ addAlignedMemoryOperands(Inst, N);<br>
+ }<br>
+<br>
+ void addAlignedMemory16Operands(MCInst &Inst, unsigned N) const {<br>
+ addAlignedMemoryOperands(Inst, N);<br>
+ }<br>
+<br>
+ void addDupAlignedMemory16Operands(MCInst &Inst, unsigned N) const {<br>
+ addAlignedMemoryOperands(Inst, N);<br>
+ }<br>
+<br>
+ void addAlignedMemory32Operands(MCInst &Inst, unsigned N) const {<br>
+ addAlignedMemoryOperands(Inst, N);<br>
+ }<br>
+<br>
+ void addDupAlignedMemory32Operands(MCInst &Inst, unsigned N) const {<br>
+ addAlignedMemoryOperands(Inst, N);<br>
+ }<br>
+<br>
+ void addAlignedMemory64Operands(MCInst &Inst, unsigned N) const {<br>
+ addAlignedMemoryOperands(Inst, N);<br>
+ }<br>
+<br>
+ void addDupAlignedMemory64Operands(MCInst &Inst, unsigned N) const {<br>
+ addAlignedMemoryOperands(Inst, N);<br>
+ }<br>
+<br>
+ void addAlignedMemory64or128Operands(MCInst &Inst, unsigned N) const {<br>
+ addAlignedMemoryOperands(Inst, N);<br>
+ }<br>
+<br>
+ void addDupAlignedMemory64or128Operands(MCInst &Inst, unsigned N) const {<br>
+ addAlignedMemoryOperands(Inst, N);<br>
+ }<br>
+<br>
+ void addAlignedMemory64or128or256Operands(MCInst &Inst, unsigned N) const {<br>
+ addAlignedMemoryOperands(Inst, N);<br>
+ }<br>
+<br>
void addAddrMode2Operands(MCInst &Inst, unsigned N) const {<br>
assert(N == 3 && "Invalid number of operands!");<br>
int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;<br>
@@ -2523,7 +2633,8 @@ public:<br>
unsigned ShiftImm,<br>
unsigned Alignment,<br>
bool isNegative,<br>
- SMLoc S, SMLoc E) {<br>
+ SMLoc S, SMLoc E,<br>
+ SMLoc AlignmentLoc = SMLoc()) {<br>
ARMOperand *Op = new ARMOperand(k_Memory);<br>
Op->Memory.BaseRegNum = BaseRegNum;<br>
Op->Memory.OffsetImm = OffsetImm;<br>
@@ -2531,6 +2642,7 @@ public:<br>
Op->Memory.ShiftType = ShiftType;<br>
Op->Memory.ShiftImm = ShiftImm;<br>
Op->Memory.Alignment = Alignment;<br>
+ Op->Memory.AlignmentLoc = AlignmentLoc;<br>
Op->Memory.isNegative = isNegative;<br>
Op->StartLoc = S;<br>
Op->EndLoc = E;<br>
@@ -4346,6 +4458,7 @@ parseMemory(SmallVectorImpl<MCParsedAsmO<br>
if (Parser.getTok().is(AsmToken::Colon)) {<br>
Parser.Lex(); // Eat the ':'.<br>
E = Parser.getTok().getLoc();<br>
+ SMLoc AlignmentLoc = Tok.getLoc();<br>
<br>
const MCExpr *Expr;<br>
if (getParser().parseExpression(Expr))<br>
@@ -4380,7 +4493,7 @@ parseMemory(SmallVectorImpl<MCParsedAsmO<br>
// the is*() predicates.<br>
Operands.push_back(ARMOperand::CreateMem(BaseRegNum, 0, 0,<br>
ARM_AM::no_shift, 0, Align,<br>
- false, S, E));<br>
+ false, S, E, AlignmentLoc));<br>
<br>
// If there's a pre-indexing writeback marker, '!', just add it as a token<br>
// operand.<br>
@@ -7968,6 +8081,42 @@ MatchAndEmitInstruction(SMLoc IDLoc, uns<br>
if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;<br>
return Error(ErrorLoc, "immediate operand must be in the range [0,239]");<br>
}<br>
+ case Match_AlignedMemoryRequiresNone:<br>
+ case Match_DupAlignedMemoryRequiresNone:<br>
+ case Match_AlignedMemoryRequires16:<br>
+ case Match_DupAlignedMemoryRequires16:<br>
+ case Match_AlignedMemoryRequires32:<br>
+ case Match_DupAlignedMemoryRequires32:<br>
+ case Match_AlignedMemoryRequires64:<br>
+ case Match_DupAlignedMemoryRequires64:<br>
+ case Match_AlignedMemoryRequires64or128:<br>
+ case Match_DupAlignedMemoryRequires64or128:<br>
+ case Match_AlignedMemoryRequires64or128or256:<br>
+ {<br>
+ SMLoc ErrorLoc = ((ARMOperand*)Operands[ErrorInfo])->getAlignmentLoc();<br>
+ if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;<br>
+ switch (MatchResult) {<br>
+ default:<br>
+ llvm_unreachable("Missing Match_Aligned type");<br>
+ case Match_AlignedMemoryRequiresNone:<br>
+ case Match_DupAlignedMemoryRequiresNone:<br>
+ return Error(ErrorLoc, "alignment must be omitted");<br>
+ case Match_AlignedMemoryRequires16:<br>
+ case Match_DupAlignedMemoryRequires16:<br>
+ return Error(ErrorLoc, "alignment must be 16 or omitted");<br>
+ case Match_AlignedMemoryRequires32:<br>
+ case Match_DupAlignedMemoryRequires32:<br>
+ return Error(ErrorLoc, "alignment must be 32 or omitted");<br>
+ case Match_AlignedMemoryRequires64:<br>
+ case Match_DupAlignedMemoryRequires64:<br>
+ return Error(ErrorLoc, "alignment must be 64 or omitted");<br>
+ case Match_AlignedMemoryRequires64or128:<br>
+ case Match_DupAlignedMemoryRequires64or128:<br>
+ return Error(ErrorLoc, "alignment must be 64, 128 or omitted");<br>
+ case Match_AlignedMemoryRequires64or128or256:<br>
+ return Error(ErrorLoc, "alignment must be 64, 128, 256 or omitted");<br>
+ }<br>
+ }<br>
}<br>
<br>
llvm_unreachable("Implement any new match types added!");<br>
<br>
Added: llvm/trunk/test/MC/ARM/neon-vld-vst-align.s<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/neon-vld-vst-align.s?rev=205930&view=auto" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/neon-vld-vst-align.s?rev=205930&view=auto</a><br>
==============================================================================<br>
--- llvm/trunk/test/MC/ARM/neon-vld-vst-align.s (added)<br>
+++ llvm/trunk/test/MC/ARM/neon-vld-vst-align.s Wed Apr 9 16:32:59 2014<br>
@@ -0,0 +1,8354 @@<br>
+@ RUN: not llvm-mc -triple=thumbv7-apple-darwin -show-encoding < %s > %t 2> %e<br>
+@ RUN: FileCheck < %t %s<br>
+@ RUN: FileCheck --check-prefix=CHECK-ERRORS < %e %s<br>
+<br>
+ vld1.8 {d0}, [r4]<br>
+ vld1.8 {d0}, [r4:16]<br>
+ vld1.8 {d0}, [r4:32]<br>
+ vld1.8 {d0}, [r4:64]<br>
+ vld1.8 {d0}, [r4:128]<br>
+ vld1.8 {d0}, [r4:256]<br>
+<br>
+@ CHECK: vld1.8 {d0}, [r4] @ encoding: [0x24,0xf9,0x0f,0x07]<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vld1.8 {d0}, [r4:16]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vld1.8 {d0}, [r4:32]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vld1.8 {d0}, [r4:64] @ encoding: [0x24,0xf9,0x1f,0x07]<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vld1.8 {d0}, [r4:128]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vld1.8 {d0}, [r4:256]<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vld1.8 {d0}, [r4]!<br>
+ vld1.8 {d0}, [r4:16]!<br>
+ vld1.8 {d0}, [r4:32]!<br>
+ vld1.8 {d0}, [r4:64]!<br>
+ vld1.8 {d0}, [r4:128]!<br>
+ vld1.8 {d0}, [r4:256]!<br>
+<br>
+@ CHECK: vld1.8 {d0}, [r4]! @ encoding: [0x24,0xf9,0x0d,0x07]<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vld1.8 {d0}, [r4:16]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vld1.8 {d0}, [r4:32]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vld1.8 {d0}, [r4:64]! @ encoding: [0x24,0xf9,0x1d,0x07]<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vld1.8 {d0}, [r4:128]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vld1.8 {d0}, [r4:256]!<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vld1.8 {d0}, [r4], r6<br>
+ vld1.8 {d0}, [r4:16], r6<br>
+ vld1.8 {d0}, [r4:32], r6<br>
+ vld1.8 {d0}, [r4:64], r6<br>
+ vld1.8 {d0}, [r4:128], r6<br>
+ vld1.8 {d0}, [r4:256], r6<br>
+<br>
+@ CHECK: vld1.8 {d0}, [r4], r6 @ encoding: [0x24,0xf9,0x06,0x07]<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vld1.8 {d0}, [r4:16], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vld1.8 {d0}, [r4:32], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vld1.8 {d0}, [r4:64], r6 @ encoding: [0x24,0xf9,0x16,0x07]<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vld1.8 {d0}, [r4:128], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vld1.8 {d0}, [r4:256], r6<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vld1.8 {d0, d1}, [r4]<br>
+ vld1.8 {d0, d1}, [r4:16]<br>
+ vld1.8 {d0, d1}, [r4:32]<br>
+ vld1.8 {d0, d1}, [r4:64]<br>
+ vld1.8 {d0, d1}, [r4:128]<br>
+ vld1.8 {d0, d1}, [r4:256]<br>
+<br>
+@ CHECK: vld1.8 {d0, d1}, [r4] @ encoding: [0x24,0xf9,0x0f,0x0a]<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted<br>
+@ CHECK-ERRORS: vld1.8 {d0, d1}, [r4:16]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted<br>
+@ CHECK-ERRORS: vld1.8 {d0, d1}, [r4:32]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vld1.8 {d0, d1}, [r4:64] @ encoding: [0x24,0xf9,0x1f,0x0a]<br>
+@ CHECK: vld1.8 {d0, d1}, [r4:128] @ encoding: [0x24,0xf9,0x2f,0x0a]<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted<br>
+@ CHECK-ERRORS: vld1.8 {d0, d1}, [r4:256]<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vld1.8 {d0, d1}, [r4]!<br>
+ vld1.8 {d0, d1}, [r4:16]!<br>
+ vld1.8 {d0, d1}, [r4:32]!<br>
+ vld1.8 {d0, d1}, [r4:64]!<br>
+ vld1.8 {d0, d1}, [r4:128]!<br>
+ vld1.8 {d0, d1}, [r4:256]!<br>
+<br>
+@ CHECK: vld1.8 {d0, d1}, [r4]! @ encoding: [0x24,0xf9,0x0d,0x0a]<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted<br>
+@ CHECK-ERRORS: vld1.8 {d0, d1}, [r4:16]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted<br>
+@ CHECK-ERRORS: vld1.8 {d0, d1}, [r4:32]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vld1.8 {d0, d1}, [r4:64]! @ encoding: [0x24,0xf9,0x1d,0x0a]<br>
+@ CHECK: vld1.8 {d0, d1}, [r4:128]! @ encoding: [0x24,0xf9,0x2d,0x0a]<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted<br>
+@ CHECK-ERRORS: vld1.8 {d0, d1}, [r4:256]!<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vld1.8 {d0, d1}, [r4], r6<br>
+ vld1.8 {d0, d1}, [r4:16], r6<br>
+ vld1.8 {d0, d1}, [r4:32], r6<br>
+ vld1.8 {d0, d1}, [r4:64], r6<br>
+ vld1.8 {d0, d1}, [r4:128], r6<br>
+ vld1.8 {d0, d1}, [r4:256], r6<br>
+<br>
+@ CHECK: vld1.8 {d0, d1}, [r4], r6 @ encoding: [0x24,0xf9,0x06,0x0a]<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted<br>
+@ CHECK-ERRORS: vld1.8 {d0, d1}, [r4:16], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted<br>
+@ CHECK-ERRORS: vld1.8 {d0, d1}, [r4:32], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vld1.8 {d0, d1}, [r4:64], r6 @ encoding: [0x24,0xf9,0x16,0x0a]<br>
+@ CHECK: vld1.8 {d0, d1}, [r4:128], r6 @ encoding: [0x24,0xf9,0x26,0x0a]<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted<br>
+@ CHECK-ERRORS: vld1.8 {d0, d1}, [r4:256], r6<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vld1.8 {d0, d1, d2}, [r4]<br>
+ vld1.8 {d0, d1, d2}, [r4:16]<br>
+ vld1.8 {d0, d1, d2}, [r4:32]<br>
+ vld1.8 {d0, d1, d2}, [r4:64]<br>
+ vld1.8 {d0, d1, d2}, [r4:128]<br>
+ vld1.8 {d0, d1, d2}, [r4:256]<br>
+<br>
+@ CHECK: vld1.8 {d0, d1, d2}, [r4] @ encoding: [0x24,0xf9,0x0f,0x06]<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vld1.8 {d0, d1, d2}, [r4:16]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vld1.8 {d0, d1, d2}, [r4:32]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vld1.8 {d0, d1, d2}, [r4:64] @ encoding: [0x24,0xf9,0x1f,0x06]<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vld1.8 {d0, d1, d2}, [r4:128]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vld1.8 {d0, d1, d2}, [r4:256]<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vld1.8 {d0, d1, d2}, [r4]!<br>
+ vld1.8 {d0, d1, d2}, [r4:16]!<br>
+ vld1.8 {d0, d1, d2}, [r4:32]!<br>
+ vld1.8 {d0, d1, d2}, [r4:64]!<br>
+ vld1.8 {d0, d1, d2}, [r4:128]!<br>
+ vld1.8 {d0, d1, d2}, [r4:256]!<br>
+<br>
+@ CHECK: vld1.8 {d0, d1, d2}, [r4]! @ encoding: [0x24,0xf9,0x0d,0x06]<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vld1.8 {d0, d1, d2}, [r4:16]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vld1.8 {d0, d1, d2}, [r4:32]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vld1.8 {d0, d1, d2}, [r4:64]! @ encoding: [0x24,0xf9,0x1d,0x06]<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vld1.8 {d0, d1, d2}, [r4:128]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vld1.8 {d0, d1, d2}, [r4:256]!<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vld1.8 {d0, d1, d2}, [r4], r6<br>
+ vld1.8 {d0, d1, d2}, [r4:16], r6<br>
+ vld1.8 {d0, d1, d2}, [r4:32], r6<br>
+ vld1.8 {d0, d1, d2}, [r4:64], r6<br>
+ vld1.8 {d0, d1, d2}, [r4:128], r6<br>
+ vld1.8 {d0, d1, d2}, [r4:256], r6<br>
+<br>
+@ CHECK: vld1.8 {d0, d1, d2}, [r4], r6 @ encoding: [0x24,0xf9,0x06,0x06]<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vld1.8 {d0, d1, d2}, [r4:16], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vld1.8 {d0, d1, d2}, [r4:32], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vld1.8 {d0, d1, d2}, [r4:64], r6 @ encoding: [0x24,0xf9,0x16,0x06]<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vld1.8 {d0, d1, d2}, [r4:128], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vld1.8 {d0, d1, d2}, [r4:256], r6<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vld1.8 {d0, d1, d2, d3}, [r4]<br>
+ vld1.8 {d0, d1, d2, d3}, [r4:16]<br>
+ vld1.8 {d0, d1, d2, d3}, [r4:32]<br>
+ vld1.8 {d0, d1, d2, d3}, [r4:64]<br>
+ vld1.8 {d0, d1, d2, d3}, [r4:128]<br>
+ vld1.8 {d0, d1, d2, d3}, [r4:256]<br>
+<br>
+@ CHECK: vld1.8 {d0, d1, d2, d3}, [r4] @ encoding: [0x24,0xf9,0x0f,0x02]<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted<br>
+@ CHECK-ERRORS: vld1.8 {d0, d1, d2, d3}, [r4:16]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted<br>
+@ CHECK-ERRORS: vld1.8 {d0, d1, d2, d3}, [r4:32]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vld1.8 {d0, d1, d2, d3}, [r4:64] @ encoding: [0x24,0xf9,0x1f,0x02]<br>
+@ CHECK: vld1.8 {d0, d1, d2, d3}, [r4:128] @ encoding: [0x24,0xf9,0x2f,0x02]<br>
+@ CHECK: vld1.8 {d0, d1, d2, d3}, [r4:256] @ encoding: [0x24,0xf9,0x3f,0x02]<br>
+<br>
+ vld1.8 {d0, d1, d2, d3}, [r4]!<br>
+ vld1.8 {d0, d1, d2, d3}, [r4:16]!<br>
+ vld1.8 {d0, d1, d2, d3}, [r4:32]!<br>
+ vld1.8 {d0, d1, d2, d3}, [r4:64]!<br>
+ vld1.8 {d0, d1, d2, d3}, [r4:128]!<br>
+ vld1.8 {d0, d1, d2, d3}, [r4:256]!<br>
+<br>
+@ CHECK: vld1.8 {d0, d1, d2, d3}, [r4]! @ encoding: [0x24,0xf9,0x0d,0x02]<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted<br>
+@ CHECK-ERRORS: vld1.8 {d0, d1, d2, d3}, [r4:16]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted<br>
+@ CHECK-ERRORS: vld1.8 {d0, d1, d2, d3}, [r4:32]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vld1.8 {d0, d1, d2, d3}, [r4:64]! @ encoding: [0x24,0xf9,0x1d,0x02]<br>
+@ CHECK: vld1.8 {d0, d1, d2, d3}, [r4:128]! @ encoding: [0x24,0xf9,0x2d,0x02]<br>
+@ CHECK: vld1.8 {d0, d1, d2, d3}, [r4:256]! @ encoding: [0x24,0xf9,0x3d,0x02]<br>
+<br>
+ vld1.8 {d0, d1, d2, d3}, [r4], r6<br>
+ vld1.8 {d0, d1, d2, d3}, [r4:16], r6<br>
+ vld1.8 {d0, d1, d2, d3}, [r4:32], r6<br>
+ vld1.8 {d0, d1, d2, d3}, [r4:64], r6<br>
+ vld1.8 {d0, d1, d2, d3}, [r4:128], r6<br>
+ vld1.8 {d0, d1, d2, d3}, [r4:256], r6<br>
+<br>
+@ CHECK: vld1.8 {d0, d1, d2, d3}, [r4], r6 @ encoding: [0x24,0xf9,0x06,0x02]<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted<br>
+@ CHECK-ERRORS: vld1.8 {d0, d1, d2, d3}, [r4:16], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted<br>
+@ CHECK-ERRORS: vld1.8 {d0, d1, d2, d3}, [r4:32], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vld1.8 {d0, d1, d2, d3}, [r4:64], r6 @ encoding: [0x24,0xf9,0x16,0x02]<br>
+@ CHECK: vld1.8 {d0, d1, d2, d3}, [r4:128], r6 @ encoding: [0x24,0xf9,0x26,0x02]<br>
+@ CHECK: vld1.8 {d0, d1, d2, d3}, [r4:256], r6 @ encoding: [0x24,0xf9,0x36,0x02]<br>
+<br>
+ vld1.8 {d0[2]}, [r4]<br>
+ vld1.8 {d0[2]}, [r4:16]<br>
+ vld1.8 {d0[2]}, [r4:32]<br>
+ vld1.8 {d0[2]}, [r4:64]<br>
+ vld1.8 {d0[2]}, [r4:128]<br>
+ vld1.8 {d0[2]}, [r4:256]<br>
+<br>
+@ CHECK: vld1.8 {d0[2]}, [r4] @ encoding: [0xa4,0xf9,0x4f,0x00]<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vld1.8 {d0[2]}, [r4:16]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vld1.8 {d0[2]}, [r4:32]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vld1.8 {d0[2]}, [r4:64]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vld1.8 {d0[2]}, [r4:128]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vld1.8 {d0[2]}, [r4:256]<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vld1.8 {d0[2]}, [r4]!<br>
+ vld1.8 {d0[2]}, [r4:16]!<br>
+ vld1.8 {d0[2]}, [r4:32]!<br>
+ vld1.8 {d0[2]}, [r4:64]!<br>
+ vld1.8 {d0[2]}, [r4:128]!<br>
+ vld1.8 {d0[2]}, [r4:256]!<br>
+<br>
+@ CHECK: vld1.8 {d0[2]}, [r4]! @ encoding: [0xa4,0xf9,0x4d,0x00]<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vld1.8 {d0[2]}, [r4:16]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vld1.8 {d0[2]}, [r4:32]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vld1.8 {d0[2]}, [r4:64]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vld1.8 {d0[2]}, [r4:128]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vld1.8 {d0[2]}, [r4:256]!<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vld1.8 {d0[2]}, [r4], r6<br>
+ vld1.8 {d0[2]}, [r4:16], r6<br>
+ vld1.8 {d0[2]}, [r4:32], r6<br>
+ vld1.8 {d0[2]}, [r4:64], r6<br>
+ vld1.8 {d0[2]}, [r4:128], r6<br>
+ vld1.8 {d0[2]}, [r4:256], r6<br>
+<br>
+@ CHECK: vld1.8 {d0[2]}, [r4], r6 @ encoding: [0xa4,0xf9,0x46,0x00]<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vld1.8 {d0[2]}, [r4:16], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vld1.8 {d0[2]}, [r4:32], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vld1.8 {d0[2]}, [r4:64], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vld1.8 {d0[2]}, [r4:128], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vld1.8 {d0[2]}, [r4:256], r6<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vld1.8 {d0[]}, [r4]<br>
+ vld1.8 {d0[]}, [r4:16]<br>
+ vld1.8 {d0[]}, [r4:32]<br>
+ vld1.8 {d0[]}, [r4:64]<br>
+ vld1.8 {d0[]}, [r4:128]<br>
+ vld1.8 {d0[]}, [r4:256]<br>
+<br>
+@ CHECK: vld1.8 {d0[]}, [r4] @ encoding: [0xa4,0xf9,0x0f,0x0c]<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vld1.8 {d0[]}, [r4:16]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vld1.8 {d0[]}, [r4:32]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vld1.8 {d0[]}, [r4:64]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vld1.8 {d0[]}, [r4:128]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vld1.8 {d0[]}, [r4:256]<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vld1.8 {d0[]}, [r4]!<br>
+ vld1.8 {d0[]}, [r4:16]!<br>
+ vld1.8 {d0[]}, [r4:32]!<br>
+ vld1.8 {d0[]}, [r4:64]!<br>
+ vld1.8 {d0[]}, [r4:128]!<br>
+ vld1.8 {d0[]}, [r4:256]!<br>
+<br>
+@ CHECK: vld1.8 {d0[]}, [r4]! @ encoding: [0xa4,0xf9,0x0d,0x0c]<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vld1.8 {d0[]}, [r4:16]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vld1.8 {d0[]}, [r4:32]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vld1.8 {d0[]}, [r4:64]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vld1.8 {d0[]}, [r4:128]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vld1.8 {d0[]}, [r4:256]!<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vld1.8 {d0[]}, [r4], r6<br>
+ vld1.8 {d0[]}, [r4:16], r6<br>
+ vld1.8 {d0[]}, [r4:32], r6<br>
+ vld1.8 {d0[]}, [r4:64], r6<br>
+ vld1.8 {d0[]}, [r4:128], r6<br>
+ vld1.8 {d0[]}, [r4:256], r6<br>
+<br>
+@ CHECK: vld1.8 {d0[]}, [r4], r6 @ encoding: [0xa4,0xf9,0x06,0x0c]<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vld1.8 {d0[]}, [r4:16], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vld1.8 {d0[]}, [r4:32], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vld1.8 {d0[]}, [r4:64], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vld1.8 {d0[]}, [r4:128], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vld1.8 {d0[]}, [r4:256], r6<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vld1.8 {d0[], d1[]}, [r4]<br>
+ vld1.8 {d0[], d1[]}, [r4:16]<br>
+ vld1.8 {d0[], d1[]}, [r4:32]<br>
+ vld1.8 {d0[], d1[]}, [r4:64]<br>
+ vld1.8 {d0[], d1[]}, [r4:128]<br>
+ vld1.8 {d0[], d1[]}, [r4:256]<br>
+<br>
+@ CHECK: vld1.8 {d0[], d1[]}, [r4] @ encoding: [0xa4,0xf9,0x2f,0x0c]<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vld1.8 {d0[], d1[]}, [r4:16]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vld1.8 {d0[], d1[]}, [r4:32]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vld1.8 {d0[], d1[]}, [r4:64]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vld1.8 {d0[], d1[]}, [r4:128]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vld1.8 {d0[], d1[]}, [r4:256]<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vld1.8 {d0[], d1[]}, [r4]!<br>
+ vld1.8 {d0[], d1[]}, [r4:16]!<br>
+ vld1.8 {d0[], d1[]}, [r4:32]!<br>
+ vld1.8 {d0[], d1[]}, [r4:64]!<br>
+ vld1.8 {d0[], d1[]}, [r4:128]!<br>
+ vld1.8 {d0[], d1[]}, [r4:256]!<br>
+<br>
+@ CHECK: vld1.8 {d0[], d1[]}, [r4]! @ encoding: [0xa4,0xf9,0x2d,0x0c]<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vld1.8 {d0[], d1[]}, [r4:16]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vld1.8 {d0[], d1[]}, [r4:32]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vld1.8 {d0[], d1[]}, [r4:64]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vld1.8 {d0[], d1[]}, [r4:128]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vld1.8 {d0[], d1[]}, [r4:256]!<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vld1.8 {d0[], d1[]}, [r4], r6<br>
+ vld1.8 {d0[], d1[]}, [r4:16], r6<br>
+ vld1.8 {d0[], d1[]}, [r4:32], r6<br>
+ vld1.8 {d0[], d1[]}, [r4:64], r6<br>
+ vld1.8 {d0[], d1[]}, [r4:128], r6<br>
+ vld1.8 {d0[], d1[]}, [r4:256], r6<br>
+<br>
+@ CHECK: vld1.8 {d0[], d1[]}, [r4], r6 @ encoding: [0xa4,0xf9,0x26,0x0c]<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vld1.8 {d0[], d1[]}, [r4:16], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vld1.8 {d0[], d1[]}, [r4:32], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vld1.8 {d0[], d1[]}, [r4:64], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vld1.8 {d0[], d1[]}, [r4:128], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vld1.8 {d0[], d1[]}, [r4:256], r6<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vld1.16 {d0}, [r4]<br>
+ vld1.16 {d0}, [r4:16]<br>
+ vld1.16 {d0}, [r4:32]<br>
+ vld1.16 {d0}, [r4:64]<br>
+ vld1.16 {d0}, [r4:128]<br>
+ vld1.16 {d0}, [r4:256]<br>
+<br>
+@ CHECK: vld1.16 {d0}, [r4] @ encoding: [0x24,0xf9,0x4f,0x07]<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vld1.16 {d0}, [r4:16]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vld1.16 {d0}, [r4:32]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vld1.16 {d0}, [r4:64] @ encoding: [0x24,0xf9,0x5f,0x07]<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vld1.16 {d0}, [r4:128]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vld1.16 {d0}, [r4:256]<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vld1.16 {d0}, [r4]!<br>
+ vld1.16 {d0}, [r4:16]!<br>
+ vld1.16 {d0}, [r4:32]!<br>
+ vld1.16 {d0}, [r4:64]!<br>
+ vld1.16 {d0}, [r4:128]!<br>
+ vld1.16 {d0}, [r4:256]!<br>
+<br>
+@ CHECK: vld1.16 {d0}, [r4]! @ encoding: [0x24,0xf9,0x4d,0x07]<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vld1.16 {d0}, [r4:16]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vld1.16 {d0}, [r4:32]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vld1.16 {d0}, [r4:64]! @ encoding: [0x24,0xf9,0x5d,0x07]<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vld1.16 {d0}, [r4:128]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vld1.16 {d0}, [r4:256]!<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vld1.16 {d0}, [r4], r6<br>
+ vld1.16 {d0}, [r4:16], r6<br>
+ vld1.16 {d0}, [r4:32], r6<br>
+ vld1.16 {d0}, [r4:64], r6<br>
+ vld1.16 {d0}, [r4:128], r6<br>
+ vld1.16 {d0}, [r4:256], r6<br>
+<br>
+@ CHECK: vld1.16 {d0}, [r4], r6 @ encoding: [0x24,0xf9,0x46,0x07]<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vld1.16 {d0}, [r4:16], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vld1.16 {d0}, [r4:32], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vld1.16 {d0}, [r4:64], r6 @ encoding: [0x24,0xf9,0x56,0x07]<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vld1.16 {d0}, [r4:128], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vld1.16 {d0}, [r4:256], r6<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vld1.16 {d0, d1}, [r4]<br>
+ vld1.16 {d0, d1}, [r4:16]<br>
+ vld1.16 {d0, d1}, [r4:32]<br>
+ vld1.16 {d0, d1}, [r4:64]<br>
+ vld1.16 {d0, d1}, [r4:128]<br>
+ vld1.16 {d0, d1}, [r4:256]<br>
+<br>
+@ CHECK: vld1.16 {d0, d1}, [r4] @ encoding: [0x24,0xf9,0x4f,0x0a]<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted<br>
+@ CHECK-ERRORS: vld1.16 {d0, d1}, [r4:16]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted<br>
+@ CHECK-ERRORS: vld1.16 {d0, d1}, [r4:32]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vld1.16 {d0, d1}, [r4:64] @ encoding: [0x24,0xf9,0x5f,0x0a]<br>
+@ CHECK: vld1.16 {d0, d1}, [r4:128] @ encoding: [0x24,0xf9,0x6f,0x0a]<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted<br>
+@ CHECK-ERRORS: vld1.16 {d0, d1}, [r4:256]<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vld1.16 {d0, d1}, [r4]!<br>
+ vld1.16 {d0, d1}, [r4:16]!<br>
+ vld1.16 {d0, d1}, [r4:32]!<br>
+ vld1.16 {d0, d1}, [r4:64]!<br>
+ vld1.16 {d0, d1}, [r4:128]!<br>
+ vld1.16 {d0, d1}, [r4:256]!<br>
+<br>
+@ CHECK: vld1.16 {d0, d1}, [r4]! @ encoding: [0x24,0xf9,0x4d,0x0a]<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted<br>
+@ CHECK-ERRORS: vld1.16 {d0, d1}, [r4:16]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted<br>
+@ CHECK-ERRORS: vld1.16 {d0, d1}, [r4:32]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vld1.16 {d0, d1}, [r4:64]! @ encoding: [0x24,0xf9,0x5d,0x0a]<br>
+@ CHECK: vld1.16 {d0, d1}, [r4:128]! @ encoding: [0x24,0xf9,0x6d,0x0a]<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted<br>
+@ CHECK-ERRORS: vld1.16 {d0, d1}, [r4:256]!<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vld1.16 {d0, d1}, [r4], r6<br>
+ vld1.16 {d0, d1}, [r4:16], r6<br>
+ vld1.16 {d0, d1}, [r4:32], r6<br>
+ vld1.16 {d0, d1}, [r4:64], r6<br>
+ vld1.16 {d0, d1}, [r4:128], r6<br>
+ vld1.16 {d0, d1}, [r4:256], r6<br>
+<br>
+@ CHECK: vld1.16 {d0, d1}, [r4], r6 @ encoding: [0x24,0xf9,0x46,0x0a]<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted<br>
+@ CHECK-ERRORS: vld1.16 {d0, d1}, [r4:16], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted<br>
+@ CHECK-ERRORS: vld1.16 {d0, d1}, [r4:32], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vld1.16 {d0, d1}, [r4:64], r6 @ encoding: [0x24,0xf9,0x56,0x0a]<br>
+@ CHECK: vld1.16 {d0, d1}, [r4:128], r6 @ encoding: [0x24,0xf9,0x66,0x0a]<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted<br>
+@ CHECK-ERRORS: vld1.16 {d0, d1}, [r4:256], r6<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vld1.16 {d0, d1, d2}, [r4]<br>
+ vld1.16 {d0, d1, d2}, [r4:16]<br>
+ vld1.16 {d0, d1, d2}, [r4:32]<br>
+ vld1.16 {d0, d1, d2}, [r4:64]<br>
+ vld1.16 {d0, d1, d2}, [r4:128]<br>
+ vld1.16 {d0, d1, d2}, [r4:256]<br>
+<br>
+@ CHECK: vld1.16 {d0, d1, d2}, [r4] @ encoding: [0x24,0xf9,0x4f,0x06]<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vld1.16 {d0, d1, d2}, [r4:16]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vld1.16 {d0, d1, d2}, [r4:32]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vld1.16 {d0, d1, d2}, [r4:64] @ encoding: [0x24,0xf9,0x5f,0x06]<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vld1.16 {d0, d1, d2}, [r4:128]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vld1.16 {d0, d1, d2}, [r4:256]<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vld1.16 {d0, d1, d2}, [r4]!<br>
+ vld1.16 {d0, d1, d2}, [r4:16]!<br>
+ vld1.16 {d0, d1, d2}, [r4:32]!<br>
+ vld1.16 {d0, d1, d2}, [r4:64]!<br>
+ vld1.16 {d0, d1, d2}, [r4:128]!<br>
+ vld1.16 {d0, d1, d2}, [r4:256]!<br>
+<br>
+@ CHECK: vld1.16 {d0, d1, d2}, [r4]! @ encoding: [0x24,0xf9,0x4d,0x06]<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vld1.16 {d0, d1, d2}, [r4:16]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vld1.16 {d0, d1, d2}, [r4:32]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vld1.16 {d0, d1, d2}, [r4:64]! @ encoding: [0x24,0xf9,0x5d,0x06]<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vld1.16 {d0, d1, d2}, [r4:128]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vld1.16 {d0, d1, d2}, [r4:256]!<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vld1.16 {d0, d1, d2}, [r4], r6<br>
+ vld1.16 {d0, d1, d2}, [r4:16], r6<br>
+ vld1.16 {d0, d1, d2}, [r4:32], r6<br>
+ vld1.16 {d0, d1, d2}, [r4:64], r6<br>
+ vld1.16 {d0, d1, d2}, [r4:128], r6<br>
+ vld1.16 {d0, d1, d2}, [r4:256], r6<br>
+<br>
+@ CHECK: vld1.16 {d0, d1, d2}, [r4], r6 @ encoding: [0x24,0xf9,0x46,0x06]<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vld1.16 {d0, d1, d2}, [r4:16], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vld1.16 {d0, d1, d2}, [r4:32], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vld1.16 {d0, d1, d2}, [r4:64], r6 @ encoding: [0x24,0xf9,0x56,0x06]<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vld1.16 {d0, d1, d2}, [r4:128], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vld1.16 {d0, d1, d2}, [r4:256], r6<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vld1.16 {d0, d1, d2, d3}, [r4]<br>
+ vld1.16 {d0, d1, d2, d3}, [r4:16]<br>
+ vld1.16 {d0, d1, d2, d3}, [r4:32]<br>
+ vld1.16 {d0, d1, d2, d3}, [r4:64]<br>
+ vld1.16 {d0, d1, d2, d3}, [r4:128]<br>
+ vld1.16 {d0, d1, d2, d3}, [r4:256]<br>
+<br>
+@ CHECK: vld1.16 {d0, d1, d2, d3}, [r4] @ encoding: [0x24,0xf9,0x4f,0x02]<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted<br>
+@ CHECK-ERRORS: vld1.16 {d0, d1, d2, d3}, [r4:16]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted<br>
+@ CHECK-ERRORS: vld1.16 {d0, d1, d2, d3}, [r4:32]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vld1.16 {d0, d1, d2, d3}, [r4:64] @ encoding: [0x24,0xf9,0x5f,0x02]<br>
+@ CHECK: vld1.16 {d0, d1, d2, d3}, [r4:128] @ encoding: [0x24,0xf9,0x6f,0x02]<br>
+@ CHECK: vld1.16 {d0, d1, d2, d3}, [r4:256] @ encoding: [0x24,0xf9,0x7f,0x02]<br>
+<br>
+ vld1.16 {d0, d1, d2, d3}, [r4]!<br>
+ vld1.16 {d0, d1, d2, d3}, [r4:16]!<br>
+ vld1.16 {d0, d1, d2, d3}, [r4:32]!<br>
+ vld1.16 {d0, d1, d2, d3}, [r4:64]!<br>
+ vld1.16 {d0, d1, d2, d3}, [r4:128]!<br>
+ vld1.16 {d0, d1, d2, d3}, [r4:256]!<br>
+<br>
+@ CHECK: vld1.16 {d0, d1, d2, d3}, [r4]! @ encoding: [0x24,0xf9,0x4d,0x02]<br>
+@ CHECK-ERRORS: vld1.16 {d0, d1, d2, d3}, [r4:16]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted<br>
+@ CHECK-ERRORS: vld1.16 {d0, d1, d2, d3}, [r4:32]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vld1.16 {d0, d1, d2, d3}, [r4:64]! @ encoding: [0x24,0xf9,0x5d,0x02]<br>
+@ CHECK: vld1.16 {d0, d1, d2, d3}, [r4:128]! @ encoding: [0x24,0xf9,0x6d,0x02]<br>
+@ CHECK: vld1.16 {d0, d1, d2, d3}, [r4:256]! @ encoding: [0x24,0xf9,0x7d,0x02]<br>
+<br>
+ vld1.16 {d0, d1, d2, d3}, [r4], r6<br>
+ vld1.16 {d0, d1, d2, d3}, [r4:16], r6<br>
+ vld1.16 {d0, d1, d2, d3}, [r4:32], r6<br>
+ vld1.16 {d0, d1, d2, d3}, [r4:64], r6<br>
+ vld1.16 {d0, d1, d2, d3}, [r4:128], r6<br>
+ vld1.16 {d0, d1, d2, d3}, [r4:256], r6<br>
+<br>
+@ CHECK: vld1.16 {d0, d1, d2, d3}, [r4], r6 @ encoding: [0x24,0xf9,0x46,0x02]<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted<br>
+@ CHECK-ERRORS: vld1.16 {d0, d1, d2, d3}, [r4:16], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted<br>
+@ CHECK-ERRORS: vld1.16 {d0, d1, d2, d3}, [r4:32], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vld1.16 {d0, d1, d2, d3}, [r4:64], r6 @ encoding: [0x24,0xf9,0x56,0x02]<br>
+@ CHECK: vld1.16 {d0, d1, d2, d3}, [r4:128], r6 @ encoding: [0x24,0xf9,0x66,0x02]<br>
+@ CHECK: vld1.16 {d0, d1, d2, d3}, [r4:256], r6 @ encoding: [0x24,0xf9,0x76,0x02]<br>
+<br>
+ vld1.16 {d0[2]}, [r4]<br>
+ vld1.16 {d0[2]}, [r4:16]<br>
+ vld1.16 {d0[2]}, [r4:32]<br>
+ vld1.16 {d0[2]}, [r4:64]<br>
+ vld1.16 {d0[2]}, [r4:128]<br>
+ vld1.16 {d0[2]}, [r4:256]<br>
+<br>
+@ CHECK: vld1.16 {d0[2]}, [r4] @ encoding: [0xa4,0xf9,0x8f,0x04]<br>
+@ CHECK: vld1.16 {d0[2]}, [r4:16] @ encoding: [0xa4,0xf9,0x9f,0x04]<br>
+@ CHECK-ERRORS: error: alignment must be 16 or omitted<br>
+@ CHECK-ERRORS: vld1.16 {d0[2]}, [r4:32]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 16 or omitted<br>
+@ CHECK-ERRORS: vld1.16 {d0[2]}, [r4:64]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 16 or omitted<br>
+@ CHECK-ERRORS: vld1.16 {d0[2]}, [r4:128]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 16 or omitted<br>
+@ CHECK-ERRORS: vld1.16 {d0[2]}, [r4:256]<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vld1.16 {d0[2]}, [r4]!<br>
+ vld1.16 {d0[2]}, [r4:16]!<br>
+ vld1.16 {d0[2]}, [r4:32]!<br>
+ vld1.16 {d0[2]}, [r4:64]!<br>
+ vld1.16 {d0[2]}, [r4:128]!<br>
+ vld1.16 {d0[2]}, [r4:256]!<br>
+<br>
+@ CHECK: vld1.16 {d0[2]}, [r4]! @ encoding: [0xa4,0xf9,0x8d,0x04]<br>
+@ CHECK: vld1.16 {d0[2]}, [r4:16]! @ encoding: [0xa4,0xf9,0x9d,0x04]<br>
+@ CHECK-ERRORS: error: alignment must be 16 or omitted<br>
+@ CHECK-ERRORS: vld1.16 {d0[2]}, [r4:32]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 16 or omitted<br>
+@ CHECK-ERRORS: vld1.16 {d0[2]}, [r4:64]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 16 or omitted<br>
+@ CHECK-ERRORS: vld1.16 {d0[2]}, [r4:128]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 16 or omitted<br>
+@ CHECK-ERRORS: vld1.16 {d0[2]}, [r4:256]!<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vld1.16 {d0[2]}, [r4], r6<br>
+ vld1.16 {d0[2]}, [r4:16], r6<br>
+ vld1.16 {d0[2]}, [r4:32], r6<br>
+ vld1.16 {d0[2]}, [r4:64], r6<br>
+ vld1.16 {d0[2]}, [r4:128], r6<br>
+ vld1.16 {d0[2]}, [r4:256], r6<br>
+<br>
+@ CHECK: vld1.16 {d0[2]}, [r4], r6 @ encoding: [0xa4,0xf9,0x86,0x04]<br>
+@ CHECK: vld1.16 {d0[2]}, [r4:16], r6 @ encoding: [0xa4,0xf9,0x96,0x04]<br>
+@ CHECK-ERRORS: error: alignment must be 16 or omitted<br>
+@ CHECK-ERRORS: vld1.16 {d0[2]}, [r4:32], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 16 or omitted<br>
+@ CHECK-ERRORS: vld1.16 {d0[2]}, [r4:64], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 16 or omitted<br>
+@ CHECK-ERRORS: vld1.16 {d0[2]}, [r4:128], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 16 or omitted<br>
+@ CHECK-ERRORS: vld1.16 {d0[2]}, [r4:256], r6<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vld1.16 {d0[]}, [r4]<br>
+ vld1.16 {d0[]}, [r4:16]<br>
+ vld1.16 {d0[]}, [r4:32]<br>
+ vld1.16 {d0[]}, [r4:64]<br>
+ vld1.16 {d0[]}, [r4:128]<br>
+ vld1.16 {d0[]}, [r4:256]<br>
+<br>
+@ CHECK: vld1.16 {d0[]}, [r4] @ encoding: [0xa4,0xf9,0x4f,0x0c]<br>
+@ CHECK: vld1.16 {d0[]}, [r4:16] @ encoding: [0xa4,0xf9,0x5f,0x0c]<br>
+@ CHECK-ERRORS: error: alignment must be 16 or omitted<br>
+@ CHECK-ERRORS: vld1.16 {d0[]}, [r4:32]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 16 or omitted<br>
+@ CHECK-ERRORS: vld1.16 {d0[]}, [r4:64]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 16 or omitted<br>
+@ CHECK-ERRORS: vld1.16 {d0[]}, [r4:128]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 16 or omitted<br>
+@ CHECK-ERRORS: vld1.16 {d0[]}, [r4:256]<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vld1.16 {d0[]}, [r4]!<br>
+ vld1.16 {d0[]}, [r4:16]!<br>
+ vld1.16 {d0[]}, [r4:32]!<br>
+ vld1.16 {d0[]}, [r4:64]!<br>
+ vld1.16 {d0[]}, [r4:128]!<br>
+ vld1.16 {d0[]}, [r4:256]!<br>
+<br>
+@ CHECK: vld1.16 {d0[]}, [r4]! @ encoding: [0xa4,0xf9,0x4d,0x0c]<br>
+@ CHECK: vld1.16 {d0[]}, [r4:16]! @ encoding: [0xa4,0xf9,0x5d,0x0c]<br>
+@ CHECK-ERRORS: error: alignment must be 16 or omitted<br>
+@ CHECK-ERRORS: vld1.16 {d0[]}, [r4:32]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 16 or omitted<br>
+@ CHECK-ERRORS: vld1.16 {d0[]}, [r4:64]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 16 or omitted<br>
+@ CHECK-ERRORS: vld1.16 {d0[]}, [r4:128]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 16 or omitted<br>
+@ CHECK-ERRORS: vld1.16 {d0[]}, [r4:256]!<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vld1.16 {d0[]}, [r4], r6<br>
+ vld1.16 {d0[]}, [r4:16], r6<br>
+ vld1.16 {d0[]}, [r4:32], r6<br>
+ vld1.16 {d0[]}, [r4:64], r6<br>
+ vld1.16 {d0[]}, [r4:128], r6<br>
+ vld1.16 {d0[]}, [r4:256], r6<br>
+<br>
+@ CHECK: vld1.16 {d0[]}, [r4], r6 @ encoding: [0xa4,0xf9,0x46,0x0c]<br>
+@ CHECK: vld1.16 {d0[]}, [r4:16], r6 @ encoding: [0xa4,0xf9,0x56,0x0c]<br>
+@ CHECK-ERRORS: error: alignment must be 16 or omitted<br>
+@ CHECK-ERRORS: vld1.16 {d0[]}, [r4:32], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 16 or omitted<br>
+@ CHECK-ERRORS: vld1.16 {d0[]}, [r4:64], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 16 or omitted<br>
+@ CHECK-ERRORS: vld1.16 {d0[]}, [r4:128], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 16 or omitted<br>
+@ CHECK-ERRORS: vld1.16 {d0[]}, [r4:256], r6<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vld1.16 {d0[], d1[]}, [r4]<br>
+ vld1.16 {d0[], d1[]}, [r4:16]<br>
+ vld1.16 {d0[], d1[]}, [r4:32]<br>
+ vld1.16 {d0[], d1[]}, [r4:64]<br>
+ vld1.16 {d0[], d1[]}, [r4:128]<br>
+ vld1.16 {d0[], d1[]}, [r4:256]<br>
+<br>
+@ CHECK: vld1.16 {d0[], d1[]}, [r4] @ encoding: [0xa4,0xf9,0x6f,0x0c]<br>
+@ CHECK: vld1.16 {d0[], d1[]}, [r4:16] @ encoding: [0xa4,0xf9,0x7f,0x0c]<br>
+@ CHECK-ERRORS: error: alignment must be 16 or omitted<br>
+@ CHECK-ERRORS: vld1.16 {d0[], d1[]}, [r4:32]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 16 or omitted<br>
+@ CHECK-ERRORS: vld1.16 {d0[], d1[]}, [r4:64]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 16 or omitted<br>
+@ CHECK-ERRORS: vld1.16 {d0[], d1[]}, [r4:128]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 16 or omitted<br>
+@ CHECK-ERRORS: vld1.16 {d0[], d1[]}, [r4:256]<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vld1.16 {d0[], d1[]}, [r4]!<br>
+ vld1.16 {d0[], d1[]}, [r4:16]!<br>
+ vld1.16 {d0[], d1[]}, [r4:32]!<br>
+ vld1.16 {d0[], d1[]}, [r4:64]!<br>
+ vld1.16 {d0[], d1[]}, [r4:128]!<br>
+ vld1.16 {d0[], d1[]}, [r4:256]!<br>
+<br>
+@ CHECK: vld1.16 {d0[], d1[]}, [r4]! @ encoding: [0xa4,0xf9,0x6d,0x0c]<br>
+@ CHECK: vld1.16 {d0[], d1[]}, [r4:16]! @ encoding: [0xa4,0xf9,0x7d,0x0c]<br>
+@ CHECK-ERRORS: error: alignment must be 16 or omitted<br>
+@ CHECK-ERRORS: vld1.16 {d0[], d1[]}, [r4:32]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 16 or omitted<br>
+@ CHECK-ERRORS: vld1.16 {d0[], d1[]}, [r4:64]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 16 or omitted<br>
+@ CHECK-ERRORS: vld1.16 {d0[], d1[]}, [r4:128]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 16 or omitted<br>
+@ CHECK-ERRORS: vld1.16 {d0[], d1[]}, [r4:256]!<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vld1.16 {d0[], d1[]}, [r4], r6<br>
+ vld1.16 {d0[], d1[]}, [r4:16], r6<br>
+ vld1.16 {d0[], d1[]}, [r4:32], r6<br>
+ vld1.16 {d0[], d1[]}, [r4:64], r6<br>
+ vld1.16 {d0[], d1[]}, [r4:128], r6<br>
+ vld1.16 {d0[], d1[]}, [r4:256], r6<br>
+<br>
+@ CHECK: vld1.16 {d0[], d1[]}, [r4], r6 @ encoding: [0xa4,0xf9,0x66,0x0c]<br>
+@ CHECK: vld1.16 {d0[], d1[]}, [r4:16], r6 @ encoding: [0xa4,0xf9,0x76,0x0c]<br>
+@ CHECK-ERRORS: error: alignment must be 16 or omitted<br>
+@ CHECK-ERRORS: vld1.16 {d0[], d1[]}, [r4:32], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 16 or omitted<br>
+@ CHECK-ERRORS: vld1.16 {d0[], d1[]}, [r4:64], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 16 or omitted<br>
+@ CHECK-ERRORS: vld1.16 {d0[], d1[]}, [r4:128], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 16 or omitted<br>
+@ CHECK-ERRORS: vld1.16 {d0[], d1[]}, [r4:256], r6<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vld1.32 {d0}, [r4]<br>
+ vld1.32 {d0}, [r4:16]<br>
+ vld1.32 {d0}, [r4:32]<br>
+ vld1.32 {d0}, [r4:64]<br>
+ vld1.32 {d0}, [r4:128]<br>
+ vld1.32 {d0}, [r4:256]<br>
+<br>
+@ CHECK: vld1.32 {d0}, [r4] @ encoding: [0x24,0xf9,0x8f,0x07]<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vld1.32 {d0}, [r4:16]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vld1.32 {d0}, [r4:32]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vld1.32 {d0}, [r4:64] @ encoding: [0x24,0xf9,0x9f,0x07]<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vld1.32 {d0}, [r4:128]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vld1.32 {d0}, [r4:256]<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vld1.32 {d0}, [r4]!<br>
+ vld1.32 {d0}, [r4:16]!<br>
+ vld1.32 {d0}, [r4:32]!<br>
+ vld1.32 {d0}, [r4:64]!<br>
+ vld1.32 {d0}, [r4:128]!<br>
+ vld1.32 {d0}, [r4:256]!<br>
+<br>
+@ CHECK: vld1.32 {d0}, [r4]! @ encoding: [0x24,0xf9,0x8d,0x07]<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vld1.32 {d0}, [r4:16]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vld1.32 {d0}, [r4:32]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vld1.32 {d0}, [r4:64]! @ encoding: [0x24,0xf9,0x9d,0x07]<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vld1.32 {d0}, [r4:128]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vld1.32 {d0}, [r4:256]!<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vld1.32 {d0}, [r4], r6<br>
+ vld1.32 {d0}, [r4:16], r6<br>
+ vld1.32 {d0}, [r4:32], r6<br>
+ vld1.32 {d0}, [r4:64], r6<br>
+ vld1.32 {d0}, [r4:128], r6<br>
+ vld1.32 {d0}, [r4:256], r6<br>
+<br>
+@ CHECK: vld1.32 {d0}, [r4], r6 @ encoding: [0x24,0xf9,0x86,0x07]<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vld1.32 {d0}, [r4:16], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vld1.32 {d0}, [r4:32], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vld1.32 {d0}, [r4:64], r6 @ encoding: [0x24,0xf9,0x96,0x07]<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vld1.32 {d0}, [r4:128], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vld1.32 {d0}, [r4:256], r6<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vld1.32 {d0, d1}, [r4]<br>
+ vld1.32 {d0, d1}, [r4:16]<br>
+ vld1.32 {d0, d1}, [r4:32]<br>
+ vld1.32 {d0, d1}, [r4:64]<br>
+ vld1.32 {d0, d1}, [r4:128]<br>
+ vld1.32 {d0, d1}, [r4:256]<br>
+<br>
+@ CHECK: vld1.32 {d0, d1}, [r4] @ encoding: [0x24,0xf9,0x8f,0x0a]<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted<br>
+@ CHECK-ERRORS: vld1.32 {d0, d1}, [r4:16]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted<br>
+@ CHECK-ERRORS: vld1.32 {d0, d1}, [r4:32]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vld1.32 {d0, d1}, [r4:64] @ encoding: [0x24,0xf9,0x9f,0x0a]<br>
+@ CHECK: vld1.32 {d0, d1}, [r4:128] @ encoding: [0x24,0xf9,0xaf,0x0a]<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted<br>
+@ CHECK-ERRORS: vld1.32 {d0, d1}, [r4:256]<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vld1.32 {d0, d1}, [r4]!<br>
+ vld1.32 {d0, d1}, [r4:16]!<br>
+ vld1.32 {d0, d1}, [r4:32]!<br>
+ vld1.32 {d0, d1}, [r4:64]!<br>
+ vld1.32 {d0, d1}, [r4:128]!<br>
+ vld1.32 {d0, d1}, [r4:256]!<br>
+<br>
+@ CHECK: vld1.32 {d0, d1}, [r4]! @ encoding: [0x24,0xf9,0x8d,0x0a]<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted<br>
+@ CHECK-ERRORS: vld1.32 {d0, d1}, [r4:16]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted<br>
+@ CHECK-ERRORS: vld1.32 {d0, d1}, [r4:32]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vld1.32 {d0, d1}, [r4:64]! @ encoding: [0x24,0xf9,0x9d,0x0a]<br>
+@ CHECK: vld1.32 {d0, d1}, [r4:128]! @ encoding: [0x24,0xf9,0xad,0x0a]<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted<br>
+@ CHECK-ERRORS: vld1.32 {d0, d1}, [r4:256]!<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vld1.32 {d0, d1}, [r4], r6<br>
+ vld1.32 {d0, d1}, [r4:16], r6<br>
+ vld1.32 {d0, d1}, [r4:32], r6<br>
+ vld1.32 {d0, d1}, [r4:64], r6<br>
+ vld1.32 {d0, d1}, [r4:128], r6<br>
+ vld1.32 {d0, d1}, [r4:256], r6<br>
+<br>
+@ CHECK: vld1.32 {d0, d1}, [r4], r6 @ encoding: [0x24,0xf9,0x86,0x0a]<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted<br>
+@ CHECK-ERRORS: vld1.32 {d0, d1}, [r4:16], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted<br>
+@ CHECK-ERRORS: vld1.32 {d0, d1}, [r4:32], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vld1.32 {d0, d1}, [r4:64], r6 @ encoding: [0x24,0xf9,0x96,0x0a]<br>
+@ CHECK: vld1.32 {d0, d1}, [r4:128], r6 @ encoding: [0x24,0xf9,0xa6,0x0a]<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted<br>
+@ CHECK-ERRORS: vld1.32 {d0, d1}, [r4:256], r6<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vld1.32 {d0, d1, d2}, [r4]<br>
+ vld1.32 {d0, d1, d2}, [r4:16]<br>
+ vld1.32 {d0, d1, d2}, [r4:32]<br>
+ vld1.32 {d0, d1, d2}, [r4:64]<br>
+ vld1.32 {d0, d1, d2}, [r4:128]<br>
+ vld1.32 {d0, d1, d2}, [r4:256]<br>
+<br>
+@ CHECK: vld1.32 {d0, d1, d2}, [r4] @ encoding: [0x24,0xf9,0x8f,0x06]<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vld1.32 {d0, d1, d2}, [r4:16]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vld1.32 {d0, d1, d2}, [r4:32]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vld1.32 {d0, d1, d2}, [r4:64] @ encoding: [0x24,0xf9,0x9f,0x06]<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vld1.32 {d0, d1, d2}, [r4:128]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vld1.32 {d0, d1, d2}, [r4:256]<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vld1.32 {d0, d1, d2}, [r4]!<br>
+ vld1.32 {d0, d1, d2}, [r4:16]!<br>
+ vld1.32 {d0, d1, d2}, [r4:32]!<br>
+ vld1.32 {d0, d1, d2}, [r4:64]!<br>
+ vld1.32 {d0, d1, d2}, [r4:128]!<br>
+ vld1.32 {d0, d1, d2}, [r4:256]!<br>
+<br>
+@ CHECK: vld1.32 {d0, d1, d2}, [r4]! @ encoding: [0x24,0xf9,0x8d,0x06]<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vld1.32 {d0, d1, d2}, [r4:16]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vld1.32 {d0, d1, d2}, [r4:32]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vld1.32 {d0, d1, d2}, [r4:64]! @ encoding: [0x24,0xf9,0x9d,0x06]<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vld1.32 {d0, d1, d2}, [r4:128]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vld1.32 {d0, d1, d2}, [r4:256]!<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vld1.32 {d0, d1, d2}, [r4], r6<br>
+ vld1.32 {d0, d1, d2}, [r4:16], r6<br>
+ vld1.32 {d0, d1, d2}, [r4:32], r6<br>
+ vld1.32 {d0, d1, d2}, [r4:64], r6<br>
+ vld1.32 {d0, d1, d2}, [r4:128], r6<br>
+ vld1.32 {d0, d1, d2}, [r4:256], r6<br>
+<br>
+@ CHECK: vld1.32 {d0, d1, d2}, [r4], r6 @ encoding: [0x24,0xf9,0x86,0x06]<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vld1.32 {d0, d1, d2}, [r4:16], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vld1.32 {d0, d1, d2}, [r4:32], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vld1.32 {d0, d1, d2}, [r4:64], r6 @ encoding: [0x24,0xf9,0x96,0x06]<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vld1.32 {d0, d1, d2}, [r4:128], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vld1.32 {d0, d1, d2}, [r4:256], r6<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vld1.32 {d0, d1, d2, d3}, [r4]<br>
+ vld1.32 {d0, d1, d2, d3}, [r4:16]<br>
+ vld1.32 {d0, d1, d2, d3}, [r4:32]<br>
+ vld1.32 {d0, d1, d2, d3}, [r4:64]<br>
+ vld1.32 {d0, d1, d2, d3}, [r4:128]<br>
+ vld1.32 {d0, d1, d2, d3}, [r4:256]<br>
+<br>
+@ CHECK: vld1.32 {d0, d1, d2, d3}, [r4] @ encoding: [0x24,0xf9,0x8f,0x02]<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted<br>
+@ CHECK-ERRORS: vld1.32 {d0, d1, d2, d3}, [r4:16]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted<br>
+@ CHECK-ERRORS: vld1.32 {d0, d1, d2, d3}, [r4:32]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vld1.32 {d0, d1, d2, d3}, [r4:64] @ encoding: [0x24,0xf9,0x9f,0x02]<br>
+@ CHECK: vld1.32 {d0, d1, d2, d3}, [r4:128] @ encoding: [0x24,0xf9,0xaf,0x02]<br>
+@ CHECK: vld1.32 {d0, d1, d2, d3}, [r4:256] @ encoding: [0x24,0xf9,0xbf,0x02]<br>
+<br>
+ vld1.32 {d0, d1, d2, d3}, [r4]!<br>
+ vld1.32 {d0, d1, d2, d3}, [r4:16]!<br>
+ vld1.32 {d0, d1, d2, d3}, [r4:32]!<br>
+ vld1.32 {d0, d1, d2, d3}, [r4:64]!<br>
+ vld1.32 {d0, d1, d2, d3}, [r4:128]!<br>
+ vld1.32 {d0, d1, d2, d3}, [r4:256]!<br>
+<br>
+@ CHECK: vld1.32 {d0, d1, d2, d3}, [r4]! @ encoding: [0x24,0xf9,0x8d,0x02]<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted<br>
+@ CHECK-ERRORS: vld1.32 {d0, d1, d2, d3}, [r4:16]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted<br>
+@ CHECK-ERRORS: vld1.32 {d0, d1, d2, d3}, [r4:32]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vld1.32 {d0, d1, d2, d3}, [r4:64]! @ encoding: [0x24,0xf9,0x9d,0x02]<br>
+@ CHECK: vld1.32 {d0, d1, d2, d3}, [r4:128]! @ encoding: [0x24,0xf9,0xad,0x02]<br>
+@ CHECK: vld1.32 {d0, d1, d2, d3}, [r4:256]! @ encoding: [0x24,0xf9,0xbd,0x02]<br>
+<br>
+ vld1.32 {d0, d1, d2, d3}, [r4], r6<br>
+ vld1.32 {d0, d1, d2, d3}, [r4:16], r6<br>
+ vld1.32 {d0, d1, d2, d3}, [r4:32], r6<br>
+ vld1.32 {d0, d1, d2, d3}, [r4:64], r6<br>
+ vld1.32 {d0, d1, d2, d3}, [r4:128], r6<br>
+ vld1.32 {d0, d1, d2, d3}, [r4:256], r6<br>
+<br>
+@ CHECK: vld1.32 {d0, d1, d2, d3}, [r4], r6 @ encoding: [0x24,0xf9,0x86,0x02]<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted<br>
+@ CHECK-ERRORS: vld1.32 {d0, d1, d2, d3}, [r4:16], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted<br>
+@ CHECK-ERRORS: vld1.32 {d0, d1, d2, d3}, [r4:32], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vld1.32 {d0, d1, d2, d3}, [r4:64], r6 @ encoding: [0x24,0xf9,0x96,0x02]<br>
+@ CHECK: vld1.32 {d0, d1, d2, d3}, [r4:128], r6 @ encoding: [0x24,0xf9,0xa6,0x02]<br>
+@ CHECK: vld1.32 {d0, d1, d2, d3}, [r4:256], r6 @ encoding: [0x24,0xf9,0xb6,0x02]<br>
+<br>
+ vld1.32 {d0[1]}, [r4]<br>
+ vld1.32 {d0[1]}, [r4:16]<br>
+ vld1.32 {d0[1]}, [r4:32]<br>
+ vld1.32 {d0[1]}, [r4:64]<br>
+ vld1.32 {d0[1]}, [r4:128]<br>
+ vld1.32 {d0[1]}, [r4:256]<br>
+<br>
+@ CHECK: vld1.32 {d0[1]}, [r4] @ encoding: [0xa4,0xf9,0x8f,0x08]<br>
+@ CHECK-ERRORS: error: alignment must be 32 or omitted<br>
+@ CHECK-ERRORS: vld1.32 {d0[1]}, [r4:16]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vld1.32 {d0[1]}, [r4:32] @ encoding: [0xa4,0xf9,0xbf,0x08]<br>
+@ CHECK-ERRORS: error: alignment must be 32 or omitted<br>
+@ CHECK-ERRORS: vld1.32 {d0[1]}, [r4:64]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 32 or omitted<br>
+@ CHECK-ERRORS: vld1.32 {d0[1]}, [r4:128]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 32 or omitted<br>
+@ CHECK-ERRORS: vld1.32 {d0[1]}, [r4:256]<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vld1.32 {d0[1]}, [r4]!<br>
+ vld1.32 {d0[1]}, [r4:16]!<br>
+ vld1.32 {d0[1]}, [r4:32]!<br>
+ vld1.32 {d0[1]}, [r4:64]!<br>
+ vld1.32 {d0[1]}, [r4:128]!<br>
+ vld1.32 {d0[1]}, [r4:256]!<br>
+<br>
+@ CHECK: vld1.32 {d0[1]}, [r4]! @ encoding: [0xa4,0xf9,0x8d,0x08]<br>
+@ CHECK-ERRORS: error: alignment must be 32 or omitted<br>
+@ CHECK-ERRORS: vld1.32 {d0[1]}, [r4:16]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vld1.32 {d0[1]}, [r4:32]! @ encoding: [0xa4,0xf9,0xbd,0x08]<br>
+@ CHECK-ERRORS: error: alignment must be 32 or omitted<br>
+@ CHECK-ERRORS: vld1.32 {d0[1]}, [r4:64]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 32 or omitted<br>
+@ CHECK-ERRORS: vld1.32 {d0[1]}, [r4:128]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 32 or omitted<br>
+@ CHECK-ERRORS: vld1.32 {d0[1]}, [r4:256]!<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vld1.32 {d0[1]}, [r4], r6<br>
+ vld1.32 {d0[1]}, [r4:16], r6<br>
+ vld1.32 {d0[1]}, [r4:32], r6<br>
+ vld1.32 {d0[1]}, [r4:64], r6<br>
+ vld1.32 {d0[1]}, [r4:128], r6<br>
+ vld1.32 {d0[1]}, [r4:256], r6<br>
+<br>
+@ CHECK: vld1.32 {d0[1]}, [r4], r6 @ encoding: [0xa4,0xf9,0x86,0x08]<br>
+@ CHECK-ERRORS: error: alignment must be 32 or omitted<br>
+@ CHECK-ERRORS: vld1.32 {d0[1]}, [r4:16], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vld1.32 {d0[1]}, [r4:32], r6 @ encoding: [0xa4,0xf9,0xb6,0x08]<br>
+@ CHECK-ERRORS: error: alignment must be 32 or omitted<br>
+@ CHECK-ERRORS: vld1.32 {d0[1]}, [r4:64], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 32 or omitted<br>
+@ CHECK-ERRORS: vld1.32 {d0[1]}, [r4:128], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 32 or omitted<br>
+@ CHECK-ERRORS: vld1.32 {d0[1]}, [r4:256], r6<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vld1.32 {d0[]}, [r4]<br>
+ vld1.32 {d0[]}, [r4:16]<br>
+ vld1.32 {d0[]}, [r4:32]<br>
+ vld1.32 {d0[]}, [r4:64]<br>
+ vld1.32 {d0[]}, [r4:128]<br>
+ vld1.32 {d0[]}, [r4:256]<br>
+<br>
+@ CHECK: vld1.32 {d0[]}, [r4] @ encoding: [0xa4,0xf9,0x8f,0x0c]<br>
+@ CHECK-ERRORS: error: alignment must be 32 or omitted<br>
+@ CHECK-ERRORS: vld1.32 {d0[]}, [r4:16]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vld1.32 {d0[]}, [r4:32] @ encoding: [0xa4,0xf9,0x9f,0x0c]<br>
+@ CHECK-ERRORS: error: alignment must be 32 or omitted<br>
+@ CHECK-ERRORS: vld1.32 {d0[]}, [r4:64]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 32 or omitted<br>
+@ CHECK-ERRORS: vld1.32 {d0[]}, [r4:128]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 32 or omitted<br>
+@ CHECK-ERRORS: vld1.32 {d0[]}, [r4:256]<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vld1.32 {d0[]}, [r4]!<br>
+ vld1.32 {d0[]}, [r4:16]!<br>
+ vld1.32 {d0[]}, [r4:32]!<br>
+ vld1.32 {d0[]}, [r4:64]!<br>
+ vld1.32 {d0[]}, [r4:128]!<br>
+ vld1.32 {d0[]}, [r4:256]!<br>
+<br>
+@ CHECK: vld1.32 {d0[]}, [r4]! @ encoding: [0xa4,0xf9,0x8d,0x0c]<br>
+@ CHECK-ERRORS: error: alignment must be 32 or omitted<br>
+@ CHECK-ERRORS: vld1.32 {d0[]}, [r4:16]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vld1.32 {d0[]}, [r4:32]! @ encoding: [0xa4,0xf9,0x9d,0x0c]<br>
+@ CHECK-ERRORS: error: alignment must be 32 or omitted<br>
+@ CHECK-ERRORS: vld1.32 {d0[]}, [r4:64]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 32 or omitted<br>
+@ CHECK-ERRORS: vld1.32 {d0[]}, [r4:128]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 32 or omitted<br>
+@ CHECK-ERRORS: vld1.32 {d0[]}, [r4:256]!<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vld1.32 {d0[]}, [r4], r6<br>
+ vld1.32 {d0[]}, [r4:16], r6<br>
+ vld1.32 {d0[]}, [r4:32], r6<br>
+ vld1.32 {d0[]}, [r4:64], r6<br>
+ vld1.32 {d0[]}, [r4:128], r6<br>
+ vld1.32 {d0[]}, [r4:256], r6<br>
+<br>
+@ CHECK: vld1.32 {d0[]}, [r4], r6 @ encoding: [0xa4,0xf9,0x86,0x0c]<br>
+@ CHECK-ERRORS: error: alignment must be 32 or omitted<br>
+@ CHECK-ERRORS: vld1.32 {d0[]}, [r4:16], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vld1.32 {d0[]}, [r4:32], r6 @ encoding: [0xa4,0xf9,0x96,0x0c]<br>
+@ CHECK-ERRORS: error: alignment must be 32 or omitted<br>
+@ CHECK-ERRORS: vld1.32 {d0[]}, [r4:64], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 32 or omitted<br>
+@ CHECK-ERRORS: vld1.32 {d0[]}, [r4:128], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 32 or omitted<br>
+@ CHECK-ERRORS: vld1.32 {d0[]}, [r4:256], r6<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vld1.32 {d0[], d1[]}, [r4]<br>
+ vld1.32 {d0[], d1[]}, [r4:16]<br>
+ vld1.32 {d0[], d1[]}, [r4:32]<br>
+ vld1.32 {d0[], d1[]}, [r4:64]<br>
+ vld1.32 {d0[], d1[]}, [r4:128]<br>
+ vld1.32 {d0[], d1[]}, [r4:256]<br>
+<br>
+@ CHECK: vld1.32 {d0[], d1[]}, [r4] @ encoding: [0xa4,0xf9,0xaf,0x0c]<br>
+@ CHECK-ERRORS: error: alignment must be 32 or omitted<br>
+@ CHECK-ERRORS: vld1.32 {d0[], d1[]}, [r4:16]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vld1.32 {d0[], d1[]}, [r4:32] @ encoding: [0xa4,0xf9,0xbf,0x0c]<br>
+@ CHECK-ERRORS: error: alignment must be 32 or omitted<br>
+@ CHECK-ERRORS: vld1.32 {d0[], d1[]}, [r4:64]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 32 or omitted<br>
+@ CHECK-ERRORS: vld1.32 {d0[], d1[]}, [r4:128]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 32 or omitted<br>
+@ CHECK-ERRORS: vld1.32 {d0[], d1[]}, [r4:256]<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vld1.32 {d0[], d1[]}, [r4]!<br>
+ vld1.32 {d0[], d1[]}, [r4:16]!<br>
+ vld1.32 {d0[], d1[]}, [r4:32]!<br>
+ vld1.32 {d0[], d1[]}, [r4:64]!<br>
+ vld1.32 {d0[], d1[]}, [r4:128]!<br>
+ vld1.32 {d0[], d1[]}, [r4:256]!<br>
+<br>
+@ CHECK: vld1.32 {d0[], d1[]}, [r4]! @ encoding: [0xa4,0xf9,0xad,0x0c]<br>
+@ CHECK-ERRORS: error: alignment must be 32 or omitted<br>
+@ CHECK-ERRORS: vld1.32 {d0[], d1[]}, [r4:16]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vld1.32 {d0[], d1[]}, [r4:32]! @ encoding: [0xa4,0xf9,0xbd,0x0c]<br>
+@ CHECK-ERRORS: error: alignment must be 32 or omitted<br>
+@ CHECK-ERRORS: vld1.32 {d0[], d1[]}, [r4:64]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 32 or omitted<br>
+@ CHECK-ERRORS: vld1.32 {d0[], d1[]}, [r4:128]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 32 or omitted<br>
+@ CHECK-ERRORS: vld1.32 {d0[], d1[]}, [r4:256]!<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vld1.32 {d0[], d1[]}, [r4], r6<br>
+ vld1.32 {d0[], d1[]}, [r4:16], r6<br>
+ vld1.32 {d0[], d1[]}, [r4:32], r6<br>
+ vld1.32 {d0[], d1[]}, [r4:64], r6<br>
+ vld1.32 {d0[], d1[]}, [r4:128], r6<br>
+ vld1.32 {d0[], d1[]}, [r4:256], r6<br>
+<br>
+@ CHECK: vld1.32 {d0[], d1[]}, [r4], r6 @ encoding: [0xa4,0xf9,0xa6,0x0c]<br>
+@ CHECK-ERRORS: error: alignment must be 32 or omitted<br>
+@ CHECK-ERRORS: vld1.32 {d0[], d1[]}, [r4:16], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vld1.32 {d0[], d1[]}, [r4:32], r6 @ encoding: [0xa4,0xf9,0xb6,0x0c]<br>
+@ CHECK-ERRORS: error: alignment must be 32 or omitted<br>
+@ CHECK-ERRORS: vld1.32 {d0[], d1[]}, [r4:64], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 32 or omitted<br>
+@ CHECK-ERRORS: vld1.32 {d0[], d1[]}, [r4:128], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 32 or omitted<br>
+@ CHECK-ERRORS: vld1.32 {d0[], d1[]}, [r4:256], r6<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vld1.32 {d0[1]}, [r4]<br>
+ vld1.32 {d0[1]}, [r4:16]<br>
+ vld1.32 {d0[1]}, [r4:32]<br>
+ vld1.32 {d0[1]}, [r4:64]<br>
+ vld1.32 {d0[1]}, [r4:128]<br>
+ vld1.32 {d0[1]}, [r4:256]<br>
+<br>
+@ CHECK: vld1.32 {d0[1]}, [r4] @ encoding: [0xa4,0xf9,0x8f,0x08]<br>
+@ CHECK-ERRORS: error: alignment must be 32 or omitted<br>
+@ CHECK-ERRORS: vld1.32 {d0[1]}, [r4:16]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vld1.32 {d0[1]}, [r4:32] @ encoding: [0xa4,0xf9,0xbf,0x08]<br>
+@ CHECK-ERRORS: error: alignment must be 32 or omitted<br>
+@ CHECK-ERRORS: vld1.32 {d0[1]}, [r4:64]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 32 or omitted<br>
+@ CHECK-ERRORS: vld1.32 {d0[1]}, [r4:128]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 32 or omitted<br>
+@ CHECK-ERRORS: vld1.32 {d0[1]}, [r4:256]<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vld1.32 {d0[1]}, [r4]!<br>
+ vld1.32 {d0[1]}, [r4:16]!<br>
+ vld1.32 {d0[1]}, [r4:32]!<br>
+ vld1.32 {d0[1]}, [r4:64]!<br>
+ vld1.32 {d0[1]}, [r4:128]!<br>
+ vld1.32 {d0[1]}, [r4:256]!<br>
+<br>
+@ CHECK: vld1.32 {d0[1]}, [r4]! @ encoding: [0xa4,0xf9,0x8d,0x08]<br>
+@ CHECK-ERRORS: error: alignment must be 32 or omitted<br>
+@ CHECK-ERRORS: vld1.32 {d0[1]}, [r4:16]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vld1.32 {d0[1]}, [r4:32]! @ encoding: [0xa4,0xf9,0xbd,0x08]<br>
+@ CHECK-ERRORS: error: alignment must be 32 or omitted<br>
+@ CHECK-ERRORS: vld1.32 {d0[1]}, [r4:64]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 32 or omitted<br>
+@ CHECK-ERRORS: vld1.32 {d0[1]}, [r4:128]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 32 or omitted<br>
+@ CHECK-ERRORS: vld1.32 {d0[1]}, [r4:256]!<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vld1.32 {d0[1]}, [r4], r6<br>
+ vld1.32 {d0[1]}, [r4:16], r6<br>
+ vld1.32 {d0[1]}, [r4:32], r6<br>
+ vld1.32 {d0[1]}, [r4:64], r6<br>
+ vld1.32 {d0[1]}, [r4:128], r6<br>
+ vld1.32 {d0[1]}, [r4:256], r6<br>
+<br>
+@ CHECK: vld1.32 {d0[1]}, [r4], r6 @ encoding: [0xa4,0xf9,0x86,0x08]<br>
+@ CHECK-ERRORS: error: alignment must be 32 or omitted<br>
+@ CHECK-ERRORS: vld1.32 {d0[1]}, [r4:16], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vld1.32 {d0[1]}, [r4:32], r6 @ encoding: [0xa4,0xf9,0xb6,0x08]<br>
+@ CHECK-ERRORS: error: alignment must be 32 or omitted<br>
+@ CHECK-ERRORS: vld1.32 {d0[1]}, [r4:64], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 32 or omitted<br>
+@ CHECK-ERRORS: vld1.32 {d0[1]}, [r4:128], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 32 or omitted<br>
+@ CHECK-ERRORS: vld1.32 {d0[1]}, [r4:256], r6<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vld1.64 {d0}, [r4]<br>
+ vld1.64 {d0}, [r4:16]<br>
+ vld1.64 {d0}, [r4:32]<br>
+ vld1.64 {d0}, [r4:64]<br>
+ vld1.64 {d0}, [r4:128]<br>
+ vld1.64 {d0}, [r4:256]<br>
+<br>
+@ CHECK: vld1.64 {d0}, [r4] @ encoding: [0x24,0xf9,0xcf,0x07]<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vld1.64 {d0}, [r4:16]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vld1.64 {d0}, [r4:32]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vld1.64 {d0}, [r4:64] @ encoding: [0x24,0xf9,0xdf,0x07]<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vld1.64 {d0}, [r4:128]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vld1.64 {d0}, [r4:256]<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vld1.64 {d0}, [r4]!<br>
+ vld1.64 {d0}, [r4:16]!<br>
+ vld1.64 {d0}, [r4:32]!<br>
+ vld1.64 {d0}, [r4:64]!<br>
+ vld1.64 {d0}, [r4:128]!<br>
+ vld1.64 {d0}, [r4:256]!<br>
+<br>
+@ CHECK: vld1.64 {d0}, [r4]! @ encoding: [0x24,0xf9,0xcd,0x07]<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vld1.64 {d0}, [r4:16]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vld1.64 {d0}, [r4:32]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vld1.64 {d0}, [r4:64]! @ encoding: [0x24,0xf9,0xdd,0x07]<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vld1.64 {d0}, [r4:128]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vld1.64 {d0}, [r4:256]!<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vld1.64 {d0}, [r4], r6<br>
+ vld1.64 {d0}, [r4:16], r6<br>
+ vld1.64 {d0}, [r4:32], r6<br>
+ vld1.64 {d0}, [r4:64], r6<br>
+ vld1.64 {d0}, [r4:128], r6<br>
+ vld1.64 {d0}, [r4:256], r6<br>
+<br>
+@ CHECK: vld1.64 {d0}, [r4], r6 @ encoding: [0x24,0xf9,0xc6,0x07]<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vld1.64 {d0}, [r4:16], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vld1.64 {d0}, [r4:32], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vld1.64 {d0}, [r4:64], r6 @ encoding: [0x24,0xf9,0xd6,0x07]<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vld1.64 {d0}, [r4:128], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vld1.64 {d0}, [r4:256], r6<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vld1.64 {d0, d1}, [r4]<br>
+ vld1.64 {d0, d1}, [r4:16]<br>
+ vld1.64 {d0, d1}, [r4:32]<br>
+ vld1.64 {d0, d1}, [r4:64]<br>
+ vld1.64 {d0, d1}, [r4:128]<br>
+ vld1.64 {d0, d1}, [r4:256]<br>
+<br>
+@ CHECK: vld1.64 {d0, d1}, [r4] @ encoding: [0x24,0xf9,0xcf,0x0a]<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted<br>
+@ CHECK-ERRORS: vld1.64 {d0, d1}, [r4:16]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted<br>
+@ CHECK-ERRORS: vld1.64 {d0, d1}, [r4:32]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vld1.64 {d0, d1}, [r4:64] @ encoding: [0x24,0xf9,0xdf,0x0a]<br>
+@ CHECK: vld1.64 {d0, d1}, [r4:128] @ encoding: [0x24,0xf9,0xef,0x0a]<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted<br>
+@ CHECK-ERRORS: vld1.64 {d0, d1}, [r4:256]<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vld1.64 {d0, d1}, [r4]!<br>
+ vld1.64 {d0, d1}, [r4:16]!<br>
+ vld1.64 {d0, d1}, [r4:32]!<br>
+ vld1.64 {d0, d1}, [r4:64]!<br>
+ vld1.64 {d0, d1}, [r4:128]!<br>
+ vld1.64 {d0, d1}, [r4:256]!<br>
+<br>
+@ CHECK: vld1.64 {d0, d1}, [r4]! @ encoding: [0x24,0xf9,0xcd,0x0a]<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted<br>
+@ CHECK-ERRORS: vld1.64 {d0, d1}, [r4:16]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted<br>
+@ CHECK-ERRORS: vld1.64 {d0, d1}, [r4:32]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vld1.64 {d0, d1}, [r4:64]! @ encoding: [0x24,0xf9,0xdd,0x0a]<br>
+@ CHECK: vld1.64 {d0, d1}, [r4:128]! @ encoding: [0x24,0xf9,0xed,0x0a]<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted<br>
+@ CHECK-ERRORS: vld1.64 {d0, d1}, [r4:256]!<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vld1.64 {d0, d1}, [r4], r6<br>
+ vld1.64 {d0, d1}, [r4:16], r6<br>
+ vld1.64 {d0, d1}, [r4:32], r6<br>
+ vld1.64 {d0, d1}, [r4:64], r6<br>
+ vld1.64 {d0, d1}, [r4:128], r6<br>
+ vld1.64 {d0, d1}, [r4:256], r6<br>
+<br>
+@ CHECK: vld1.64 {d0, d1}, [r4], r6 @ encoding: [0x24,0xf9,0xc6,0x0a]<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted<br>
+@ CHECK-ERRORS: vld1.64 {d0, d1}, [r4:16], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted<br>
+@ CHECK-ERRORS: vld1.64 {d0, d1}, [r4:32], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vld1.64 {d0, d1}, [r4:64], r6 @ encoding: [0x24,0xf9,0xd6,0x0a]<br>
+@ CHECK: vld1.64 {d0, d1}, [r4:128], r6 @ encoding: [0x24,0xf9,0xe6,0x0a]<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted<br>
+@ CHECK-ERRORS: vld1.64 {d0, d1}, [r4:256], r6<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vld1.64 {d0, d1, d2}, [r4]<br>
+ vld1.64 {d0, d1, d2}, [r4:16]<br>
+ vld1.64 {d0, d1, d2}, [r4:32]<br>
+ vld1.64 {d0, d1, d2}, [r4:64]<br>
+ vld1.64 {d0, d1, d2}, [r4:128]<br>
+ vld1.64 {d0, d1, d2}, [r4:256]<br>
+<br>
+@ CHECK: vld1.64 {d0, d1, d2}, [r4] @ encoding: [0x24,0xf9,0xcf,0x06]<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vld1.64 {d0, d1, d2}, [r4:16]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vld1.64 {d0, d1, d2}, [r4:32]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vld1.64 {d0, d1, d2}, [r4:64] @ encoding: [0x24,0xf9,0xdf,0x06]<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vld1.64 {d0, d1, d2}, [r4:128]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vld1.64 {d0, d1, d2}, [r4:256]<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vld1.64 {d0, d1, d2}, [r4]!<br>
+ vld1.64 {d0, d1, d2}, [r4:16]!<br>
+ vld1.64 {d0, d1, d2}, [r4:32]!<br>
+ vld1.64 {d0, d1, d2}, [r4:64]!<br>
+ vld1.64 {d0, d1, d2}, [r4:128]!<br>
+ vld1.64 {d0, d1, d2}, [r4:256]!<br>
+<br>
+@ CHECK: vld1.64 {d0, d1, d2}, [r4]! @ encoding: [0x24,0xf9,0xcd,0x06]<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vld1.64 {d0, d1, d2}, [r4:16]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vld1.64 {d0, d1, d2}, [r4:32]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vld1.64 {d0, d1, d2}, [r4:64]! @ encoding: [0x24,0xf9,0xdd,0x06]<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vld1.64 {d0, d1, d2}, [r4:128]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vld1.64 {d0, d1, d2}, [r4:256]!<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vld1.64 {d0, d1, d2}, [r4], r6<br>
+ vld1.64 {d0, d1, d2}, [r4:16], r6<br>
+ vld1.64 {d0, d1, d2}, [r4:32], r6<br>
+ vld1.64 {d0, d1, d2}, [r4:64], r6<br>
+ vld1.64 {d0, d1, d2}, [r4:128], r6<br>
+ vld1.64 {d0, d1, d2}, [r4:256], r6<br>
+<br>
+@ CHECK: vld1.64 {d0, d1, d2}, [r4], r6 @ encoding: [0x24,0xf9,0xc6,0x06]<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vld1.64 {d0, d1, d2}, [r4:16], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vld1.64 {d0, d1, d2}, [r4:32], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vld1.64 {d0, d1, d2}, [r4:64], r6 @ encoding: [0x24,0xf9,0xd6,0x06]<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vld1.64 {d0, d1, d2}, [r4:128], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vld1.64 {d0, d1, d2}, [r4:256], r6<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vld1.64 {d0, d1, d2, d3}, [r4]<br>
+ vld1.64 {d0, d1, d2, d3}, [r4:16]<br>
+ vld1.64 {d0, d1, d2, d3}, [r4:32]<br>
+ vld1.64 {d0, d1, d2, d3}, [r4:64]<br>
+ vld1.64 {d0, d1, d2, d3}, [r4:128]<br>
+ vld1.64 {d0, d1, d2, d3}, [r4:256]<br>
+<br>
+@ CHECK: vld1.64 {d0, d1, d2, d3}, [r4] @ encoding: [0x24,0xf9,0xcf,0x02]<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted<br>
+@ CHECK-ERRORS: vld1.64 {d0, d1, d2, d3}, [r4:16]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted<br>
+@ CHECK-ERRORS: vld1.64 {d0, d1, d2, d3}, [r4:32]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vld1.64 {d0, d1, d2, d3}, [r4:64] @ encoding: [0x24,0xf9,0xdf,0x02]<br>
+@ CHECK: vld1.64 {d0, d1, d2, d3}, [r4:128] @ encoding: [0x24,0xf9,0xef,0x02]<br>
+@ CHECK: vld1.64 {d0, d1, d2, d3}, [r4:256] @ encoding: [0x24,0xf9,0xff,0x02]<br>
+<br>
+ vld1.64 {d0, d1, d2, d3}, [r4]!<br>
+ vld1.64 {d0, d1, d2, d3}, [r4:16]!<br>
+ vld1.64 {d0, d1, d2, d3}, [r4:32]!<br>
+ vld1.64 {d0, d1, d2, d3}, [r4:64]!<br>
+ vld1.64 {d0, d1, d2, d3}, [r4:128]!<br>
+ vld1.64 {d0, d1, d2, d3}, [r4:256]!<br>
+<br>
+@ CHECK: vld1.64 {d0, d1, d2, d3}, [r4]! @ encoding: [0x24,0xf9,0xcd,0x02]<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted<br>
+@ CHECK-ERRORS: vld1.64 {d0, d1, d2, d3}, [r4:16]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted<br>
+@ CHECK-ERRORS: vld1.64 {d0, d1, d2, d3}, [r4:32]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vld1.64 {d0, d1, d2, d3}, [r4:64]! @ encoding: [0x24,0xf9,0xdd,0x02]<br>
+@ CHECK: vld1.64 {d0, d1, d2, d3}, [r4:128]! @ encoding: [0x24,0xf9,0xed,0x02]<br>
+@ CHECK: vld1.64 {d0, d1, d2, d3}, [r4:256]! @ encoding: [0x24,0xf9,0xfd,0x02]<br>
+<br>
+ vld1.64 {d0, d1, d2, d3}, [r4], r6<br>
+ vld1.64 {d0, d1, d2, d3}, [r4:16], r6<br>
+ vld1.64 {d0, d1, d2, d3}, [r4:32], r6<br>
+ vld1.64 {d0, d1, d2, d3}, [r4:64], r6<br>
+ vld1.64 {d0, d1, d2, d3}, [r4:128], r6<br>
+ vld1.64 {d0, d1, d2, d3}, [r4:256], r6<br>
+<br>
+@ CHECK: vld1.64 {d0, d1, d2, d3}, [r4], r6 @ encoding: [0x24,0xf9,0xc6,0x02]<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted<br>
+@ CHECK-ERRORS: vld1.64 {d0, d1, d2, d3}, [r4:16], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted<br>
+@ CHECK-ERRORS: vld1.64 {d0, d1, d2, d3}, [r4:32], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vld1.64 {d0, d1, d2, d3}, [r4:64], r6 @ encoding: [0x24,0xf9,0xd6,0x02]<br>
+@ CHECK: vld1.64 {d0, d1, d2, d3}, [r4:128], r6 @ encoding: [0x24,0xf9,0xe6,0x02]<br>
+@ CHECK: vld1.64 {d0, d1, d2, d3}, [r4:256], r6 @ encoding: [0x24,0xf9,0xf6,0x02]<br>
+<br>
+ vld2.8 {d0, d1}, [r4]<br>
+ vld2.8 {d0, d1}, [r4:16]<br>
+ vld2.8 {d0, d1}, [r4:32]<br>
+ vld2.8 {d0, d1}, [r4:64]<br>
+ vld2.8 {d0, d1}, [r4:128]<br>
+ vld2.8 {d0, d1}, [r4:256]<br>
+<br>
+@ CHECK: vld2.8 {d0, d1}, [r4] @ encoding: [0x24,0xf9,0x0f,0x08]<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted<br>
+@ CHECK-ERRORS: vld2.8 {d0, d1}, [r4:16]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted<br>
+@ CHECK-ERRORS: vld2.8 {d0, d1}, [r4:32]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vld2.8 {d0, d1}, [r4:64] @ encoding: [0x24,0xf9,0x1f,0x08]<br>
+@ CHECK: vld2.8 {d0, d1}, [r4:128] @ encoding: [0x24,0xf9,0x2f,0x08]<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted<br>
+@ CHECK-ERRORS: vld2.8 {d0, d1}, [r4:256]<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vld2.8 {d0, d1}, [r4]!<br>
+ vld2.8 {d0, d1}, [r4:16]!<br>
+ vld2.8 {d0, d1}, [r4:32]!<br>
+ vld2.8 {d0, d1}, [r4:64]!<br>
+ vld2.8 {d0, d1}, [r4:128]!<br>
+ vld2.8 {d0, d1}, [r4:256]!<br>
+<br>
+@ CHECK: vld2.8 {d0, d1}, [r4]! @ encoding: [0x24,0xf9,0x0d,0x08]<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted<br>
+@ CHECK-ERRORS: vld2.8 {d0, d1}, [r4:16]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted<br>
+@ CHECK-ERRORS: vld2.8 {d0, d1}, [r4:32]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vld2.8 {d0, d1}, [r4:64]! @ encoding: [0x24,0xf9,0x1d,0x08]<br>
+@ CHECK: vld2.8 {d0, d1}, [r4:128]! @ encoding: [0x24,0xf9,0x2d,0x08]<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted<br>
+@ CHECK-ERRORS: vld2.8 {d0, d1}, [r4:256]!<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vld2.8 {d0, d1}, [r4], r6<br>
+ vld2.8 {d0, d1}, [r4:16], r6<br>
+ vld2.8 {d0, d1}, [r4:32], r6<br>
+ vld2.8 {d0, d1}, [r4:64], r6<br>
+ vld2.8 {d0, d1}, [r4:128], r6<br>
+ vld2.8 {d0, d1}, [r4:256], r6<br>
+<br>
+@ CHECK: vld2.8 {d0, d1}, [r4], r6 @ encoding: [0x24,0xf9,0x06,0x08]<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted<br>
+@ CHECK-ERRORS: vld2.8 {d0, d1}, [r4:16], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted<br>
+@ CHECK-ERRORS: vld2.8 {d0, d1}, [r4:32], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vld2.8 {d0, d1}, [r4:64], r6 @ encoding: [0x24,0xf9,0x16,0x08]<br>
+@ CHECK: vld2.8 {d0, d1}, [r4:128], r6 @ encoding: [0x24,0xf9,0x26,0x08]<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted<br>
+@ CHECK-ERRORS: vld2.8 {d0, d1}, [r4:256], r6<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vld2.8 {d0, d2}, [r4]<br>
+ vld2.8 {d0, d2}, [r4:16]<br>
+ vld2.8 {d0, d2}, [r4:32]<br>
+ vld2.8 {d0, d2}, [r4:64]<br>
+ vld2.8 {d0, d2}, [r4:128]<br>
+ vld2.8 {d0, d2}, [r4:256]<br>
+<br>
+@ CHECK: vld2.8 {d0, d2}, [r4] @ encoding: [0x24,0xf9,0x0f,0x09]<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted<br>
+@ CHECK-ERRORS: vld2.8 {d0, d2}, [r4:16]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted<br>
+@ CHECK-ERRORS: vld2.8 {d0, d2}, [r4:32]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vld2.8 {d0, d2}, [r4:64] @ encoding: [0x24,0xf9,0x1f,0x09]<br>
+@ CHECK: vld2.8 {d0, d2}, [r4:128] @ encoding: [0x24,0xf9,0x2f,0x09]<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted<br>
+@ CHECK-ERRORS: vld2.8 {d0, d2}, [r4:256]<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vld2.8 {d0, d2}, [r4]!<br>
+ vld2.8 {d0, d2}, [r4:16]!<br>
+ vld2.8 {d0, d2}, [r4:32]!<br>
+ vld2.8 {d0, d2}, [r4:64]!<br>
+ vld2.8 {d0, d2}, [r4:128]!<br>
+ vld2.8 {d0, d2}, [r4:256]!<br>
+<br>
+@ CHECK: vld2.8 {d0, d2}, [r4]! @ encoding: [0x24,0xf9,0x0d,0x09]<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted<br>
+@ CHECK-ERRORS: vld2.8 {d0, d2}, [r4:16]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted<br>
+@ CHECK-ERRORS: vld2.8 {d0, d2}, [r4:32]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vld2.8 {d0, d2}, [r4:64]! @ encoding: [0x24,0xf9,0x1d,0x09]<br>
+@ CHECK: vld2.8 {d0, d2}, [r4:128]! @ encoding: [0x24,0xf9,0x2d,0x09]<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted<br>
+@ CHECK-ERRORS: vld2.8 {d0, d2}, [r4:256]!<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vld2.8 {d0, d2}, [r4], r6<br>
+ vld2.8 {d0, d2}, [r4:16], r6<br>
+ vld2.8 {d0, d2}, [r4:32], r6<br>
+ vld2.8 {d0, d2}, [r4:64], r6<br>
+ vld2.8 {d0, d2}, [r4:128], r6<br>
+ vld2.8 {d0, d2}, [r4:256], r6<br>
+<br>
+@ CHECK: vld2.8 {d0, d2}, [r4], r6 @ encoding: [0x24,0xf9,0x06,0x09]<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted<br>
+@ CHECK-ERRORS: vld2.8 {d0, d2}, [r4:16], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted<br>
+@ CHECK-ERRORS: vld2.8 {d0, d2}, [r4:32], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vld2.8 {d0, d2}, [r4:64], r6 @ encoding: [0x24,0xf9,0x16,0x09]<br>
+@ CHECK: vld2.8 {d0, d2}, [r4:128], r6 @ encoding: [0x24,0xf9,0x26,0x09]<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted<br>
+@ CHECK-ERRORS: vld2.8 {d0, d2}, [r4:256], r6<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vld2.8 {d0, d1, d2, d3}, [r4]<br>
+ vld2.8 {d0, d1, d2, d3}, [r4:16]<br>
+ vld2.8 {d0, d1, d2, d3}, [r4:32]<br>
+ vld2.8 {d0, d1, d2, d3}, [r4:64]<br>
+ vld2.8 {d0, d1, d2, d3}, [r4:128]<br>
+ vld2.8 {d0, d1, d2, d3}, [r4:256]<br>
+<br>
+@ CHECK: vld2.8 {d0, d1, d2, d3}, [r4] @ encoding: [0x24,0xf9,0x0f,0x03]<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted<br>
+@ CHECK-ERRORS: vld2.8 {d0, d1, d2, d3}, [r4:16]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted<br>
+@ CHECK-ERRORS: vld2.8 {d0, d1, d2, d3}, [r4:32]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vld2.8 {d0, d1, d2, d3}, [r4:64] @ encoding: [0x24,0xf9,0x1f,0x03]<br>
+@ CHECK: vld2.8 {d0, d1, d2, d3}, [r4:128] @ encoding: [0x24,0xf9,0x2f,0x03]<br>
+@ CHECK: vld2.8 {d0, d1, d2, d3}, [r4:256] @ encoding: [0x24,0xf9,0x3f,0x03]<br>
+<br>
+ vld2.8 {d0, d1, d2, d3}, [r4]!<br>
+ vld2.8 {d0, d1, d2, d3}, [r4:16]!<br>
+ vld2.8 {d0, d1, d2, d3}, [r4:32]!<br>
+ vld2.8 {d0, d1, d2, d3}, [r4:64]!<br>
+ vld2.8 {d0, d1, d2, d3}, [r4:128]!<br>
+ vld2.8 {d0, d1, d2, d3}, [r4:256]!<br>
+<br>
+@ CHECK: vld2.8 {d0, d1, d2, d3}, [r4]! @ encoding: [0x24,0xf9,0x0d,0x03]<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted<br>
+@ CHECK-ERRORS: vld2.8 {d0, d1, d2, d3}, [r4:16]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted<br>
+@ CHECK-ERRORS: vld2.8 {d0, d1, d2, d3}, [r4:32]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vld2.8 {d0, d1, d2, d3}, [r4:64]! @ encoding: [0x24,0xf9,0x1d,0x03]<br>
+@ CHECK: vld2.8 {d0, d1, d2, d3}, [r4:128]! @ encoding: [0x24,0xf9,0x2d,0x03]<br>
+@ CHECK: vld2.8 {d0, d1, d2, d3}, [r4:256]! @ encoding: [0x24,0xf9,0x3d,0x03]<br>
+<br>
+ vld2.8 {d0, d1, d2, d3}, [r4], r6<br>
+ vld2.8 {d0, d1, d2, d3}, [r4:16], r6<br>
+ vld2.8 {d0, d1, d2, d3}, [r4:32], r6<br>
+ vld2.8 {d0, d1, d2, d3}, [r4:64], r6<br>
+ vld2.8 {d0, d1, d2, d3}, [r4:128], r6<br>
+ vld2.8 {d0, d1, d2, d3}, [r4:256], r6<br>
+<br>
+@ CHECK: vld2.8 {d0, d1, d2, d3}, [r4], r6 @ encoding: [0x24,0xf9,0x06,0x03]<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted<br>
+@ CHECK-ERRORS: vld2.8 {d0, d1, d2, d3}, [r4:16], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted<br>
+@ CHECK-ERRORS: vld2.8 {d0, d1, d2, d3}, [r4:32], r6<br>
+@ CHECK: vld2.8 {d0, d1, d2, d3}, [r4:64], r6 @ encoding: [0x24,0xf9,0x16,0x03]<br>
+@ CHECK: vld2.8 {d0, d1, d2, d3}, [r4:128], r6 @ encoding: [0x24,0xf9,0x26,0x03]<br>
+@ CHECK: vld2.8 {d0, d1, d2, d3}, [r4:256], r6 @ encoding: [0x24,0xf9,0x36,0x03]<br>
+<br>
+ vld2.8 {d0[2], d1[2]}, [r4]<br>
+ vld2.8 {d0[2], d1[2]}, [r4:16]<br>
+ vld2.8 {d0[2], d1[2]}, [r4:32]<br>
+ vld2.8 {d0[2], d1[2]}, [r4:64]<br>
+ vld2.8 {d0[2], d1[2]}, [r4:128]<br>
+ vld2.8 {d0[2], d1[2]}, [r4:256]<br>
+<br>
+@ CHECK: vld2.8 {d0[2], d1[2]}, [r4] @ encoding: [0xa4,0xf9,0x4f,0x01]<br>
+@ CHECK: vld2.8 {d0[2], d1[2]}, [r4:16] @ encoding: [0xa4,0xf9,0x5f,0x01]<br>
+@ CHECK-ERRORS: error: alignment must be 16 or omitted<br>
+@ CHECK-ERRORS: vld2.8 {d0[2], d1[2]}, [r4:32]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 16 or omitted<br>
+@ CHECK-ERRORS: vld2.8 {d0[2], d1[2]}, [r4:64]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 16 or omitted<br>
+@ CHECK-ERRORS: vld2.8 {d0[2], d1[2]}, [r4:128]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 16 or omitted<br>
+@ CHECK-ERRORS: vld2.8 {d0[2], d1[2]}, [r4:256]<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vld2.8 {d0[2], d1[2]}, [r4]!<br>
+ vld2.8 {d0[2], d1[2]}, [r4:16]!<br>
+ vld2.8 {d0[2], d1[2]}, [r4:32]!<br>
+ vld2.8 {d0[2], d1[2]}, [r4:64]!<br>
+ vld2.8 {d0[2], d1[2]}, [r4:128]!<br>
+ vld2.8 {d0[2], d1[2]}, [r4:256]!<br>
+<br>
+@ CHECK: vld2.8 {d0[2], d1[2]}, [r4]! @ encoding: [0xa4,0xf9,0x4d,0x01]<br>
+@ CHECK: vld2.8 {d0[2], d1[2]}, [r4:16]! @ encoding: [0xa4,0xf9,0x5d,0x01]<br>
+@ CHECK-ERRORS: error: alignment must be 16 or omitted<br>
+@ CHECK-ERRORS: vld2.8 {d0[2], d1[2]}, [r4:32]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 16 or omitted<br>
+@ CHECK-ERRORS: vld2.8 {d0[2], d1[2]}, [r4:64]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 16 or omitted<br>
+@ CHECK-ERRORS: vld2.8 {d0[2], d1[2]}, [r4:128]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 16 or omitted<br>
+@ CHECK-ERRORS: vld2.8 {d0[2], d1[2]}, [r4:256]!<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vld2.8 {d0[2], d1[2]}, [r4], r6<br>
+ vld2.8 {d0[2], d1[2]}, [r4:16], r6<br>
+ vld2.8 {d0[2], d1[2]}, [r4:32], r6<br>
+ vld2.8 {d0[2], d1[2]}, [r4:64], r6<br>
+ vld2.8 {d0[2], d1[2]}, [r4:128], r6<br>
+ vld2.8 {d0[2], d1[2]}, [r4:256], r6<br>
+<br>
+@ CHECK: vld2.8 {d0[2], d1[2]}, [r4], r6 @ encoding: [0xa4,0xf9,0x46,0x01]<br>
+@ CHECK: vld2.8 {d0[2], d1[2]}, [r4:16], r6 @ encoding: [0xa4,0xf9,0x56,0x01]<br>
+@ CHECK-ERRORS: error: alignment must be 16 or omitted<br>
+@ CHECK-ERRORS: vld2.8 {d0[2], d1[2]}, [r4:32], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 16 or omitted<br>
+@ CHECK-ERRORS: vld2.8 {d0[2], d1[2]}, [r4:64], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 16 or omitted<br>
+@ CHECK-ERRORS: vld2.8 {d0[2], d1[2]}, [r4:128], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 16 or omitted<br>
+@ CHECK-ERRORS: vld2.8 {d0[2], d1[2]}, [r4:256], r6<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vld2.8 {d0[], d1[]}, [r4]<br>
+ vld2.8 {d0[], d1[]}, [r4:16]<br>
+ vld2.8 {d0[], d1[]}, [r4:32]<br>
+ vld2.8 {d0[], d1[]}, [r4:64]<br>
+ vld2.8 {d0[], d1[]}, [r4:128]<br>
+ vld2.8 {d0[], d1[]}, [r4:256]<br>
+<br>
+@ CHECK: vld2.8 {d0[], d1[]}, [r4] @ encoding: [0xa4,0xf9,0x0f,0x0d]<br>
+@ CHECK: vld2.8 {d0[], d1[]}, [r4:16] @ encoding: [0xa4,0xf9,0x1f,0x0d]<br>
+@ CHECK-ERRORS: error: alignment must be 16 or omitted<br>
+@ CHECK-ERRORS: vld2.8 {d0[], d1[]}, [r4:32]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 16 or omitted<br>
+@ CHECK-ERRORS: vld2.8 {d0[], d1[]}, [r4:64]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 16 or omitted<br>
+@ CHECK-ERRORS: vld2.8 {d0[], d1[]}, [r4:128]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 16 or omitted<br>
+@ CHECK-ERRORS: vld2.8 {d0[], d1[]}, [r4:256]<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vld2.8 {d0[], d1[]}, [r4]!<br>
+ vld2.8 {d0[], d1[]}, [r4:16]!<br>
+ vld2.8 {d0[], d1[]}, [r4:32]!<br>
+ vld2.8 {d0[], d1[]}, [r4:64]!<br>
+ vld2.8 {d0[], d1[]}, [r4:128]!<br>
+ vld2.8 {d0[], d1[]}, [r4:256]!<br>
+<br>
+@ CHECK: vld2.8 {d0[], d1[]}, [r4]! @ encoding: [0xa4,0xf9,0x0d,0x0d]<br>
+@ CHECK: vld2.8 {d0[], d1[]}, [r4:16]! @ encoding: [0xa4,0xf9,0x1d,0x0d]<br>
+@ CHECK-ERRORS: error: alignment must be 16 or omitted<br>
+@ CHECK-ERRORS: vld2.8 {d0[], d1[]}, [r4:32]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 16 or omitted<br>
+@ CHECK-ERRORS: vld2.8 {d0[], d1[]}, [r4:64]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 16 or omitted<br>
+@ CHECK-ERRORS: vld2.8 {d0[], d1[]}, [r4:128]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 16 or omitted<br>
+@ CHECK-ERRORS: vld2.8 {d0[], d1[]}, [r4:256]!<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vld2.8 {d0[], d1[]}, [r4], r6<br>
+ vld2.8 {d0[], d1[]}, [r4:16], r6<br>
+ vld2.8 {d0[], d1[]}, [r4:32], r6<br>
+ vld2.8 {d0[], d1[]}, [r4:64], r6<br>
+ vld2.8 {d0[], d1[]}, [r4:128], r6<br>
+ vld2.8 {d0[], d1[]}, [r4:256], r6<br>
+<br>
+@ CHECK: vld2.8 {d0[], d1[]}, [r4], r6 @ encoding: [0xa4,0xf9,0x06,0x0d]<br>
+@ CHECK: vld2.8 {d0[], d1[]}, [r4:16], r6 @ encoding: [0xa4,0xf9,0x16,0x0d]<br>
+@ CHECK-ERRORS: error: alignment must be 16 or omitted<br>
+@ CHECK-ERRORS: vld2.8 {d0[], d1[]}, [r4:32], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 16 or omitted<br>
+@ CHECK-ERRORS: vld2.8 {d0[], d1[]}, [r4:64], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 16 or omitted<br>
+@ CHECK-ERRORS: vld2.8 {d0[], d1[]}, [r4:128], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 16 or omitted<br>
+@ CHECK-ERRORS: vld2.8 {d0[], d1[]}, [r4:256], r6<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vld2.8 {d0[], d2[]}, [r4]<br>
+ vld2.8 {d0[], d2[]}, [r4:16]<br>
+ vld2.8 {d0[], d2[]}, [r4:32]<br>
+ vld2.8 {d0[], d2[]}, [r4:64]<br>
+ vld2.8 {d0[], d2[]}, [r4:128]<br>
+ vld2.8 {d0[], d2[]}, [r4:256]<br>
+<br>
+@ CHECK: vld2.8 {d0[], d2[]}, [r4] @ encoding: [0xa4,0xf9,0x2f,0x0d]<br>
+@ CHECK: vld2.8 {d0[], d2[]}, [r4:16] @ encoding: [0xa4,0xf9,0x3f,0x0d]<br>
+@ CHECK-ERRORS: error: alignment must be 16 or omitted<br>
+@ CHECK-ERRORS: vld2.8 {d0[], d2[]}, [r4:32]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 16 or omitted<br>
+@ CHECK-ERRORS: vld2.8 {d0[], d2[]}, [r4:64]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 16 or omitted<br>
+@ CHECK-ERRORS: vld2.8 {d0[], d2[]}, [r4:128]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 16 or omitted<br>
+@ CHECK-ERRORS: vld2.8 {d0[], d2[]}, [r4:256]<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vld2.8 {d0[], d2[]}, [r4]!<br>
+ vld2.8 {d0[], d2[]}, [r4:16]!<br>
+ vld2.8 {d0[], d2[]}, [r4:32]!<br>
+ vld2.8 {d0[], d2[]}, [r4:64]!<br>
+ vld2.8 {d0[], d2[]}, [r4:128]!<br>
+ vld2.8 {d0[], d2[]}, [r4:256]!<br>
+<br>
+@ CHECK: vld2.8 {d0[], d2[]}, [r4]! @ encoding: [0xa4,0xf9,0x2d,0x0d]<br>
+@ CHECK: vld2.8 {d0[], d2[]}, [r4:16]! @ encoding: [0xa4,0xf9,0x3d,0x0d]<br>
+@ CHECK-ERRORS: error: alignment must be 16 or omitted<br>
+@ CHECK-ERRORS: vld2.8 {d0[], d2[]}, [r4:32]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 16 or omitted<br>
+@ CHECK-ERRORS: vld2.8 {d0[], d2[]}, [r4:64]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 16 or omitted<br>
+@ CHECK-ERRORS: vld2.8 {d0[], d2[]}, [r4:128]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 16 or omitted<br>
+@ CHECK-ERRORS: vld2.8 {d0[], d2[]}, [r4:256]!<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vld2.8 {d0[], d2[]}, [r4], r6<br>
+ vld2.8 {d0[], d2[]}, [r4:16], r6<br>
+ vld2.8 {d0[], d2[]}, [r4:32], r6<br>
+ vld2.8 {d0[], d2[]}, [r4:64], r6<br>
+ vld2.8 {d0[], d2[]}, [r4:128], r6<br>
+ vld2.8 {d0[], d2[]}, [r4:256], r6<br>
+<br>
+@ CHECK: vld2.8 {d0[], d2[]}, [r4], r6 @ encoding: [0xa4,0xf9,0x26,0x0d]<br>
+@ CHECK: vld2.8 {d0[], d2[]}, [r4:16], r6 @ encoding: [0xa4,0xf9,0x36,0x0d]<br>
+@ CHECK-ERRORS: error: alignment must be 16 or omitted<br>
+@ CHECK-ERRORS: vld2.8 {d0[], d2[]}, [r4:32], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 16 or omitted<br>
+@ CHECK-ERRORS: vld2.8 {d0[], d2[]}, [r4:64], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 16 or omitted<br>
+@ CHECK-ERRORS: vld2.8 {d0[], d2[]}, [r4:128], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 16 or omitted<br>
+@ CHECK-ERRORS: vld2.8 {d0[], d2[]}, [r4:256], r6<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vld2.16 {d0, d1}, [r4]<br>
+ vld2.16 {d0, d1}, [r4:16]<br>
+ vld2.16 {d0, d1}, [r4:32]<br>
+ vld2.16 {d0, d1}, [r4:64]<br>
+ vld2.16 {d0, d1}, [r4:128]<br>
+ vld2.16 {d0, d1}, [r4:256]<br>
+<br>
+@ CHECK: vld2.16 {d0, d1}, [r4] @ encoding: [0x24,0xf9,0x4f,0x08]<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted<br>
+@ CHECK-ERRORS: vld2.16 {d0, d1}, [r4:16]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted<br>
+@ CHECK-ERRORS: vld2.16 {d0, d1}, [r4:32]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vld2.16 {d0, d1}, [r4:64] @ encoding: [0x24,0xf9,0x5f,0x08]<br>
+@ CHECK: vld2.16 {d0, d1}, [r4:128] @ encoding: [0x24,0xf9,0x6f,0x08]<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted<br>
+@ CHECK-ERRORS: vld2.16 {d0, d1}, [r4:256]<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vld2.16 {d0, d1}, [r4]!<br>
+ vld2.16 {d0, d1}, [r4:16]!<br>
+ vld2.16 {d0, d1}, [r4:32]!<br>
+ vld2.16 {d0, d1}, [r4:64]!<br>
+ vld2.16 {d0, d1}, [r4:128]!<br>
+ vld2.16 {d0, d1}, [r4:256]!<br>
+<br>
+@ CHECK: vld2.16 {d0, d1}, [r4]! @ encoding: [0x24,0xf9,0x4d,0x08]<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted<br>
+@ CHECK-ERRORS: vld2.16 {d0, d1}, [r4:16]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted<br>
+@ CHECK-ERRORS: vld2.16 {d0, d1}, [r4:32]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vld2.16 {d0, d1}, [r4:64]! @ encoding: [0x24,0xf9,0x5d,0x08]<br>
+@ CHECK: vld2.16 {d0, d1}, [r4:128]! @ encoding: [0x24,0xf9,0x6d,0x08]<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted<br>
+@ CHECK-ERRORS: vld2.16 {d0, d1}, [r4:256]!<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vld2.16 {d0, d1}, [r4], r6<br>
+ vld2.16 {d0, d1}, [r4:16], r6<br>
+ vld2.16 {d0, d1}, [r4:32], r6<br>
+ vld2.16 {d0, d1}, [r4:64], r6<br>
+ vld2.16 {d0, d1}, [r4:128], r6<br>
+ vld2.16 {d0, d1}, [r4:256], r6<br>
+<br>
+@ CHECK: vld2.16 {d0, d1}, [r4], r6 @ encoding: [0x24,0xf9,0x46,0x08]<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted<br>
+@ CHECK-ERRORS: vld2.16 {d0, d1}, [r4:16], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted<br>
+@ CHECK-ERRORS: vld2.16 {d0, d1}, [r4:32], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vld2.16 {d0, d1}, [r4:64], r6 @ encoding: [0x24,0xf9,0x56,0x08]<br>
+@ CHECK: vld2.16 {d0, d1}, [r4:128], r6 @ encoding: [0x24,0xf9,0x66,0x08]<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted<br>
+@ CHECK-ERRORS: vld2.16 {d0, d1}, [r4:256], r6<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vld2.16 {d0, d2}, [r4]<br>
+ vld2.16 {d0, d2}, [r4:16]<br>
+ vld2.16 {d0, d2}, [r4:32]<br>
+ vld2.16 {d0, d2}, [r4:64]<br>
+ vld2.16 {d0, d2}, [r4:128]<br>
+ vld2.16 {d0, d2}, [r4:256]<br>
+<br>
+@ CHECK: vld2.16 {d0, d2}, [r4] @ encoding: [0x24,0xf9,0x4f,0x09]<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted<br>
+@ CHECK-ERRORS: vld2.16 {d0, d2}, [r4:16]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted<br>
+@ CHECK-ERRORS: vld2.16 {d0, d2}, [r4:32]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vld2.16 {d0, d2}, [r4:64] @ encoding: [0x24,0xf9,0x5f,0x09]<br>
+@ CHECK: vld2.16 {d0, d2}, [r4:128] @ encoding: [0x24,0xf9,0x6f,0x09]<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted<br>
+@ CHECK-ERRORS: vld2.16 {d0, d2}, [r4:256]<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vld2.16 {d0, d2}, [r4]!<br>
+ vld2.16 {d0, d2}, [r4:16]!<br>
+ vld2.16 {d0, d2}, [r4:32]!<br>
+ vld2.16 {d0, d2}, [r4:64]!<br>
+ vld2.16 {d0, d2}, [r4:128]!<br>
+ vld2.16 {d0, d2}, [r4:256]!<br>
+<br>
+@ CHECK: vld2.16 {d0, d2}, [r4]! @ encoding: [0x24,0xf9,0x4d,0x09]<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted<br>
+@ CHECK-ERRORS: vld2.16 {d0, d2}, [r4:16]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted<br>
+@ CHECK-ERRORS: vld2.16 {d0, d2}, [r4:32]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vld2.16 {d0, d2}, [r4:64]! @ encoding: [0x24,0xf9,0x5d,0x09]<br>
+@ CHECK: vld2.16 {d0, d2}, [r4:128]! @ encoding: [0x24,0xf9,0x6d,0x09]<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted<br>
+@ CHECK-ERRORS: vld2.16 {d0, d2}, [r4:256]!<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vld2.16 {d0, d2}, [r4], r6<br>
+ vld2.16 {d0, d2}, [r4:16], r6<br>
+ vld2.16 {d0, d2}, [r4:32], r6<br>
+ vld2.16 {d0, d2}, [r4:64], r6<br>
+ vld2.16 {d0, d2}, [r4:128], r6<br>
+ vld2.16 {d0, d2}, [r4:256], r6<br>
+<br>
+@ CHECK: vld2.16 {d0, d2}, [r4], r6 @ encoding: [0x24,0xf9,0x46,0x09]<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted<br>
+@ CHECK-ERRORS: vld2.16 {d0, d2}, [r4:16], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted<br>
+@ CHECK-ERRORS: vld2.16 {d0, d2}, [r4:32], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vld2.16 {d0, d2}, [r4:64], r6 @ encoding: [0x24,0xf9,0x56,0x09]<br>
+@ CHECK: vld2.16 {d0, d2}, [r4:128], r6 @ encoding: [0x24,0xf9,0x66,0x09]<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted<br>
+@ CHECK-ERRORS: vld2.16 {d0, d2}, [r4:256], r6<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vld2.16 {d0, d1, d2, d3}, [r4]<br>
+ vld2.16 {d0, d1, d2, d3}, [r4:16]<br>
+ vld2.16 {d0, d1, d2, d3}, [r4:32]<br>
+ vld2.16 {d0, d1, d2, d3}, [r4:64]<br>
+ vld2.16 {d0, d1, d2, d3}, [r4:128]<br>
+ vld2.16 {d0, d1, d2, d3}, [r4:256]<br>
+<br>
+@ CHECK: vld2.16 {d0, d1, d2, d3}, [r4] @ encoding: [0x24,0xf9,0x4f,0x03]<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted<br>
+@ CHECK-ERRORS: vld2.16 {d0, d1, d2, d3}, [r4:16]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted<br>
+@ CHECK-ERRORS: vld2.16 {d0, d1, d2, d3}, [r4:32]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vld2.16 {d0, d1, d2, d3}, [r4:64] @ encoding: [0x24,0xf9,0x5f,0x03]<br>
+@ CHECK: vld2.16 {d0, d1, d2, d3}, [r4:128] @ encoding: [0x24,0xf9,0x6f,0x03]<br>
+@ CHECK: vld2.16 {d0, d1, d2, d3}, [r4:256] @ encoding: [0x24,0xf9,0x7f,0x03]<br>
+<br>
+ vld2.16 {d0, d1, d2, d3}, [r4]!<br>
+ vld2.16 {d0, d1, d2, d3}, [r4:16]!<br>
+ vld2.16 {d0, d1, d2, d3}, [r4:32]!<br>
+ vld2.16 {d0, d1, d2, d3}, [r4:64]!<br>
+ vld2.16 {d0, d1, d2, d3}, [r4:128]!<br>
+ vld2.16 {d0, d1, d2, d3}, [r4:256]!<br>
+<br>
+@ CHECK: vld2.16 {d0, d1, d2, d3}, [r4]! @ encoding: [0x24,0xf9,0x4d,0x03]<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted<br>
+@ CHECK-ERRORS: vld2.16 {d0, d1, d2, d3}, [r4:16]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted<br>
+@ CHECK-ERRORS: vld2.16 {d0, d1, d2, d3}, [r4:32]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vld2.16 {d0, d1, d2, d3}, [r4:64]! @ encoding: [0x24,0xf9,0x5d,0x03]<br>
+@ CHECK: vld2.16 {d0, d1, d2, d3}, [r4:128]! @ encoding: [0x24,0xf9,0x6d,0x03]<br>
+@ CHECK: vld2.16 {d0, d1, d2, d3}, [r4:256]! @ encoding: [0x24,0xf9,0x7d,0x03]<br>
+<br>
+ vld2.16 {d0, d1, d2, d3}, [r4], r6<br>
+ vld2.16 {d0, d1, d2, d3}, [r4:16], r6<br>
+ vld2.16 {d0, d1, d2, d3}, [r4:32], r6<br>
+ vld2.16 {d0, d1, d2, d3}, [r4:64], r6<br>
+ vld2.16 {d0, d1, d2, d3}, [r4:128], r6<br>
+ vld2.16 {d0, d1, d2, d3}, [r4:256], r6<br>
+<br>
+@ CHECK: vld2.16 {d0, d1, d2, d3}, [r4], r6 @ encoding: [0x24,0xf9,0x46,0x03]<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted<br>
+@ CHECK-ERRORS: vld2.16 {d0, d1, d2, d3}, [r4:16], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted<br>
+@ CHECK-ERRORS: vld2.16 {d0, d1, d2, d3}, [r4:32], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vld2.16 {d0, d1, d2, d3}, [r4:64], r6 @ encoding: [0x24,0xf9,0x56,0x03]<br>
+@ CHECK: vld2.16 {d0, d1, d2, d3}, [r4:128], r6 @ encoding: [0x24,0xf9,0x66,0x03]<br>
+@ CHECK: vld2.16 {d0, d1, d2, d3}, [r4:256], r6 @ encoding: [0x24,0xf9,0x76,0x03]<br>
+<br>
+ vld2.16 {d0[2], d1[2]}, [r4]<br>
+ vld2.16 {d0[2], d1[2]}, [r4:16]<br>
+ vld2.16 {d0[2], d1[2]}, [r4:32]<br>
+ vld2.16 {d0[2], d1[2]}, [r4:64]<br>
+ vld2.16 {d0[2], d1[2]}, [r4:128]<br>
+ vld2.16 {d0[2], d1[2]}, [r4:256]<br>
+<br>
+@ CHECK: vld2.16 {d0[2], d1[2]}, [r4] @ encoding: [0xa4,0xf9,0x8f,0x05]<br>
+@ CHECK-ERRORS: error: alignment must be 32 or omitted<br>
+@ CHECK-ERRORS: vld2.16 {d0[2], d1[2]}, [r4:16]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vld2.16 {d0[2], d1[2]}, [r4:32] @ encoding: [0xa4,0xf9,0x9f,0x05]<br>
+@ CHECK-ERRORS: error: alignment must be 32 or omitted<br>
+@ CHECK-ERRORS: vld2.16 {d0[2], d1[2]}, [r4:64]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 32 or omitted<br>
+@ CHECK-ERRORS: vld2.16 {d0[2], d1[2]}, [r4:128]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 32 or omitted<br>
+@ CHECK-ERRORS: vld2.16 {d0[2], d1[2]}, [r4:256]<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vld2.16 {d0[2], d1[2]}, [r4]!<br>
+ vld2.16 {d0[2], d1[2]}, [r4:16]!<br>
+ vld2.16 {d0[2], d1[2]}, [r4:32]!<br>
+ vld2.16 {d0[2], d1[2]}, [r4:64]!<br>
+ vld2.16 {d0[2], d1[2]}, [r4:128]!<br>
+ vld2.16 {d0[2], d1[2]}, [r4:256]!<br>
+<br>
+@ CHECK: vld2.16 {d0[2], d1[2]}, [r4]! @ encoding: [0xa4,0xf9,0x8d,0x05]<br>
+@ CHECK-ERRORS: error: alignment must be 32 or omitted<br>
+@ CHECK-ERRORS: vld2.16 {d0[2], d1[2]}, [r4:16]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vld2.16 {d0[2], d1[2]}, [r4:32]! @ encoding: [0xa4,0xf9,0x9d,0x05]<br>
+@ CHECK-ERRORS: error: alignment must be 32 or omitted<br>
+@ CHECK-ERRORS: vld2.16 {d0[2], d1[2]}, [r4:64]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 32 or omitted<br>
+@ CHECK-ERRORS: vld2.16 {d0[2], d1[2]}, [r4:128]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 32 or omitted<br>
+@ CHECK-ERRORS: vld2.16 {d0[2], d1[2]}, [r4:256]!<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vld2.16 {d0[2], d1[2]}, [r4], r6<br>
+ vld2.16 {d0[2], d1[2]}, [r4:16], r6<br>
+ vld2.16 {d0[2], d1[2]}, [r4:32], r6<br>
+ vld2.16 {d0[2], d1[2]}, [r4:64], r6<br>
+ vld2.16 {d0[2], d1[2]}, [r4:128], r6<br>
+ vld2.16 {d0[2], d1[2]}, [r4:256], r6<br>
+<br>
+@ CHECK: vld2.16 {d0[2], d1[2]}, [r4], r6 @ encoding: [0xa4,0xf9,0x86,0x05]<br>
+@ CHECK-ERRORS: error: alignment must be 32 or omitted<br>
+@ CHECK-ERRORS: vld2.16 {d0[2], d1[2]}, [r4:16], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vld2.16 {d0[2], d1[2]}, [r4:32], r6 @ encoding: [0xa4,0xf9,0x96,0x05]<br>
+@ CHECK-ERRORS: error: alignment must be 32 or omitted<br>
+@ CHECK-ERRORS: vld2.16 {d0[2], d1[2]}, [r4:64], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 32 or omitted<br>
+@ CHECK-ERRORS: vld2.16 {d0[2], d1[2]}, [r4:128], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 32 or omitted<br>
+@ CHECK-ERRORS: vld2.16 {d0[2], d1[2]}, [r4:256], r6<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vld2.16 {d0[2], d2[2]}, [r4]<br>
+ vld2.16 {d0[2], d2[2]}, [r4:16]<br>
+ vld2.16 {d0[2], d2[2]}, [r4:32]<br>
+ vld2.16 {d0[2], d2[2]}, [r4:64]<br>
+ vld2.16 {d0[2], d2[2]}, [r4:128]<br>
+ vld2.16 {d0[2], d2[2]}, [r4:256]<br>
+<br>
+@ CHECK: vld2.16 {d0[2], d2[2]}, [r4] @ encoding: [0xa4,0xf9,0xaf,0x05]<br>
+@ CHECK-ERRORS: error: alignment must be 32 or omitted<br>
+@ CHECK-ERRORS: vld2.16 {d0[2], d2[2]}, [r4:16]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vld2.16 {d0[2], d2[2]}, [r4:32] @ encoding: [0xa4,0xf9,0xbf,0x05]<br>
+@ CHECK-ERRORS: error: alignment must be 32 or omitted<br>
+@ CHECK-ERRORS: vld2.16 {d0[2], d2[2]}, [r4:64]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 32 or omitted<br>
+@ CHECK-ERRORS: vld2.16 {d0[2], d2[2]}, [r4:128]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 32 or omitted<br>
+@ CHECK-ERRORS: vld2.16 {d0[2], d2[2]}, [r4:256]<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vld2.16 {d0[2], d2[2]}, [r4]!<br>
+ vld2.16 {d0[2], d2[2]}, [r4:16]!<br>
+ vld2.16 {d0[2], d2[2]}, [r4:32]!<br>
+ vld2.16 {d0[2], d2[2]}, [r4:64]!<br>
+ vld2.16 {d0[2], d2[2]}, [r4:128]!<br>
+ vld2.16 {d0[2], d2[2]}, [r4:256]!<br>
+<br>
+@ CHECK: vld2.16 {d0[2], d1[2]}, [r4]! @ encoding: [0xa4,0xf9,0xad,0x05]<br>
+@ CHECK-ERRORS: error: alignment must be 32 or omitted<br>
+@ CHECK-ERRORS: vld2.16 {d0[2], d2[2]}, [r4:16]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vld2.16 {d0[2], d1[2]}, [r4:32]! @ encoding: [0xa4,0xf9,0xbd,0x05]<br>
+@ CHECK-ERRORS: error: alignment must be 32 or omitted<br>
+@ CHECK-ERRORS: vld2.16 {d0[2], d2[2]}, [r4:64]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 32 or omitted<br>
+@ CHECK-ERRORS: vld2.16 {d0[2], d2[2]}, [r4:128]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 32 or omitted<br>
+@ CHECK-ERRORS: vld2.16 {d0[2], d2[2]}, [r4:256]!<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vld2.16 {d0[2], d2[2]}, [r4], r6<br>
+ vld2.16 {d0[2], d2[2]}, [r4:16], r6<br>
+ vld2.16 {d0[2], d2[2]}, [r4:32], r6<br>
+ vld2.16 {d0[2], d2[2]}, [r4:64], r6<br>
+ vld2.16 {d0[2], d2[2]}, [r4:128], r6<br>
+ vld2.16 {d0[2], d2[2]}, [r4:256], r6<br>
+<br>
+@ CHECK: vld2.16 {d0[2], d2[2]}, [r4], r6 @ encoding: [0xa4,0xf9,0xa6,0x05]<br>
+@ CHECK-ERRORS: error: alignment must be 32 or omitted<br>
+@ CHECK-ERRORS: vld2.16 {d0[2], d2[2]}, [r4:16], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vld2.16 {d0[2], d2[2]}, [r4:32], r6 @ encoding: [0xa4,0xf9,0xb6,0x05]<br>
+@ CHECK-ERRORS: error: alignment must be 32 or omitted<br>
+@ CHECK-ERRORS: vld2.16 {d0[2], d2[2]}, [r4:64], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 32 or omitted<br>
+@ CHECK-ERRORS: vld2.16 {d0[2], d2[2]}, [r4:128], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 32 or omitted<br>
+@ CHECK-ERRORS: vld2.16 {d0[2], d2[2]}, [r4:256], r6<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vld2.16 {d0[], d1[]}, [r4]<br>
+ vld2.16 {d0[], d1[]}, [r4:16]<br>
+ vld2.16 {d0[], d1[]}, [r4:32]<br>
+ vld2.16 {d0[], d1[]}, [r4:64]<br>
+ vld2.16 {d0[], d1[]}, [r4:128]<br>
+ vld2.16 {d0[], d1[]}, [r4:256]<br>
+<br>
+@ CHECK: vld2.16 {d0[], d1[]}, [r4] @ encoding: [0xa4,0xf9,0x4f,0x0d]<br>
+@ CHECK-ERRORS: error: alignment must be 32 or omitted<br>
+@ CHECK-ERRORS: vld2.16 {d0[], d1[]}, [r4:16]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vld2.16 {d0[], d1[]}, [r4:32] @ encoding: [0xa4,0xf9,0x5f,0x0d]<br>
+@ CHECK-ERRORS: error: alignment must be 32 or omitted<br>
+@ CHECK-ERRORS: vld2.16 {d0[], d1[]}, [r4:64]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 32 or omitted<br>
+@ CHECK-ERRORS: vld2.16 {d0[], d1[]}, [r4:128]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 32 or omitted<br>
+@ CHECK-ERRORS: vld2.16 {d0[], d1[]}, [r4:256]<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vld2.16 {d0[], d1[]}, [r4]!<br>
+ vld2.16 {d0[], d1[]}, [r4:16]!<br>
+ vld2.16 {d0[], d1[]}, [r4:32]!<br>
+ vld2.16 {d0[], d1[]}, [r4:64]!<br>
+ vld2.16 {d0[], d1[]}, [r4:128]!<br>
+ vld2.16 {d0[], d1[]}, [r4:256]!<br>
+<br>
+@ CHECK: vld2.16 {d0[], d1[]}, [r4]! @ encoding: [0xa4,0xf9,0x4d,0x0d]<br>
+@ CHECK-ERRORS: error: alignment must be 32 or omitted<br>
+@ CHECK-ERRORS: vld2.16 {d0[], d1[]}, [r4:16]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vld2.16 {d0[], d1[]}, [r4:32]! @ encoding: [0xa4,0xf9,0x5d,0x0d]<br>
+@ CHECK-ERRORS: error: alignment must be 32 or omitted<br>
+@ CHECK-ERRORS: vld2.16 {d0[], d1[]}, [r4:64]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 32 or omitted<br>
+@ CHECK-ERRORS: vld2.16 {d0[], d1[]}, [r4:128]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 32 or omitted<br>
+@ CHECK-ERRORS: vld2.16 {d0[], d1[]}, [r4:256]!<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vld2.16 {d0[], d1[]}, [r4], r6<br>
+ vld2.16 {d0[], d1[]}, [r4:16], r6<br>
+ vld2.16 {d0[], d1[]}, [r4:32], r6<br>
+ vld2.16 {d0[], d1[]}, [r4:64], r6<br>
+ vld2.16 {d0[], d1[]}, [r4:128], r6<br>
+ vld2.16 {d0[], d1[]}, [r4:256], r6<br>
+<br>
+@ CHECK: vld2.16 {d0[], d1[]}, [r4], r6 @ encoding: [0xa4,0xf9,0x46,0x0d]<br>
+@ CHECK-ERRORS: error: alignment must be 32 or omitted<br>
+@ CHECK-ERRORS: vld2.16 {d0[], d1[]}, [r4:16], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vld2.16 {d0[], d1[]}, [r4:32], r6 @ encoding: [0xa4,0xf9,0x56,0x0d]<br>
+@ CHECK-ERRORS: error: alignment must be 32 or omitted<br>
+@ CHECK-ERRORS: vld2.16 {d0[], d1[]}, [r4:64], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 32 or omitted<br>
+@ CHECK-ERRORS: vld2.16 {d0[], d1[]}, [r4:128], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 32 or omitted<br>
+@ CHECK-ERRORS: vld2.16 {d0[], d1[]}, [r4:256], r6<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vld2.16 {d0[], d2[]}, [r4]<br>
+ vld2.16 {d0[], d2[]}, [r4:16]<br>
+ vld2.16 {d0[], d2[]}, [r4:32]<br>
+ vld2.16 {d0[], d2[]}, [r4:64]<br>
+ vld2.16 {d0[], d2[]}, [r4:128]<br>
+ vld2.16 {d0[], d2[]}, [r4:256]<br>
+<br>
+@ CHECK: vld2.16 {d0[], d2[]}, [r4] @ encoding: [0xa4,0xf9,0x6f,0x0d]<br>
+@ CHECK-ERRORS: error: alignment must be 32 or omitted<br>
+@ CHECK-ERRORS: vld2.16 {d0[], d2[]}, [r4:16]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vld2.16 {d0[], d2[]}, [r4:32] @ encoding: [0xa4,0xf9,0x7f,0x0d]<br>
+@ CHECK-ERRORS: error: alignment must be 32 or omitted<br>
+@ CHECK-ERRORS: vld2.16 {d0[], d2[]}, [r4:64]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 32 or omitted<br>
+@ CHECK-ERRORS: vld2.16 {d0[], d2[]}, [r4:128]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 32 or omitted<br>
+@ CHECK-ERRORS: vld2.16 {d0[], d2[]}, [r4:256]<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vld2.16 {d0[], d2[]}, [r4]!<br>
+ vld2.16 {d0[], d2[]}, [r4:16]!<br>
+ vld2.16 {d0[], d2[]}, [r4:32]!<br>
+ vld2.16 {d0[], d2[]}, [r4:64]!<br>
+ vld2.16 {d0[], d2[]}, [r4:128]!<br>
+ vld2.16 {d0[], d2[]}, [r4:256]!<br>
+<br>
+@ CHECK: vld2.16 {d0[], d2[]}, [r4]! @ encoding: [0xa4,0xf9,0x6d,0x0d]<br>
+@ CHECK-ERRORS: error: alignment must be 32 or omitted<br>
+@ CHECK-ERRORS: vld2.16 {d0[], d2[]}, [r4:16]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vld2.16 {d0[], d2[]}, [r4:32]! @ encoding: [0xa4,0xf9,0x7d,0x0d]<br>
+@ CHECK-ERRORS: error: alignment must be 32 or omitted<br>
+@ CHECK-ERRORS: vld2.16 {d0[], d2[]}, [r4:64]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 32 or omitted<br>
+@ CHECK-ERRORS: vld2.16 {d0[], d2[]}, [r4:128]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 32 or omitted<br>
+@ CHECK-ERRORS: vld2.16 {d0[], d2[]}, [r4:256]!<br>
+<br>
+ vld2.16 {d0[], d2[]}, [r4], r6<br>
+ vld2.16 {d0[], d2[]}, [r4:16], r6<br>
+ vld2.16 {d0[], d2[]}, [r4:32], r6<br>
+ vld2.16 {d0[], d2[]}, [r4:64], r6<br>
+ vld2.16 {d0[], d2[]}, [r4:128], r6<br>
+ vld2.16 {d0[], d2[]}, [r4:256], r6<br>
+<br>
+@ CHECK: vld2.16 {d0[], d2[]}, [r4], r6 @ encoding: [0xa4,0xf9,0x66,0x0d]<br>
+@ CHECK-ERRORS: error: alignment must be 32 or omitted<br>
+@ CHECK-ERRORS: vld2.16 {d0[], d2[]}, [r4:16], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vld2.16 {d0[], d2[]}, [r4:32], r6 @ encoding: [0xa4,0xf9,0x76,0x0d]<br>
+@ CHECK-ERRORS: error: alignment must be 32 or omitted<br>
+@ CHECK-ERRORS: vld2.16 {d0[], d2[]}, [r4:64], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 32 or omitted<br>
+@ CHECK-ERRORS: vld2.16 {d0[], d2[]}, [r4:128], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 32 or omitted<br>
+@ CHECK-ERRORS: vld2.16 {d0[], d2[]}, [r4:256], r6<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vld2.32 {d0, d1}, [r4]<br>
+ vld2.32 {d0, d1}, [r4:16]<br>
+ vld2.32 {d0, d1}, [r4:32]<br>
+ vld2.32 {d0, d1}, [r4:64]<br>
+ vld2.32 {d0, d1}, [r4:128]<br>
+ vld2.32 {d0, d1}, [r4:256]<br>
+<br>
+@ CHECK: vld2.32 {d0, d1}, [r4] @ encoding: [0x24,0xf9,0x8f,0x08]<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted<br>
+@ CHECK-ERRORS: vld2.32 {d0, d1}, [r4:16]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted<br>
+@ CHECK-ERRORS: vld2.32 {d0, d1}, [r4:32]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vld2.32 {d0, d1}, [r4:64] @ encoding: [0x24,0xf9,0x9f,0x08]<br>
+@ CHECK: vld2.32 {d0, d1}, [r4:128] @ encoding: [0x24,0xf9,0xaf,0x08]<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted<br>
+@ CHECK-ERRORS: vld2.32 {d0, d1}, [r4:256]<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vld2.32 {d0, d1}, [r4]!<br>
+ vld2.32 {d0, d1}, [r4:16]!<br>
+ vld2.32 {d0, d1}, [r4:32]!<br>
+ vld2.32 {d0, d1}, [r4:64]!<br>
+ vld2.32 {d0, d1}, [r4:128]!<br>
+ vld2.32 {d0, d1}, [r4:256]!<br>
+<br>
+@ CHECK: vld2.32 {d0, d1}, [r4]! @ encoding: [0x24,0xf9,0x8d,0x08]<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted<br>
+@ CHECK-ERRORS: vld2.32 {d0, d1}, [r4:16]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted<br>
+@ CHECK-ERRORS: vld2.32 {d0, d1}, [r4:32]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vld2.32 {d0, d1}, [r4:64]! @ encoding: [0x24,0xf9,0x9d,0x08]<br>
+@ CHECK: vld2.32 {d0, d1}, [r4:128]! @ encoding: [0x24,0xf9,0xad,0x08]<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted<br>
+@ CHECK-ERRORS: vld2.32 {d0, d1}, [r4:256]!<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vld2.32 {d0, d1}, [r4], r6<br>
+ vld2.32 {d0, d1}, [r4:16], r6<br>
+ vld2.32 {d0, d1}, [r4:32], r6<br>
+ vld2.32 {d0, d1}, [r4:64], r6<br>
+ vld2.32 {d0, d1}, [r4:128], r6<br>
+ vld2.32 {d0, d1}, [r4:256], r6<br>
+<br>
+@ CHECK: vld2.32 {d0, d1}, [r4], r6 @ encoding: [0x24,0xf9,0x86,0x08]<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted<br>
+@ CHECK-ERRORS: vld2.32 {d0, d1}, [r4:16], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted<br>
+@ CHECK-ERRORS: vld2.32 {d0, d1}, [r4:32], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vld2.32 {d0, d1}, [r4:64], r6 @ encoding: [0x24,0xf9,0x96,0x08]<br>
+@ CHECK: vld2.32 {d0, d1}, [r4:128], r6 @ encoding: [0x24,0xf9,0xa6,0x08]<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted<br>
+@ CHECK-ERRORS: vld2.32 {d0, d1}, [r4:256], r6<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vld2.32 {d0, d2}, [r4]<br>
+ vld2.32 {d0, d2}, [r4:16]<br>
+ vld2.32 {d0, d2}, [r4:32]<br>
+ vld2.32 {d0, d2}, [r4:64]<br>
+ vld2.32 {d0, d2}, [r4:128]<br>
+ vld2.32 {d0, d2}, [r4:256]<br>
+<br>
+@ CHECK: vld2.32 {d0, d2}, [r4] @ encoding: [0x24,0xf9,0x8f,0x09]<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted<br>
+@ CHECK-ERRORS: vld2.32 {d0, d2}, [r4:16]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted<br>
+@ CHECK-ERRORS: vld2.32 {d0, d2}, [r4:32]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vld2.32 {d0, d2}, [r4:64] @ encoding: [0x24,0xf9,0x9f,0x09]<br>
+@ CHECK: vld2.32 {d0, d2}, [r4:128] @ encoding: [0x24,0xf9,0xaf,0x09]<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted<br>
+@ CHECK-ERRORS: vld2.32 {d0, d2}, [r4:256]<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vld2.32 {d0, d2}, [r4]!<br>
+ vld2.32 {d0, d2}, [r4:16]!<br>
+ vld2.32 {d0, d2}, [r4:32]!<br>
+ vld2.32 {d0, d2}, [r4:64]!<br>
+ vld2.32 {d0, d2}, [r4:128]!<br>
+ vld2.32 {d0, d2}, [r4:256]!<br>
+<br>
+@ CHECK: vld2.32 {d0, d2}, [r4]! @ encoding: [0x24,0xf9,0x8d,0x09]<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted<br>
+@ CHECK-ERRORS: vld2.32 {d0, d2}, [r4:16]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted<br>
+@ CHECK-ERRORS: vld2.32 {d0, d2}, [r4:32]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vld2.32 {d0, d2}, [r4:64]! @ encoding: [0x24,0xf9,0x9d,0x09]<br>
+@ CHECK: vld2.32 {d0, d2}, [r4:128]! @ encoding: [0x24,0xf9,0xad,0x09]<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted<br>
+@ CHECK-ERRORS: vld2.32 {d0, d2}, [r4:256]!<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vld2.32 {d0, d2}, [r4], r6<br>
+ vld2.32 {d0, d2}, [r4:16], r6<br>
+ vld2.32 {d0, d2}, [r4:32], r6<br>
+ vld2.32 {d0, d2}, [r4:64], r6<br>
+ vld2.32 {d0, d2}, [r4:128], r6<br>
+ vld2.32 {d0, d2}, [r4:256], r6<br>
+<br>
+@ CHECK: vld2.32 {d0, d2}, [r4], r6 @ encoding: [0x24,0xf9,0x86,0x09]<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted<br>
+@ CHECK-ERRORS: vld2.32 {d0, d2}, [r4:16], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted<br>
+@ CHECK-ERRORS: vld2.32 {d0, d2}, [r4:32], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vld2.32 {d0, d2}, [r4:64], r6 @ encoding: [0x24,0xf9,0x96,0x09]<br>
+@ CHECK: vld2.32 {d0, d2}, [r4:128], r6 @ encoding: [0x24,0xf9,0xa6,0x09]<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted<br>
+@ CHECK-ERRORS: vld2.32 {d0, d2}, [r4:256], r6<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vld2.32 {d0, d1, d2, d3}, [r4]<br>
+ vld2.32 {d0, d1, d2, d3}, [r4:16]<br>
+ vld2.32 {d0, d1, d2, d3}, [r4:32]<br>
+ vld2.32 {d0, d1, d2, d3}, [r4:64]<br>
+ vld2.32 {d0, d1, d2, d3}, [r4:128]<br>
+ vld2.32 {d0, d1, d2, d3}, [r4:256]<br>
+<br>
+@ CHECK: vld2.32 {d0, d1, d2, d3}, [r4] @ encoding: [0x24,0xf9,0x8f,0x03]<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted<br>
+@ CHECK-ERRORS: vld2.32 {d0, d1, d2, d3}, [r4:16]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted<br>
+@ CHECK-ERRORS: vld2.32 {d0, d1, d2, d3}, [r4:32]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vld2.32 {d0, d1, d2, d3}, [r4:64] @ encoding: [0x24,0xf9,0x9f,0x03]<br>
+@ CHECK: vld2.32 {d0, d1, d2, d3}, [r4:128] @ encoding: [0x24,0xf9,0xaf,0x03]<br>
+@ CHECK: vld2.32 {d0, d1, d2, d3}, [r4:256] @ encoding: [0x24,0xf9,0xbf,0x03]<br>
+<br>
+ vld2.32 {d0, d1, d2, d3}, [r4]!<br>
+ vld2.32 {d0, d1, d2, d3}, [r4:16]!<br>
+ vld2.32 {d0, d1, d2, d3}, [r4:32]!<br>
+ vld2.32 {d0, d1, d2, d3}, [r4:64]!<br>
+ vld2.32 {d0, d1, d2, d3}, [r4:128]!<br>
+ vld2.32 {d0, d1, d2, d3}, [r4:256]!<br>
+<br>
+@ CHECK: vld2.32 {d0, d1, d2, d3}, [r4]! @ encoding: [0x24,0xf9,0x8d,0x03]<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted<br>
+@ CHECK-ERRORS: vld2.32 {d0, d1, d2, d3}, [r4:16]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted<br>
+@ CHECK-ERRORS: vld2.32 {d0, d1, d2, d3}, [r4:32]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vld2.32 {d0, d1, d2, d3}, [r4:64]! @ encoding: [0x24,0xf9,0x9d,0x03]<br>
+@ CHECK: vld2.32 {d0, d1, d2, d3}, [r4:128]! @ encoding: [0x24,0xf9,0xad,0x03]<br>
+@ CHECK: vld2.32 {d0, d1, d2, d3}, [r4:256]! @ encoding: [0x24,0xf9,0xbd,0x03]<br>
+<br>
+ vld2.32 {d0, d1, d2, d3}, [r4], r6<br>
+ vld2.32 {d0, d1, d2, d3}, [r4:16], r6<br>
+ vld2.32 {d0, d1, d2, d3}, [r4:32], r6<br>
+ vld2.32 {d0, d1, d2, d3}, [r4:64], r6<br>
+ vld2.32 {d0, d1, d2, d3}, [r4:128], r6<br>
+ vld2.32 {d0, d1, d2, d3}, [r4:256], r6<br>
+<br>
+@ CHECK: vld2.32 {d0, d1, d2, d3}, [r4], r6 @ encoding: [0x24,0xf9,0x86,0x03]<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted<br>
+@ CHECK-ERRORS: vld2.32 {d0, d1, d2, d3}, [r4:16], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted<br>
+@ CHECK-ERRORS: vld2.32 {d0, d1, d2, d3}, [r4:32], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vld2.32 {d0, d1, d2, d3}, [r4:64], r6 @ encoding: [0x24,0xf9,0x96,0x03]<br>
+@ CHECK: vld2.32 {d0, d1, d2, d3}, [r4:128], r6 @ encoding: [0x24,0xf9,0xa6,0x03]<br>
+@ CHECK: vld2.32 {d0, d1, d2, d3}, [r4:256], r6 @ encoding: [0x24,0xf9,0xb6,0x03]<br>
+<br>
+ vld2.32 {d0[1], d1[1]}, [r4]<br>
+ vld2.32 {d0[1], d1[1]}, [r4:16]<br>
+ vld2.32 {d0[1], d1[1]}, [r4:32]<br>
+ vld2.32 {d0[1], d1[1]}, [r4:64]<br>
+ vld2.32 {d0[1], d1[1]}, [r4:128]<br>
+ vld2.32 {d0[1], d1[1]}, [r4:256]<br>
+<br>
+@ CHECK: vld2.32 {d0[1], d1[1]}, [r4] @ encoding: [0xa4,0xf9,0x8f,0x09]<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vld2.32 {d0[1], d1[1]}, [r4:16]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vld2.32 {d0[1], d1[1]}, [r4:32]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vld2.32 {d0[1], d1[1]}, [r4:64] @ encoding: [0xa4,0xf9,0x9f,0x09]<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vld2.32 {d0[1], d1[1]}, [r4:128]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vld2.32 {d0[1], d1[1]}, [r4:256]<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vld2.32 {d0[1], d1[1]}, [r4]!<br>
+ vld2.32 {d0[1], d1[1]}, [r4:16]!<br>
+ vld2.32 {d0[1], d1[1]}, [r4:32]!<br>
+ vld2.32 {d0[1], d1[1]}, [r4:64]!<br>
+ vld2.32 {d0[1], d1[1]}, [r4:128]!<br>
+ vld2.32 {d0[1], d1[1]}, [r4:256]!<br>
+<br>
+@ CHECK: vld2.32 {d0[1], d1[1]}, [r4]! @ encoding: [0xa4,0xf9,0x8d,0x09]<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vld2.32 {d0[1], d1[1]}, [r4:16]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vld2.32 {d0[1], d1[1]}, [r4:32]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vld2.32 {d0[1], d1[1]}, [r4:64]! @ encoding: [0xa4,0xf9,0x9d,0x09]<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vld2.32 {d0[1], d1[1]}, [r4:128]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vld2.32 {d0[1], d1[1]}, [r4:256]!<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vld2.32 {d0[1], d1[1]}, [r4], r6<br>
+ vld2.32 {d0[1], d1[1]}, [r4:16], r6<br>
+ vld2.32 {d0[1], d1[1]}, [r4:32], r6<br>
+ vld2.32 {d0[1], d1[1]}, [r4:64], r6<br>
+ vld2.32 {d0[1], d1[1]}, [r4:128], r6<br>
+ vld2.32 {d0[1], d1[1]}, [r4:256], r6<br>
+<br>
+@ CHECK: vld2.32 {d0[1], d1[1]}, [r4], r6 @ encoding: [0xa4,0xf9,0x86,0x09]<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vld2.32 {d0[1], d1[1]}, [r4:16], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vld2.32 {d0[1], d1[1]}, [r4:32], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vld2.32 {d0[1], d1[1]}, [r4:64], r6 @ encoding: [0xa4,0xf9,0x96,0x09]<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vld2.32 {d0[1], d1[1]}, [r4:128], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vld2.32 {d0[1], d1[1]}, [r4:256], r6<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vld2.32 {d0[1], d2[1]}, [r4]<br>
+ vld2.32 {d0[1], d2[1]}, [r4:16]<br>
+ vld2.32 {d0[1], d2[1]}, [r4:32]<br>
+ vld2.32 {d0[1], d2[1]}, [r4:64]<br>
+ vld2.32 {d0[1], d2[1]}, [r4:128]<br>
+ vld2.32 {d0[1], d2[1]}, [r4:256]<br>
+<br>
+@ CHECK: vld2.32 {d0[1], d2[1]}, [r4] @ encoding: [0xa4,0xf9,0xcf,0x09]<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vld2.32 {d0[1], d2[1]}, [r4:16]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vld2.32 {d0[1], d2[1]}, [r4:32]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vld2.32 {d0[1], d2[1]}, [r4:64] @ encoding: [0xa4,0xf9,0xdf,0x09]<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vld2.32 {d0[1], d2[1]}, [r4:128]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vld2.32 {d0[1], d2[1]}, [r4:256]<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vld2.32 {d0[1], d2[1]}, [r4]!<br>
+ vld2.32 {d0[1], d2[1]}, [r4:16]!<br>
+ vld2.32 {d0[1], d2[1]}, [r4:32]!<br>
+ vld2.32 {d0[1], d2[1]}, [r4:64]!<br>
+ vld2.32 {d0[1], d2[1]}, [r4:128]!<br>
+ vld2.32 {d0[1], d2[1]}, [r4:256]!<br>
+<br>
+@ CHECK: vld2.32 {d0[1], d2[1]}, [r4]! @ encoding: [0xa4,0xf9,0xcd,0x09]<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vld2.32 {d0[1], d2[1]}, [r4:16]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vld2.32 {d0[1], d2[1]}, [r4:32]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vld2.32 {d0[1], d2[1]}, [r4:64]! @ encoding: [0xa4,0xf9,0xdd,0x09]<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vld2.32 {d0[1], d2[1]}, [r4:128]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vld2.32 {d0[1], d2[1]}, [r4:256]!<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vld2.32 {d0[1], d2[1]}, [r4], r6<br>
+ vld2.32 {d0[1], d2[1]}, [r4:16], r6<br>
+ vld2.32 {d0[1], d2[1]}, [r4:32], r6<br>
+ vld2.32 {d0[1], d2[1]}, [r4:64], r6<br>
+ vld2.32 {d0[1], d2[1]}, [r4:128], r6<br>
+ vld2.32 {d0[1], d2[1]}, [r4:256], r6<br>
+<br>
+@ CHECK: vld2.32 {d0[1], d2[1]}, [r4], r6 @ encoding: [0xa4,0xf9,0xc6,0x09]<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vld2.32 {d0[1], d2[1]}, [r4:16], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vld2.32 {d0[1], d2[1]}, [r4:32], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vld2.32 {d0[1], d2[1]}, [r4:64], r6 @ encoding: [0xa4,0xf9,0xd6,0x09]<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vld2.32 {d0[1], d2[1]}, [r4:128], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vld2.32 {d0[1], d2[1]}, [r4:256], r6<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vld2.32 {d0[], d1[]}, [r4]<br>
+ vld2.32 {d0[], d1[]}, [r4:16]<br>
+ vld2.32 {d0[], d1[]}, [r4:32]<br>
+ vld2.32 {d0[], d1[]}, [r4:64]<br>
+ vld2.32 {d0[], d1[]}, [r4:128]<br>
+ vld2.32 {d0[], d1[]}, [r4:256]<br>
+<br>
+@ CHECK: vld2.32 {d0[], d1[]}, [r4] @ encoding: [0xa4,0xf9,0x8f,0x0d]<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vld2.32 {d0[], d1[]}, [r4:16]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vld2.32 {d0[], d1[]}, [r4:32]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vld2.32 {d0[], d1[]}, [r4:64] @ encoding: [0xa4,0xf9,0x9f,0x0d]<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vld2.32 {d0[], d1[]}, [r4:128]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vld2.32 {d0[], d1[]}, [r4:256]<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vld2.32 {d0[], d1[]}, [r4]!<br>
+ vld2.32 {d0[], d1[]}, [r4:16]!<br>
+ vld2.32 {d0[], d1[]}, [r4:32]!<br>
+ vld2.32 {d0[], d1[]}, [r4:64]!<br>
+ vld2.32 {d0[], d1[]}, [r4:128]!<br>
+ vld2.32 {d0[], d1[]}, [r4:256]!<br>
+<br>
+@ CHECK: vld2.32 {d0[], d1[]}, [r4]! @ encoding: [0xa4,0xf9,0x8d,0x0d]<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vld2.32 {d0[], d1[]}, [r4:16]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vld2.32 {d0[], d1[]}, [r4:32]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vld2.32 {d0[], d1[]}, [r4:64]! @ encoding: [0xa4,0xf9,0x9d,0x0d]<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vld2.32 {d0[], d1[]}, [r4:128]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vld2.32 {d0[], d1[]}, [r4:256]!<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vld2.32 {d0[], d1[]}, [r4], r6<br>
+ vld2.32 {d0[], d1[]}, [r4:16], r6<br>
+ vld2.32 {d0[], d1[]}, [r4:32], r6<br>
+ vld2.32 {d0[], d1[]}, [r4:64], r6<br>
+ vld2.32 {d0[], d1[]}, [r4:128], r6<br>
+ vld2.32 {d0[], d1[]}, [r4:256], r6<br>
+<br>
+@ CHECK: vld2.32 {d0[], d1[]}, [r4], r6 @ encoding: [0xa4,0xf9,0x86,0x0d]<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vld2.32 {d0[], d1[]}, [r4:16], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vld2.32 {d0[], d1[]}, [r4:32], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vld2.32 {d0[], d1[]}, [r4:64], r6 @ encoding: [0xa4,0xf9,0x96,0x0d]<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vld2.32 {d0[], d1[]}, [r4:128], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vld2.32 {d0[], d1[]}, [r4:256], r6<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vld2.32 {d0[], d2[]}, [r4]<br>
+ vld2.32 {d0[], d2[]}, [r4:16]<br>
+ vld2.32 {d0[], d2[]}, [r4:32]<br>
+ vld2.32 {d0[], d2[]}, [r4:64]<br>
+ vld2.32 {d0[], d2[]}, [r4:128]<br>
+ vld2.32 {d0[], d2[]}, [r4:256]<br>
+<br>
+@ CHECK: vld2.32 {d0[], d2[]}, [r4] @ encoding: [0xa4,0xf9,0xaf,0x0d]<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vld2.32 {d0[], d2[]}, [r4:16]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vld2.32 {d0[], d2[]}, [r4:32]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vld2.32 {d0[], d2[]}, [r4:64] @ encoding: [0xa4,0xf9,0xbf,0x0d]<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vld2.32 {d0[], d2[]}, [r4:128]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vld2.32 {d0[], d2[]}, [r4:256]<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vld2.32 {d0[], d2[]}, [r4]!<br>
+ vld2.32 {d0[], d2[]}, [r4:16]!<br>
+ vld2.32 {d0[], d2[]}, [r4:32]!<br>
+ vld2.32 {d0[], d2[]}, [r4:64]!<br>
+ vld2.32 {d0[], d2[]}, [r4:128]!<br>
+ vld2.32 {d0[], d2[]}, [r4:256]!<br>
+<br>
+@ CHECK: vld2.32 {d0[], d2[]}, [r4]! @ encoding: [0xa4,0xf9,0xad,0x0d]<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vld2.32 {d0[], d2[]}, [r4:16]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vld2.32 {d0[], d2[]}, [r4:32]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vld2.32 {d0[], d2[]}, [r4:64]! @ encoding: [0xa4,0xf9,0xbd,0x0d]<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vld2.32 {d0[], d2[]}, [r4:128]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vld2.32 {d0[], d2[]}, [r4:256]!<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vld2.32 {d0[], d2[]}, [r4], r6<br>
+ vld2.32 {d0[], d2[]}, [r4:16], r6<br>
+ vld2.32 {d0[], d2[]}, [r4:32], r6<br>
+ vld2.32 {d0[], d2[]}, [r4:64], r6<br>
+ vld2.32 {d0[], d2[]}, [r4:128], r6<br>
+ vld2.32 {d0[], d2[]}, [r4:256], r6<br>
+<br>
+@ CHECK: vld2.32 {d0[], d2[]}, [r4], r6 @ encoding: [0xa4,0xf9,0xa6,0x0d]<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vld2.32 {d0[], d2[]}, [r4:16], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vld2.32 {d0[], d2[]}, [r4:32], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vld2.32 {d0[], d2[]}, [r4:64], r6 @ encoding: [0xa4,0xf9,0xb6,0x0d]<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vld2.32 {d0[], d2[]}, [r4:128], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vld2.32 {d0[], d2[]}, [r4:256], r6<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vld3.8 {d0, d1, d2}, [r4]<br>
+ vld3.8 {d0, d1, d2}, [r4:16]<br>
+ vld3.8 {d0, d1, d2}, [r4:32]<br>
+ vld3.8 {d0, d1, d2}, [r4:64]<br>
+ vld3.8 {d0, d1, d2}, [r4:128]<br>
+ vld3.8 {d0, d1, d2}, [r4:256]<br>
+<br>
+@ CHECK: vld3.8 {d0, d1, d2}, [r4] @ encoding: [0x24,0xf9,0x0f,0x04]<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vld3.8 {d0, d1, d2}, [r4:16]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vld3.8 {d0, d1, d2}, [r4:32]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vld3.8 {d0, d1, d2}, [r4:64] @ encoding: [0x24,0xf9,0x1f,0x04]<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vld3.8 {d0, d1, d2}, [r4:128]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vld3.8 {d0, d1, d2}, [r4:256]<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vld3.8 {d0, d1, d2}, [r4]!<br>
+ vld3.8 {d0, d1, d2}, [r4:16]!<br>
+ vld3.8 {d0, d1, d2}, [r4:32]!<br>
+ vld3.8 {d0, d1, d2}, [r4:64]!<br>
+ vld3.8 {d0, d1, d2}, [r4:128]!<br>
+ vld3.8 {d0, d1, d2}, [r4:256]!<br>
+<br>
+@ CHECK: vld3.8 {d0, d1, d2}, [r4]! @ encoding: [0x24,0xf9,0x0d,0x04]<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vld3.8 {d0, d1, d2}, [r4:16]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vld3.8 {d0, d1, d2}, [r4:32]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vld3.8 {d0, d1, d2}, [r4:64]! @ encoding: [0x24,0xf9,0x1d,0x04]<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vld3.8 {d0, d1, d2}, [r4:128]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vld3.8 {d0, d1, d2}, [r4:256]!<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vld3.8 {d0, d1, d2}, [r4], r6<br>
+ vld3.8 {d0, d1, d2}, [r4:16], r6<br>
+ vld3.8 {d0, d1, d2}, [r4:32], r6<br>
+ vld3.8 {d0, d1, d2}, [r4:64], r6<br>
+ vld3.8 {d0, d1, d2}, [r4:128], r6<br>
+ vld3.8 {d0, d1, d2}, [r4:256], r6<br>
+<br>
+@ CHECK: vld3.8 {d0, d1, d2}, [r4], r6 @ encoding: [0x24,0xf9,0x06,0x04]<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vld3.8 {d0, d1, d2}, [r4:16], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vld3.8 {d0, d1, d2}, [r4:32], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vld3.8 {d0, d1, d2}, [r4:64], r6 @ encoding: [0x24,0xf9,0x16,0x04]<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vld3.8 {d0, d1, d2}, [r4:128], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vld3.8 {d0, d1, d2}, [r4:256], r6<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vld3.8 {d0, d2, d4}, [r4]<br>
+ vld3.8 {d0, d2, d4}, [r4:16]<br>
+ vld3.8 {d0, d2, d4}, [r4:32]<br>
+ vld3.8 {d0, d2, d4}, [r4:64]<br>
+ vld3.8 {d0, d2, d4}, [r4:128]<br>
+ vld3.8 {d0, d2, d4}, [r4:256]<br>
+<br>
+@ CHECK: vld3.8 {d0, d2, d4}, [r4] @ encoding: [0x24,0xf9,0x0f,0x05]<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vld3.8 {d0, d2, d4}, [r4:16]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vld3.8 {d0, d2, d4}, [r4:32]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vld3.8 {d0, d2, d4}, [r4:64] @ encoding: [0x24,0xf9,0x1f,0x05]<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vld3.8 {d0, d2, d4}, [r4:128]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vld3.8 {d0, d2, d4}, [r4:256]<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vld3.8 {d0, d2, d4}, [r4]!<br>
+ vld3.8 {d0, d2, d4}, [r4:16]!<br>
+ vld3.8 {d0, d2, d4}, [r4:32]!<br>
+ vld3.8 {d0, d2, d4}, [r4:64]!<br>
+ vld3.8 {d0, d2, d4}, [r4:128]!<br>
+ vld3.8 {d0, d2, d4}, [r4:256]!<br>
+<br>
+@ CHECK: vld3.8 {d0, d2, d4}, [r4]! @ encoding: [0x24,0xf9,0x0d,0x05]<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vld3.8 {d0, d2, d4}, [r4:16]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vld3.8 {d0, d2, d4}, [r4:32]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vld3.8 {d0, d2, d4}, [r4:64]! @ encoding: [0x24,0xf9,0x1d,0x05]<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vld3.8 {d0, d2, d4}, [r4:128]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vld3.8 {d0, d2, d4}, [r4:256]!<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vld3.8 {d0, d2, d4}, [r4], r6<br>
+ vld3.8 {d0, d2, d4}, [r4:16], r6<br>
+ vld3.8 {d0, d2, d4}, [r4:32], r6<br>
+ vld3.8 {d0, d2, d4}, [r4:64], r6<br>
+ vld3.8 {d0, d2, d4}, [r4:128], r6<br>
+ vld3.8 {d0, d2, d4}, [r4:256], r6<br>
+<br>
+@ CHECK: vld3.8 {d0, d2, d4}, [r4], r6 @ encoding: [0x24,0xf9,0x06,0x05]<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vld3.8 {d0, d2, d4}, [r4:16], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vld3.8 {d0, d2, d4}, [r4:32], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vld3.8 {d0, d2, d4}, [r4:64], r6 @ encoding: [0x24,0xf9,0x16,0x05]<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vld3.8 {d0, d2, d4}, [r4:128], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vld3.8 {d0, d2, d4}, [r4:256], r6<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vld3.8 {d0[1], d1[1], d2[1]}, [r4]<br>
+ vld3.8 {d0[1], d1[1], d2[1]}, [r4:16]<br>
+ vld3.8 {d0[1], d1[1], d2[1]}, [r4:32]<br>
+ vld3.8 {d0[1], d1[1], d2[1]}, [r4:64]<br>
+ vld3.8 {d0[1], d1[1], d2[1]}, [r4:128]<br>
+ vld3.8 {d0[1], d1[1], d2[1]}, [r4:256]<br>
+<br>
+@ CHECK: vld3.8 {d0[1], d1[1], d2[1]}, [r4] @ encoding: [0xa4,0xf9,0x2f,0x02]<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vld3.8 {d0[1], d1[1], d2[1]}, [r4:16]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vld3.8 {d0[1], d1[1], d2[1]}, [r4:32]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vld3.8 {d0[1], d1[1], d2[1]}, [r4:64]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vld3.8 {d0[1], d1[1], d2[1]}, [r4:128]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vld3.8 {d0[1], d1[1], d2[1]}, [r4:256]<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vld3.8 {d0[1], d1[1], d2[1]}, [r4]!<br>
+ vld3.8 {d0[1], d1[1], d2[1]}, [r4:16]!<br>
+ vld3.8 {d0[1], d1[1], d2[1]}, [r4:32]!<br>
+ vld3.8 {d0[1], d1[1], d2[1]}, [r4:64]!<br>
+ vld3.8 {d0[1], d1[1], d2[1]}, [r4:128]!<br>
+ vld3.8 {d0[1], d1[1], d2[1]}, [r4:256]!<br>
+<br>
+@ CHECK: vld3.8 {d0[1], d1[1], d2[1]}, [r4]! @ encoding: [0xa4,0xf9,0x2d,0x02]<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vld3.8 {d0[1], d1[1], d2[1]}, [r4:16]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vld3.8 {d0[1], d1[1], d2[1]}, [r4:32]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vld3.8 {d0[1], d1[1], d2[1]}, [r4:64]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vld3.8 {d0[1], d1[1], d2[1]}, [r4:128]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vld3.8 {d0[1], d1[1], d2[1]}, [r4:256]!<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vld3.8 {d0[1], d1[1], d2[1]}, [r4], r6<br>
+ vld3.8 {d0[1], d1[1], d2[1]}, [r4:16], r6<br>
+ vld3.8 {d0[1], d1[1], d2[1]}, [r4:32], r6<br>
+ vld3.8 {d0[1], d1[1], d2[1]}, [r4:64], r6<br>
+ vld3.8 {d0[1], d1[1], d2[1]}, [r4:128], r6<br>
+ vld3.8 {d0[1], d1[1], d2[1]}, [r4:256], r6<br>
+<br>
+@ CHECK: vld3.8 {d0[1], d1[1], d2[1]}, [r4], r6 @ encoding: [0xa4,0xf9,0x26,0x02]<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vld3.8 {d0[1], d1[1], d2[1]}, [r4:16], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vld3.8 {d0[1], d1[1], d2[1]}, [r4:32], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vld3.8 {d0[1], d1[1], d2[1]}, [r4:64], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vld3.8 {d0[1], d1[1], d2[1]}, [r4:128], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vld3.8 {d0[1], d1[1], d2[1]}, [r4:256], r6<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vld3.8 {d0[], d1[], d2[]}, [r4]<br>
+ vld3.8 {d0[], d1[], d2[]}, [r4:16]<br>
+ vld3.8 {d0[], d1[], d2[]}, [r4:32]<br>
+ vld3.8 {d0[], d1[], d2[]}, [r4:64]<br>
+ vld3.8 {d0[], d1[], d2[]}, [r4:128]<br>
+ vld3.8 {d0[], d1[], d2[]}, [r4:256]<br>
+<br>
+@ CHECK: vld3.8 {d0[], d1[], d2[]}, [r4] @ encoding: [0xa4,0xf9,0x0f,0x0e]<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vld3.8 {d0[], d1[], d2[]}, [r4:16]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vld3.8 {d0[], d1[], d2[]}, [r4:32]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vld3.8 {d0[], d1[], d2[]}, [r4:64]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vld3.8 {d0[], d1[], d2[]}, [r4:128]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vld3.8 {d0[], d1[], d2[]}, [r4:256]<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vld3.8 {d0[], d1[], d2[]}, [r4]!<br>
+ vld3.8 {d0[], d1[], d2[]}, [r4:16]!<br>
+ vld3.8 {d0[], d1[], d2[]}, [r4:32]!<br>
+ vld3.8 {d0[], d1[], d2[]}, [r4:64]!<br>
+ vld3.8 {d0[], d1[], d2[]}, [r4:128]!<br>
+ vld3.8 {d0[], d1[], d2[]}, [r4:256]!<br>
+<br>
+@ CHECK: vld3.8 {d0[], d1[], d2[]}, [r4]! @ encoding: [0xa4,0xf9,0x0d,0x0e]<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vld3.8 {d0[], d1[], d2[]}, [r4:16]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vld3.8 {d0[], d1[], d2[]}, [r4:32]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vld3.8 {d0[], d1[], d2[]}, [r4:64]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vld3.8 {d0[], d1[], d2[]}, [r4:128]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vld3.8 {d0[], d1[], d2[]}, [r4:256]!<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vld3.8 {d0[], d1[], d2[]}, [r4], r6<br>
+ vld3.8 {d0[], d1[], d2[]}, [r4:16], r6<br>
+ vld3.8 {d0[], d1[], d2[]}, [r4:32], r6<br>
+ vld3.8 {d0[], d1[], d2[]}, [r4:64], r6<br>
+ vld3.8 {d0[], d1[], d2[]}, [r4:128], r6<br>
+ vld3.8 {d0[], d1[], d2[]}, [r4:256], r6<br>
+<br>
+@ CHECK: vld3.8 {d0[], d1[], d2[]}, [r4], r6 @ encoding: [0xa4,0xf9,0x06,0x0e]<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vld3.8 {d0[], d1[], d2[]}, [r4:16], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vld3.8 {d0[], d1[], d2[]}, [r4:32], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vld3.8 {d0[], d1[], d2[]}, [r4:64], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vld3.8 {d0[], d1[], d2[]}, [r4:128], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vld3.8 {d0[], d1[], d2[]}, [r4:256], r6<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vld3.8 {d0[], d2[], d4[]}, [r4]<br>
+ vld3.8 {d0[], d2[], d4[]}, [r4:16]<br>
+ vld3.8 {d0[], d2[], d4[]}, [r4:32]<br>
+ vld3.8 {d0[], d2[], d4[]}, [r4:64]<br>
+ vld3.8 {d0[], d2[], d4[]}, [r4:128]<br>
+ vld3.8 {d0[], d2[], d4[]}, [r4:256]<br>
+<br>
+@ CHECK: vld3.8 {d0[], d2[], d4[]}, [r4] @ encoding: [0xa4,0xf9,0x2f,0x0e]<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vld3.8 {d0[], d2[], d4[]}, [r4:16]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vld3.8 {d0[], d2[], d4[]}, [r4:32]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vld3.8 {d0[], d2[], d4[]}, [r4:64]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vld3.8 {d0[], d2[], d4[]}, [r4:128]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vld3.8 {d0[], d2[], d4[]}, [r4:256]<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vld3.8 {d0[], d2[], d4[]}, [r4]!<br>
+ vld3.8 {d0[], d2[], d4[]}, [r4:16]!<br>
+ vld3.8 {d0[], d2[], d4[]}, [r4:32]!<br>
+ vld3.8 {d0[], d2[], d4[]}, [r4:64]!<br>
+ vld3.8 {d0[], d2[], d4[]}, [r4:128]!<br>
+ vld3.8 {d0[], d2[], d4[]}, [r4:256]!<br>
+<br>
+@ CHECK: vld3.8 {d0[], d1[], d2[]}, [r4]! @ encoding: [0xa4,0xf9,0x2d,0x0e]<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vld3.8 {d0[], d2[], d4[]}, [r4:16]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vld3.8 {d0[], d2[], d4[]}, [r4:32]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vld3.8 {d0[], d2[], d4[]}, [r4:64]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vld3.8 {d0[], d2[], d4[]}, [r4:128]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vld3.8 {d0[], d2[], d4[]}, [r4:256]!<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vld3.8 {d0[], d2[], d4[]}, [r4], r6<br>
+ vld3.8 {d0[], d2[], d4[]}, [r4:16], r6<br>
+ vld3.8 {d0[], d2[], d4[]}, [r4:32], r6<br>
+ vld3.8 {d0[], d2[], d4[]}, [r4:64], r6<br>
+ vld3.8 {d0[], d2[], d4[]}, [r4:128], r6<br>
+ vld3.8 {d0[], d2[], d4[]}, [r4:256], r6<br>
+<br>
+@ CHECK: vld3.8 {d0[], d2[], d4[]}, [r4], r6 @ encoding: [0xa4,0xf9,0x26,0x0e]<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vld3.8 {d0[], d2[], d4[]}, [r4:16], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vld3.8 {d0[], d2[], d4[]}, [r4:32], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vld3.8 {d0[], d2[], d4[]}, [r4:64], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vld3.8 {d0[], d2[], d4[]}, [r4:128], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vld3.8 {d0[], d2[], d4[]}, [r4:256], r6<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vld3.16 {d0, d1, d2}, [r4]<br>
+ vld3.16 {d0, d1, d2}, [r4:16]<br>
+ vld3.16 {d0, d1, d2}, [r4:32]<br>
+ vld3.16 {d0, d1, d2}, [r4:64]<br>
+ vld3.16 {d0, d1, d2}, [r4:128]<br>
+ vld3.16 {d0, d1, d2}, [r4:256]<br>
+<br>
+@ CHECK: vld3.16 {d0, d1, d2}, [r4] @ encoding: [0x24,0xf9,0x4f,0x04]<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vld3.16 {d0, d1, d2}, [r4:16]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vld3.16 {d0, d1, d2}, [r4:32]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vld3.16 {d0, d1, d2}, [r4:64] @ encoding: [0x24,0xf9,0x5f,0x04]<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vld3.16 {d0, d1, d2}, [r4:128]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vld3.16 {d0, d1, d2}, [r4:256]<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vld3.16 {d0, d1, d2}, [r4]!<br>
+ vld3.16 {d0, d1, d2}, [r4:16]!<br>
+ vld3.16 {d0, d1, d2}, [r4:32]!<br>
+ vld3.16 {d0, d1, d2}, [r4:64]!<br>
+ vld3.16 {d0, d1, d2}, [r4:128]!<br>
+ vld3.16 {d0, d1, d2}, [r4:256]!<br>
+<br>
+@ CHECK: vld3.16 {d0, d1, d2}, [r4]! @ encoding: [0x24,0xf9,0x4d,0x04]<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vld3.16 {d0, d1, d2}, [r4:16]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vld3.16 {d0, d1, d2}, [r4:32]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vld3.16 {d0, d1, d2}, [r4:64]! @ encoding: [0x24,0xf9,0x5d,0x04]<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vld3.16 {d0, d1, d2}, [r4:128]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vld3.16 {d0, d1, d2}, [r4:256]!<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vld3.16 {d0, d1, d2}, [r4], r6<br>
+ vld3.16 {d0, d1, d2}, [r4:16], r6<br>
+ vld3.16 {d0, d1, d2}, [r4:32], r6<br>
+ vld3.16 {d0, d1, d2}, [r4:64], r6<br>
+ vld3.16 {d0, d1, d2}, [r4:128], r6<br>
+ vld3.16 {d0, d1, d2}, [r4:256], r6<br>
+<br>
+@ CHECK: vld3.16 {d0, d1, d2}, [r4], r6 @ encoding: [0x24,0xf9,0x46,0x04]<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vld3.16 {d0, d1, d2}, [r4:16], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vld3.16 {d0, d1, d2}, [r4:32], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vld3.16 {d0, d1, d2}, [r4:64], r6 @ encoding: [0x24,0xf9,0x56,0x04]<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vld3.16 {d0, d1, d2}, [r4:128], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vld3.16 {d0, d1, d2}, [r4:256], r6<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vld3.16 {d0, d2, d4}, [r4]<br>
+ vld3.16 {d0, d2, d4}, [r4:16]<br>
+ vld3.16 {d0, d2, d4}, [r4:32]<br>
+ vld3.16 {d0, d2, d4}, [r4:64]<br>
+ vld3.16 {d0, d2, d4}, [r4:128]<br>
+ vld3.16 {d0, d2, d4}, [r4:256]<br>
+<br>
+@ CHECK: vld3.16 {d0, d2, d4}, [r4] @ encoding: [0x24,0xf9,0x4f,0x05]<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vld3.16 {d0, d2, d4}, [r4:16]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vld3.16 {d0, d2, d4}, [r4:32]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vld3.16 {d0, d2, d4}, [r4:64] @ encoding: [0x24,0xf9,0x5f,0x05]<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vld3.16 {d0, d2, d4}, [r4:128]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vld3.16 {d0, d2, d4}, [r4:256]<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vld3.16 {d0, d2, d4}, [r4]!<br>
+ vld3.16 {d0, d2, d4}, [r4:16]!<br>
+ vld3.16 {d0, d2, d4}, [r4:32]!<br>
+ vld3.16 {d0, d2, d4}, [r4:64]!<br>
+ vld3.16 {d0, d2, d4}, [r4:128]!<br>
+ vld3.16 {d0, d2, d4}, [r4:256]!<br>
+<br>
+@ CHECK: vld3.16 {d0, d2, d4}, [r4]! @ encoding: [0x24,0xf9,0x4d,0x05]<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vld3.16 {d0, d2, d4}, [r4:16]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vld3.16 {d0, d2, d4}, [r4:32]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vld3.16 {d0, d2, d4}, [r4:64]! @ encoding: [0x24,0xf9,0x5d,0x05]<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vld3.16 {d0, d2, d4}, [r4:128]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vld3.16 {d0, d2, d4}, [r4:256]!<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vld3.16 {d0, d2, d4}, [r4], r6<br>
+ vld3.16 {d0, d2, d4}, [r4:16], r6<br>
+ vld3.16 {d0, d2, d4}, [r4:32], r6<br>
+ vld3.16 {d0, d2, d4}, [r4:64], r6<br>
+ vld3.16 {d0, d2, d4}, [r4:128], r6<br>
+ vld3.16 {d0, d2, d4}, [r4:256], r6<br>
+<br>
+@ CHECK: vld3.16 {d0, d2, d4}, [r4], r6 @ encoding: [0x24,0xf9,0x46,0x05]<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vld3.16 {d0, d2, d4}, [r4:16], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vld3.16 {d0, d2, d4}, [r4:32], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vld3.16 {d0, d2, d4}, [r4:64], r6 @ encoding: [0x24,0xf9,0x56,0x05]<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vld3.16 {d0, d2, d4}, [r4:128], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vld3.16 {d0, d2, d4}, [r4:256], r6<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vld3.16 {d0[1], d1[1], d2[1]}, [r4]<br>
+ vld3.16 {d0[1], d1[1], d2[1]}, [r4:16]<br>
+ vld3.16 {d0[1], d1[1], d2[1]}, [r4:32]<br>
+ vld3.16 {d0[1], d1[1], d2[1]}, [r4:64]<br>
+ vld3.16 {d0[1], d1[1], d2[1]}, [r4:128]<br>
+ vld3.16 {d0[1], d1[1], d2[1]}, [r4:256]<br>
+<br>
+@ CHECK: vld3.16 {d0[1], d1[1], d2[1]}, [r4] @ encoding: [0xa4,0xf9,0x4f,0x06]<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vld3.16 {d0[1], d1[1], d2[1]}, [r4:16]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vld3.16 {d0[1], d1[1], d2[1]}, [r4:32]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vld3.16 {d0[1], d1[1], d2[1]}, [r4:64]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vld3.16 {d0[1], d1[1], d2[1]}, [r4:128]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vld3.16 {d0[1], d1[1], d2[1]}, [r4:256]<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vld3.16 {d0[1], d1[1], d2[1]}, [r4]!<br>
+ vld3.16 {d0[1], d1[1], d2[1]}, [r4:16]!<br>
+ vld3.16 {d0[1], d1[1], d2[1]}, [r4:32]!<br>
+ vld3.16 {d0[1], d1[1], d2[1]}, [r4:64]!<br>
+ vld3.16 {d0[1], d1[1], d2[1]}, [r4:128]!<br>
+ vld3.16 {d0[1], d1[1], d2[1]}, [r4:256]!<br>
+<br>
+@ CHECK: vld3.16 {d0[1], d1[1], d2[1]}, [r4]! @ encoding: [0xa4,0xf9,0x4d,0x06]<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vld3.16 {d0[1], d1[1], d2[1]}, [r4:16]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vld3.16 {d0[1], d1[1], d2[1]}, [r4:32]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vld3.16 {d0[1], d1[1], d2[1]}, [r4:64]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vld3.16 {d0[1], d1[1], d2[1]}, [r4:128]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vld3.16 {d0[1], d1[1], d2[1]}, [r4:256]!<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vld3.16 {d0[1], d1[1], d2[1]}, [r4], r6<br>
+ vld3.16 {d0[1], d1[1], d2[1]}, [r4:16], r6<br>
+ vld3.16 {d0[1], d1[1], d2[1]}, [r4:32], r6<br>
+ vld3.16 {d0[1], d1[1], d2[1]}, [r4:64], r6<br>
+ vld3.16 {d0[1], d1[1], d2[1]}, [r4:128], r6<br>
+ vld3.16 {d0[1], d1[1], d2[1]}, [r4:256], r6<br>
+<br>
+@ CHECK: vld3.16 {d0[1], d1[1], d2[1]}, [r4], r6 @ encoding: [0xa4,0xf9,0x46,0x06]<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vld3.16 {d0[1], d1[1], d2[1]}, [r4:16], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vld3.16 {d0[1], d1[1], d2[1]}, [r4:32], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vld3.16 {d0[1], d1[1], d2[1]}, [r4:64], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vld3.16 {d0[1], d1[1], d2[1]}, [r4:128], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vld3.16 {d0[1], d1[1], d2[1]}, [r4:256], r6<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vld3.16 {d0[1], d2[1], d4[1]}, [r4]<br>
+ vld3.16 {d0[1], d2[1], d4[1]}, [r4:16]<br>
+ vld3.16 {d0[1], d2[1], d4[1]}, [r4:32]<br>
+ vld3.16 {d0[1], d2[1], d4[1]}, [r4:64]<br>
+ vld3.16 {d0[1], d2[1], d4[1]}, [r4:128]<br>
+ vld3.16 {d0[1], d2[1], d4[1]}, [r4:256]<br>
+<br>
+@ CHECK: vld3.16 {d0[1], d2[1], d4[1]}, [r4] @ encoding: [0xa4,0xf9,0x6f,0x06]<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vld3.16 {d0[1], d2[1], d4[1]}, [r4:16]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vld3.16 {d0[1], d2[1], d4[1]}, [r4:32]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vld3.16 {d0[1], d2[1], d4[1]}, [r4:64]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vld3.16 {d0[1], d2[1], d4[1]}, [r4:128]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vld3.16 {d0[1], d2[1], d4[1]}, [r4:256]<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vld3.16 {d0[1], d2[1], d4[1]}, [r4]!<br>
+ vld3.16 {d0[1], d2[1], d4[1]}, [r4:16]!<br>
+ vld3.16 {d0[1], d2[1], d4[1]}, [r4:32]!<br>
+ vld3.16 {d0[1], d2[1], d4[1]}, [r4:64]!<br>
+ vld3.16 {d0[1], d2[1], d4[1]}, [r4:128]!<br>
+ vld3.16 {d0[1], d2[1], d4[1]}, [r4:256]!<br>
+<br>
+@ CHECK: vld3.16 {d0[1], d1[1], d2[1]}, [r4]! @ encoding: [0xa4,0xf9,0x6d,0x06]<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vld3.16 {d0[1], d2[1], d4[1]}, [r4:16]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vld3.16 {d0[1], d2[1], d4[1]}, [r4:32]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vld3.16 {d0[1], d2[1], d4[1]}, [r4:64]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vld3.16 {d0[1], d2[1], d4[1]}, [r4:128]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vld3.16 {d0[1], d2[1], d4[1]}, [r4:256]!<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vld3.16 {d0[1], d2[1], d4[1]}, [r4], r6<br>
+ vld3.16 {d0[1], d2[1], d4[1]}, [r4:16], r6<br>
+ vld3.16 {d0[1], d2[1], d4[1]}, [r4:32], r6<br>
+ vld3.16 {d0[1], d2[1], d4[1]}, [r4:64], r6<br>
+ vld3.16 {d0[1], d2[1], d4[1]}, [r4:128], r6<br>
+ vld3.16 {d0[1], d2[1], d4[1]}, [r4:256], r6<br>
+<br>
+@ CHECK: vld3.16 {d0[1], d2[1], d4[1]}, [r4], r6 @ encoding: [0xa4,0xf9,0x66,0x06]<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vld3.16 {d0[1], d2[1], d4[1]}, [r4:16], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vld3.16 {d0[1], d2[1], d4[1]}, [r4:32], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vld3.16 {d0[1], d2[1], d4[1]}, [r4:64], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vld3.16 {d0[1], d2[1], d4[1]}, [r4:128], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vld3.16 {d0[1], d2[1], d4[1]}, [r4:256], r6<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vld3.16 {d0[], d1[], d2[]}, [r4]<br>
+ vld3.16 {d0[], d1[], d2[]}, [r4:16]<br>
+ vld3.16 {d0[], d1[], d2[]}, [r4:32]<br>
+ vld3.16 {d0[], d1[], d2[]}, [r4:64]<br>
+ vld3.16 {d0[], d1[], d2[]}, [r4:128]<br>
+ vld3.16 {d0[], d1[], d2[]}, [r4:256]<br>
+<br>
+@ CHECK: vld3.16 {d0[], d1[], d2[]}, [r4] @ encoding: [0xa4,0xf9,0x4f,0x0e]<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vld3.16 {d0[], d1[], d2[]}, [r4:16]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vld3.16 {d0[], d1[], d2[]}, [r4:32]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vld3.16 {d0[], d1[], d2[]}, [r4:64]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vld3.16 {d0[], d1[], d2[]}, [r4:128]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vld3.16 {d0[], d1[], d2[]}, [r4:256]<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vld3.16 {d0[], d1[], d2[]}, [r4]!<br>
+ vld3.16 {d0[], d1[], d2[]}, [r4:16]!<br>
+ vld3.16 {d0[], d1[], d2[]}, [r4:32]!<br>
+ vld3.16 {d0[], d1[], d2[]}, [r4:64]!<br>
+ vld3.16 {d0[], d1[], d2[]}, [r4:128]!<br>
+ vld3.16 {d0[], d1[], d2[]}, [r4:256]!<br>
+<br>
+@ CHECK: vld3.16 {d0[], d1[], d2[]}, [r4]! @ encoding: [0xa4,0xf9,0x4d,0x0e]<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vld3.16 {d0[], d1[], d2[]}, [r4:16]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vld3.16 {d0[], d1[], d2[]}, [r4:32]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vld3.16 {d0[], d1[], d2[]}, [r4:64]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vld3.16 {d0[], d1[], d2[]}, [r4:128]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vld3.16 {d0[], d1[], d2[]}, [r4:256]!<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vld3.16 {d0[], d1[], d2[]}, [r4], r6<br>
+ vld3.16 {d0[], d1[], d2[]}, [r4:16], r6<br>
+ vld3.16 {d0[], d1[], d2[]}, [r4:32], r6<br>
+ vld3.16 {d0[], d1[], d2[]}, [r4:64], r6<br>
+ vld3.16 {d0[], d1[], d2[]}, [r4:128], r6<br>
+ vld3.16 {d0[], d1[], d2[]}, [r4:256], r6<br>
+<br>
+@ CHECK: vld3.16 {d0[], d1[], d2[]}, [r4], r6 @ encoding: [0xa4,0xf9,0x46,0x0e]<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vld3.16 {d0[], d1[], d2[]}, [r4:16], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vld3.16 {d0[], d1[], d2[]}, [r4:32], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vld3.16 {d0[], d1[], d2[]}, [r4:64], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vld3.16 {d0[], d1[], d2[]}, [r4:128], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vld3.16 {d0[], d1[], d2[]}, [r4:256], r6<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vld3.16 {d0[], d2[], d4[]}, [r4]<br>
+ vld3.16 {d0[], d2[], d4[]}, [r4:16]<br>
+ vld3.16 {d0[], d2[], d4[]}, [r4:32]<br>
+ vld3.16 {d0[], d2[], d4[]}, [r4:64]<br>
+ vld3.16 {d0[], d2[], d4[]}, [r4:128]<br>
+ vld3.16 {d0[], d2[], d4[]}, [r4:256]<br>
+<br>
+@ CHECK: vld3.16 {d0[], d2[], d4[]}, [r4] @ encoding: [0xa4,0xf9,0x6f,0x0e]<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vld3.16 {d0[], d2[], d4[]}, [r4:16]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vld3.16 {d0[], d2[], d4[]}, [r4:32]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vld3.16 {d0[], d2[], d4[]}, [r4:64]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vld3.16 {d0[], d2[], d4[]}, [r4:128]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vld3.16 {d0[], d2[], d4[]}, [r4:256]<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vld3.16 {d0[], d2[], d4[]}, [r4]!<br>
+ vld3.16 {d0[], d2[], d4[]}, [r4:16]!<br>
+ vld3.16 {d0[], d2[], d4[]}, [r4:32]!<br>
+ vld3.16 {d0[], d2[], d4[]}, [r4:64]!<br>
+ vld3.16 {d0[], d2[], d4[]}, [r4:128]!<br>
+ vld3.16 {d0[], d2[], d4[]}, [r4:256]!<br>
+<br>
+@ CHECK: vld3.16 {d0[], d2[], d4[]}, [r4]! @ encoding: [0xa4,0xf9,0x6d,0x0e]<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vld3.16 {d0[], d2[], d4[]}, [r4:16]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vld3.16 {d0[], d2[], d4[]}, [r4:32]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vld3.16 {d0[], d2[], d4[]}, [r4:64]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vld3.16 {d0[], d2[], d4[]}, [r4:128]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vld3.16 {d0[], d2[], d4[]}, [r4:256]!<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vld3.16 {d0[], d2[], d4[]}, [r4], r6<br>
+ vld3.16 {d0[], d2[], d4[]}, [r4:16], r6<br>
+ vld3.16 {d0[], d2[], d4[]}, [r4:32], r6<br>
+ vld3.16 {d0[], d2[], d4[]}, [r4:64], r6<br>
+ vld3.16 {d0[], d2[], d4[]}, [r4:128], r6<br>
+ vld3.16 {d0[], d2[], d4[]}, [r4:256], r6<br>
+<br>
+@ CHECK: vld3.16 {d0[], d2[], d4[]}, [r4], r6 @ encoding: [0xa4,0xf9,0x66,0x0e]<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vld3.16 {d0[], d2[], d4[]}, [r4:16], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vld3.16 {d0[], d2[], d4[]}, [r4:32], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vld3.16 {d0[], d2[], d4[]}, [r4:64], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vld3.16 {d0[], d2[], d4[]}, [r4:128], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vld3.16 {d0[], d2[], d4[]}, [r4:256], r6<br>
+<br>
+ vld3.32 {d0, d1, d2}, [r4]<br>
+ vld3.32 {d0, d1, d2}, [r4:16]<br>
+ vld3.32 {d0, d1, d2}, [r4:32]<br>
+ vld3.32 {d0, d1, d2}, [r4:64]<br>
+ vld3.32 {d0, d1, d2}, [r4:128]<br>
+ vld3.32 {d0, d1, d2}, [r4:256]<br>
+<br>
+@ CHECK: vld3.32 {d0, d1, d2}, [r4] @ encoding: [0x24,0xf9,0x8f,0x04]<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vld3.32 {d0, d1, d2}, [r4:16]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vld3.32 {d0, d1, d2}, [r4:32]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vld3.32 {d0, d1, d2}, [r4:64] @ encoding: [0x24,0xf9,0x9f,0x04]<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vld3.32 {d0, d1, d2}, [r4:128]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vld3.32 {d0, d1, d2}, [r4:256]<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vld3.32 {d0, d1, d2}, [r4]!<br>
+ vld3.32 {d0, d1, d2}, [r4:16]!<br>
+ vld3.32 {d0, d1, d2}, [r4:32]!<br>
+ vld3.32 {d0, d1, d2}, [r4:64]!<br>
+ vld3.32 {d0, d1, d2}, [r4:128]!<br>
+ vld3.32 {d0, d1, d2}, [r4:256]!<br>
+<br>
+@ CHECK: vld3.32 {d0, d1, d2}, [r4]! @ encoding: [0x24,0xf9,0x8d,0x04]<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vld3.32 {d0, d1, d2}, [r4:16]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vld3.32 {d0, d1, d2}, [r4:32]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vld3.32 {d0, d1, d2}, [r4:64]! @ encoding: [0x24,0xf9,0x9d,0x04]<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vld3.32 {d0, d1, d2}, [r4:128]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vld3.32 {d0, d1, d2}, [r4:256]!<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vld3.32 {d0, d1, d2}, [r4], r6<br>
+ vld3.32 {d0, d1, d2}, [r4:16], r6<br>
+ vld3.32 {d0, d1, d2}, [r4:32], r6<br>
+ vld3.32 {d0, d1, d2}, [r4:64], r6<br>
+ vld3.32 {d0, d1, d2}, [r4:128], r6<br>
+ vld3.32 {d0, d1, d2}, [r4:256], r6<br>
+<br>
+@ CHECK: vld3.32 {d0, d1, d2}, [r4], r6 @ encoding: [0x24,0xf9,0x86,0x04]<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vld3.32 {d0, d1, d2}, [r4:16], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vld3.32 {d0, d1, d2}, [r4:32], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vld3.32 {d0, d1, d2}, [r4:64], r6 @ encoding: [0x24,0xf9,0x96,0x04]<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vld3.32 {d0, d1, d2}, [r4:128], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vld3.32 {d0, d1, d2}, [r4:256], r6<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vld3.32 {d0, d2, d4}, [r4]<br>
+ vld3.32 {d0, d2, d4}, [r4:16]<br>
+ vld3.32 {d0, d2, d4}, [r4:32]<br>
+ vld3.32 {d0, d2, d4}, [r4:64]<br>
+ vld3.32 {d0, d2, d4}, [r4:128]<br>
+ vld3.32 {d0, d2, d4}, [r4:256]<br>
+<br>
+@ CHECK: vld3.32 {d0, d2, d4}, [r4] @ encoding: [0x24,0xf9,0x8f,0x05]<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vld3.32 {d0, d2, d4}, [r4:16]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vld3.32 {d0, d2, d4}, [r4:32]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vld3.32 {d0, d2, d4}, [r4:64] @ encoding: [0x24,0xf9,0x9f,0x05]<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vld3.32 {d0, d2, d4}, [r4:128]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vld3.32 {d0, d2, d4}, [r4:256]<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vld3.32 {d0, d2, d4}, [r4]!<br>
+ vld3.32 {d0, d2, d4}, [r4:16]!<br>
+ vld3.32 {d0, d2, d4}, [r4:32]!<br>
+ vld3.32 {d0, d2, d4}, [r4:64]!<br>
+ vld3.32 {d0, d2, d4}, [r4:128]!<br>
+ vld3.32 {d0, d2, d4}, [r4:256]!<br>
+<br>
+@ CHECK: vld3.32 {d0, d2, d4}, [r4]! @ encoding: [0x24,0xf9,0x8d,0x05]<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vld3.32 {d0, d2, d4}, [r4:16]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vld3.32 {d0, d2, d4}, [r4:32]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vld3.32 {d0, d2, d4}, [r4:64]! @ encoding: [0x24,0xf9,0x9d,0x05]<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vld3.32 {d0, d2, d4}, [r4:128]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vld3.32 {d0, d2, d4}, [r4:256]!<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vld3.32 {d0, d2, d4}, [r4], r6<br>
+ vld3.32 {d0, d2, d4}, [r4:16], r6<br>
+ vld3.32 {d0, d2, d4}, [r4:32], r6<br>
+ vld3.32 {d0, d2, d4}, [r4:64], r6<br>
+ vld3.32 {d0, d2, d4}, [r4:128], r6<br>
+ vld3.32 {d0, d2, d4}, [r4:256], r6<br>
+<br>
+@ CHECK: vld3.32 {d0, d2, d4}, [r4], r6 @ encoding: [0x24,0xf9,0x86,0x05]<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vld3.32 {d0, d2, d4}, [r4:16], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vld3.32 {d0, d2, d4}, [r4:32], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vld3.32 {d0, d2, d4}, [r4:64], r6 @ encoding: [0x24,0xf9,0x96,0x05]<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vld3.32 {d0, d2, d4}, [r4:128], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vld3.32 {d0, d2, d4}, [r4:256], r6<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vld3.32 {d0[1], d1[1], d2[1]}, [r4]<br>
+ vld3.32 {d0[1], d1[1], d2[1]}, [r4:16]<br>
+ vld3.32 {d0[1], d1[1], d2[1]}, [r4:32]<br>
+ vld3.32 {d0[1], d1[1], d2[1]}, [r4:64]<br>
+ vld3.32 {d0[1], d1[1], d2[1]}, [r4:128]<br>
+ vld3.32 {d0[1], d1[1], d2[1]}, [r4:256]<br>
+<br>
+@ CHECK: vld3.32 {d0[1], d1[1], d2[1]}, [r4] @ encoding: [0xa4,0xf9,0x8f,0x0a]<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vld3.32 {d0[1], d1[1], d2[1]}, [r4:16]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vld3.32 {d0[1], d1[1], d2[1]}, [r4:32]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vld3.32 {d0[1], d1[1], d2[1]}, [r4:64]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vld3.32 {d0[1], d1[1], d2[1]}, [r4:128]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vld3.32 {d0[1], d1[1], d2[1]}, [r4:256]<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vld3.32 {d0[1], d1[1], d2[1]}, [r4]!<br>
+ vld3.32 {d0[1], d1[1], d2[1]}, [r4:16]!<br>
+ vld3.32 {d0[1], d1[1], d2[1]}, [r4:32]!<br>
+ vld3.32 {d0[1], d1[1], d2[1]}, [r4:64]!<br>
+ vld3.32 {d0[1], d1[1], d2[1]}, [r4:128]!<br>
+ vld3.32 {d0[1], d1[1], d2[1]}, [r4:256]!<br>
+<br>
+@ CHECK: vld3.32 {d0[1], d1[1], d2[1]}, [r4]! @ encoding: [0xa4,0xf9,0x8d,0x0a]<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vld3.32 {d0[1], d1[1], d2[1]}, [r4:16]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vld3.32 {d0[1], d1[1], d2[1]}, [r4:32]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vld3.32 {d0[1], d1[1], d2[1]}, [r4:64]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vld3.32 {d0[1], d1[1], d2[1]}, [r4:128]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vld3.32 {d0[1], d1[1], d2[1]}, [r4:256]!<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vld3.32 {d0[1], d1[1], d2[1]}, [r4], r6<br>
+ vld3.32 {d0[1], d1[1], d2[1]}, [r4:16], r6<br>
+ vld3.32 {d0[1], d1[1], d2[1]}, [r4:32], r6<br>
+ vld3.32 {d0[1], d1[1], d2[1]}, [r4:64], r6<br>
+ vld3.32 {d0[1], d1[1], d2[1]}, [r4:128], r6<br>
+ vld3.32 {d0[1], d1[1], d2[1]}, [r4:256], r6<br>
+<br>
+@ CHECK: vld3.32 {d0[1], d1[1], d2[1]}, [r4], r6 @ encoding: [0xa4,0xf9,0x86,0x0a]<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vld3.32 {d0[1], d1[1], d2[1]}, [r4:16], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vld3.32 {d0[1], d1[1], d2[1]}, [r4:32], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vld3.32 {d0[1], d1[1], d2[1]}, [r4:64], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vld3.32 {d0[1], d1[1], d2[1]}, [r4:128], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vld3.32 {d0[1], d1[1], d2[1]}, [r4:256], r6<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vld3.32 {d0[1], d2[1], d4[1]}, [r4]<br>
+ vld3.32 {d0[1], d2[1], d4[1]}, [r4:16]<br>
+ vld3.32 {d0[1], d2[1], d4[1]}, [r4:32]<br>
+ vld3.32 {d0[1], d2[1], d4[1]}, [r4:64]<br>
+ vld3.32 {d0[1], d2[1], d4[1]}, [r4:128]<br>
+ vld3.32 {d0[1], d2[1], d4[1]}, [r4:256]<br>
+<br>
+@ CHECK: vld3.32 {d0[1], d2[1], d4[1]}, [r4] @ encoding: [0xa4,0xf9,0xcf,0x0a]<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vld3.32 {d0[1], d2[1], d4[1]}, [r4:16]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vld3.32 {d0[1], d2[1], d4[1]}, [r4:32]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vld3.32 {d0[1], d2[1], d4[1]}, [r4:64]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vld3.32 {d0[1], d2[1], d4[1]}, [r4:128]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vld3.32 {d0[1], d2[1], d4[1]}, [r4:256]<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vld3.32 {d0[1], d2[1], d4[1]}, [r4]!<br>
+ vld3.32 {d0[1], d2[1], d4[1]}, [r4:16]!<br>
+ vld3.32 {d0[1], d2[1], d4[1]}, [r4:32]!<br>
+ vld3.32 {d0[1], d2[1], d4[1]}, [r4:64]!<br>
+ vld3.32 {d0[1], d2[1], d4[1]}, [r4:128]!<br>
+ vld3.32 {d0[1], d2[1], d4[1]}, [r4:256]!<br>
+<br>
+@ CHECK: vld3.32 {d0[1], d2[1], d4[1]}, [r4]! @ encoding: [0xa4,0xf9,0xcd,0x0a]<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vld3.32 {d0[1], d2[1], d4[1]}, [r4:16]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vld3.32 {d0[1], d2[1], d4[1]}, [r4:32]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vld3.32 {d0[1], d2[1], d4[1]}, [r4:64]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vld3.32 {d0[1], d2[1], d4[1]}, [r4:128]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vld3.32 {d0[1], d2[1], d4[1]}, [r4:256]!<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vld3.32 {d0[1], d2[1], d4[1]}, [r4], r6<br>
+ vld3.32 {d0[1], d2[1], d4[1]}, [r4:16], r6<br>
+ vld3.32 {d0[1], d2[1], d4[1]}, [r4:32], r6<br>
+ vld3.32 {d0[1], d2[1], d4[1]}, [r4:64], r6<br>
+ vld3.32 {d0[1], d2[1], d4[1]}, [r4:128], r6<br>
+ vld3.32 {d0[1], d2[1], d4[1]}, [r4:256], r6<br>
+<br>
+@ CHECK: vld3.32 {d0[1], d2[1], d4[1]}, [r4], r6 @ encoding: [0xa4,0xf9,0xc6,0x0a]<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vld3.32 {d0[1], d2[1], d4[1]}, [r4:16], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vld3.32 {d0[1], d2[1], d4[1]}, [r4:32], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vld3.32 {d0[1], d2[1], d4[1]}, [r4:64], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vld3.32 {d0[1], d2[1], d4[1]}, [r4:128], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vld3.32 {d0[1], d2[1], d4[1]}, [r4:256], r6<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vld3.32 {d0[], d1[], d2[]}, [r4]<br>
+ vld3.32 {d0[], d1[], d2[]}, [r4:16]<br>
+ vld3.32 {d0[], d1[], d2[]}, [r4:32]<br>
+ vld3.32 {d0[], d1[], d2[]}, [r4:64]<br>
+ vld3.32 {d0[], d1[], d2[]}, [r4:128]<br>
+ vld3.32 {d0[], d1[], d2[]}, [r4:256]<br>
+<br>
+@ CHECK: vld3.32 {d0[], d1[], d2[]}, [r4] @ encoding: [0xa4,0xf9,0x8f,0x0e]<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vld3.32 {d0[], d1[], d2[]}, [r4:16]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vld3.32 {d0[], d1[], d2[]}, [r4:32]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vld3.32 {d0[], d1[], d2[]}, [r4:64]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vld3.32 {d0[], d1[], d2[]}, [r4:128]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vld3.32 {d0[], d1[], d2[]}, [r4:256]<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vld3.32 {d0[], d1[], d2[]}, [r4]!<br>
+ vld3.32 {d0[], d1[], d2[]}, [r4:16]!<br>
+ vld3.32 {d0[], d1[], d2[]}, [r4:32]!<br>
+ vld3.32 {d0[], d1[], d2[]}, [r4:64]!<br>
+ vld3.32 {d0[], d1[], d2[]}, [r4:128]!<br>
+ vld3.32 {d0[], d1[], d2[]}, [r4:256]!<br>
+<br>
+@ CHECK: vld3.32 {d0[], d1[], d2[]}, [r4]! @ encoding: [0xa4,0xf9,0x8d,0x0e]<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vld3.32 {d0[], d1[], d2[]}, [r4:16]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vld3.32 {d0[], d1[], d2[]}, [r4:32]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vld3.32 {d0[], d1[], d2[]}, [r4:64]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vld3.32 {d0[], d1[], d2[]}, [r4:128]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vld3.32 {d0[], d1[], d2[]}, [r4:256]!<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vld3.32 {d0[], d1[], d2[]}, [r4], r6<br>
+ vld3.32 {d0[], d1[], d2[]}, [r4:16], r6<br>
+ vld3.32 {d0[], d1[], d2[]}, [r4:32], r6<br>
+ vld3.32 {d0[], d1[], d2[]}, [r4:64], r6<br>
+ vld3.32 {d0[], d1[], d2[]}, [r4:128], r6<br>
+ vld3.32 {d0[], d1[], d2[]}, [r4:256], r6<br>
+<br>
+@ CHECK: vld3.32 {d0[], d1[], d2[]}, [r4], r6 @ encoding: [0xa4,0xf9,0x86,0x0e]<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vld3.32 {d0[], d1[], d2[]}, [r4:16], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vld3.32 {d0[], d1[], d2[]}, [r4:32], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vld3.32 {d0[], d1[], d2[]}, [r4:64], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vld3.32 {d0[], d1[], d2[]}, [r4:128], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vld3.32 {d0[], d1[], d2[]}, [r4:256], r6<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vld3.32 {d0[], d2[], d4[]}, [r4]<br>
+ vld3.32 {d0[], d2[], d4[]}, [r4:16]<br>
+ vld3.32 {d0[], d2[], d4[]}, [r4:32]<br>
+ vld3.32 {d0[], d2[], d4[]}, [r4:64]<br>
+ vld3.32 {d0[], d2[], d4[]}, [r4:128]<br>
+ vld3.32 {d0[], d2[], d4[]}, [r4:256]<br>
+<br>
+@ CHECK: vld3.32 {d0[], d2[], d4[]}, [r4] @ encoding: [0xa4,0xf9,0xaf,0x0e]<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vld3.32 {d0[], d2[], d4[]}, [r4:16]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vld3.32 {d0[], d2[], d4[]}, [r4:32]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vld3.32 {d0[], d2[], d4[]}, [r4:64]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vld3.32 {d0[], d2[], d4[]}, [r4:128]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vld3.32 {d0[], d2[], d4[]}, [r4:256]<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vld3.32 {d0[], d2[], d4[]}, [r4]!<br>
+ vld3.32 {d0[], d2[], d4[]}, [r4:16]!<br>
+ vld3.32 {d0[], d2[], d4[]}, [r4:32]!<br>
+ vld3.32 {d0[], d2[], d4[]}, [r4:64]!<br>
+ vld3.32 {d0[], d2[], d4[]}, [r4:128]!<br>
+ vld3.32 {d0[], d2[], d4[]}, [r4:256]!<br>
+<br>
+@ CHECK: vld3.32 {d0[], d2[], d4[]}, [r4]! @ encoding: [0xa4,0xf9,0xad,0x0e]<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vld3.32 {d0[], d2[], d4[]}, [r4:16]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vld3.32 {d0[], d2[], d4[]}, [r4:32]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vld3.32 {d0[], d2[], d4[]}, [r4:64]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vld3.32 {d0[], d2[], d4[]}, [r4:128]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vld3.32 {d0[], d2[], d4[]}, [r4:256]!<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vld3.32 {d0[], d2[], d4[]}, [r4], r6<br>
+ vld3.32 {d0[], d2[], d4[]}, [r4:16], r6<br>
+ vld3.32 {d0[], d2[], d4[]}, [r4:32], r6<br>
+ vld3.32 {d0[], d2[], d4[]}, [r4:64], r6<br>
+ vld3.32 {d0[], d2[], d4[]}, [r4:128], r6<br>
+ vld3.32 {d0[], d2[], d4[]}, [r4:256], r6<br>
+<br>
+@ CHECK: vld3.32 {d0[], d2[], d4[]}, [r4], r6 @ encoding: [0xa4,0xf9,0xa6,0x0e]<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vld3.32 {d0[], d2[], d4[]}, [r4:16], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vld3.32 {d0[], d2[], d4[]}, [r4:32], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vld3.32 {d0[], d2[], d4[]}, [r4:64], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vld3.32 {d0[], d2[], d4[]}, [r4:128], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vld3.32 {d0[], d2[], d4[]}, [r4:256], r6<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vld4.8 {d0, d1, d2, d3}, [r4]<br>
+ vld4.8 {d0, d1, d2, d3}, [r4:16]<br>
+ vld4.8 {d0, d1, d2, d3}, [r4:32]<br>
+ vld4.8 {d0, d1, d2, d3}, [r4:64]<br>
+ vld4.8 {d0, d1, d2, d3}, [r4:128]<br>
+ vld4.8 {d0, d1, d2, d3}, [r4:256]<br>
+<br>
+@ CHECK: vld4.8 {d0, d1, d2, d3}, [r4] @ encoding: [0x24,0xf9,0x0f,0x00]<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted<br>
+@ CHECK-ERRORS: vld4.8 {d0, d1, d2, d3}, [r4:16]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted<br>
+@ CHECK-ERRORS: vld4.8 {d0, d1, d2, d3}, [r4:32]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vld4.8 {d0, d1, d2, d3}, [r4:64] @ encoding: [0x24,0xf9,0x1f,0x00]<br>
+@ CHECK: vld4.8 {d0, d1, d2, d3}, [r4:128] @ encoding: [0x24,0xf9,0x2f,0x00]<br>
+@ CHECK: vld4.8 {d0, d1, d2, d3}, [r4:256] @ encoding: [0x24,0xf9,0x3f,0x00]<br>
+<br>
+ vld4.8 {d0, d1, d2, d3}, [r4]!<br>
+ vld4.8 {d0, d1, d2, d3}, [r4:16]!<br>
+ vld4.8 {d0, d1, d2, d3}, [r4:32]!<br>
+ vld4.8 {d0, d1, d2, d3}, [r4:64]!<br>
+ vld4.8 {d0, d1, d2, d3}, [r4:128]!<br>
+ vld4.8 {d0, d1, d2, d3}, [r4:256]!<br>
+<br>
+@ CHECK: vld4.8 {d0, d1, d2, d3}, [r4]! @ encoding: [0x24,0xf9,0x0d,0x00]<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted<br>
+@ CHECK-ERRORS: vld4.8 {d0, d1, d2, d3}, [r4:16]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted<br>
+@ CHECK-ERRORS: vld4.8 {d0, d1, d2, d3}, [r4:32]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vld4.8 {d0, d1, d2, d3}, [r4:64]! @ encoding: [0x24,0xf9,0x1d,0x00]<br>
+@ CHECK: vld4.8 {d0, d1, d2, d3}, [r4:128]! @ encoding: [0x24,0xf9,0x2d,0x00]<br>
+@ CHECK: vld4.8 {d0, d1, d2, d3}, [r4:256]! @ encoding: [0x24,0xf9,0x3d,0x00]<br>
+<br>
+ vld4.8 {d0, d1, d2, d3}, [r4], r6<br>
+ vld4.8 {d0, d1, d2, d3}, [r4:16], r6<br>
+ vld4.8 {d0, d1, d2, d3}, [r4:32], r6<br>
+ vld4.8 {d0, d1, d2, d3}, [r4:64], r6<br>
+ vld4.8 {d0, d1, d2, d3}, [r4:128], r6<br>
+ vld4.8 {d0, d1, d2, d3}, [r4:256], r6<br>
+<br>
+@ CHECK: vld4.8 {d0, d1, d2, d3}, [r4], r6 @ encoding: [0x24,0xf9,0x06,0x00]<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted<br>
+@ CHECK-ERRORS: vld4.8 {d0, d1, d2, d3}, [r4:16], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted<br>
+@ CHECK-ERRORS: vld4.8 {d0, d1, d2, d3}, [r4:32], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vld4.8 {d0, d1, d2, d3}, [r4:64], r6 @ encoding: [0x24,0xf9,0x16,0x00]<br>
+@ CHECK: vld4.8 {d0, d1, d2, d3}, [r4:128], r6 @ encoding: [0x24,0xf9,0x26,0x00]<br>
+@ CHECK: vld4.8 {d0, d1, d2, d3}, [r4:256], r6 @ encoding: [0x24,0xf9,0x36,0x00]<br>
+<br>
+ vld4.8 {d0, d2, d4, d6}, [r4]<br>
+ vld4.8 {d0, d2, d4, d6}, [r4:16]<br>
+ vld4.8 {d0, d2, d4, d6}, [r4:32]<br>
+ vld4.8 {d0, d2, d4, d6}, [r4:64]<br>
+ vld4.8 {d0, d2, d4, d6}, [r4:128]<br>
+ vld4.8 {d0, d2, d4, d6}, [r4:256]<br>
+<br>
+@ CHECK: vld4.8 {d0, d2, d4, d6}, [r4] @ encoding: [0x24,0xf9,0x0f,0x01]<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted<br>
+@ CHECK-ERRORS: vld4.8 {d0, d2, d4, d6}, [r4:16]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted<br>
+@ CHECK-ERRORS: vld4.8 {d0, d2, d4, d6}, [r4:32]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vld4.8 {d0, d2, d4, d6}, [r4:64] @ encoding: [0x24,0xf9,0x1f,0x01]<br>
+@ CHECK: vld4.8 {d0, d2, d4, d6}, [r4:128] @ encoding: [0x24,0xf9,0x2f,0x01]<br>
+@ CHECK: vld4.8 {d0, d2, d4, d6}, [r4:256] @ encoding: [0x24,0xf9,0x3f,0x01]<br>
+<br>
+ vld4.8 {d0, d2, d4, d6}, [r4]!<br>
+ vld4.8 {d0, d2, d4, d6}, [r4:16]!<br>
+ vld4.8 {d0, d2, d4, d6}, [r4:32]!<br>
+ vld4.8 {d0, d2, d4, d6}, [r4:64]!<br>
+ vld4.8 {d0, d2, d4, d6}, [r4:128]!<br>
+ vld4.8 {d0, d2, d4, d6}, [r4:256]!<br>
+<br>
+@ CHECK: vld4.8 {d0, d2, d4, d6}, [r4]! @ encoding: [0x24,0xf9,0x0d,0x01]<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted<br>
+@ CHECK-ERRORS: vld4.8 {d0, d2, d4, d6}, [r4:16]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted<br>
+@ CHECK-ERRORS: vld4.8 {d0, d2, d4, d6}, [r4:32]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vld4.8 {d0, d2, d4, d6}, [r4:64]! @ encoding: [0x24,0xf9,0x1d,0x01]<br>
+@ CHECK: vld4.8 {d0, d2, d4, d6}, [r4:128]! @ encoding: [0x24,0xf9,0x2d,0x01]<br>
+@ CHECK: vld4.8 {d0, d2, d4, d6}, [r4:256]! @ encoding: [0x24,0xf9,0x3d,0x01]<br>
+<br>
+ vld4.8 {d0, d2, d4, d6}, [r4], r6<br>
+ vld4.8 {d0, d2, d4, d6}, [r4:16], r6<br>
+ vld4.8 {d0, d2, d4, d6}, [r4:32], r6<br>
+ vld4.8 {d0, d2, d4, d6}, [r4:64], r6<br>
+ vld4.8 {d0, d2, d4, d6}, [r4:128], r6<br>
+ vld4.8 {d0, d2, d4, d6}, [r4:256], r6<br>
+<br>
+@ CHECK: vld4.8 {d0, d2, d4, d6}, [r4], r6 @ encoding: [0x24,0xf9,0x06,0x01]<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted<br>
+@ CHECK-ERRORS: vld4.8 {d0, d2, d4, d6}, [r4:16], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted<br>
+@ CHECK-ERRORS: vld4.8 {d0, d2, d4, d6}, [r4:32], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vld4.8 {d0, d2, d4, d6}, [r4:64], r6 @ encoding: [0x24,0xf9,0x16,0x01]<br>
+@ CHECK: vld4.8 {d0, d2, d4, d6}, [r4:128], r6 @ encoding: [0x24,0xf9,0x26,0x01]<br>
+@ CHECK: vld4.8 {d0, d2, d4, d6}, [r4:256], r6 @ encoding: [0x24,0xf9,0x36,0x01]<br>
+<br>
+ vld4.8 {d0[1], d1[1], d2[1], d3[1]}, [r4]<br>
+ vld4.8 {d0[1], d1[1], d2[1], d3[1]}, [r4:16]<br>
+ vld4.8 {d0[1], d1[1], d2[1], d3[1]}, [r4:32]<br>
+ vld4.8 {d0[1], d1[1], d2[1], d3[1]}, [r4:64]<br>
+ vld4.8 {d0[1], d1[1], d2[1], d3[1]}, [r4:128]<br>
+ vld4.8 {d0[1], d1[1], d2[1], d3[1]}, [r4:256]<br>
+<br>
+@ CHECK: vld4.8 {d0[1], d1[1], d2[1], d3[1]}, [r4] @ encoding: [0xa4,0xf9,0x2f,0x03]<br>
+@ CHECK-ERRORS: error: alignment must be 32 or omitted<br>
+@ CHECK-ERRORS: vld4.8 {d0[1], d1[1], d2[1], d3[1]}, [r4:16]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vld4.8 {d0[1], d1[1], d2[1], d3[1]}, [r4:32] @ encoding: [0xa4,0xf9,0x3f,0x03]<br>
+@ CHECK-ERRORS: error: alignment must be 32 or omitted<br>
+@ CHECK-ERRORS: vld4.8 {d0[1], d1[1], d2[1], d3[1]}, [r4:64]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 32 or omitted<br>
+@ CHECK-ERRORS: vld4.8 {d0[1], d1[1], d2[1], d3[1]}, [r4:128]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 32 or omitted<br>
+@ CHECK-ERRORS: vld4.8 {d0[1], d1[1], d2[1], d3[1]}, [r4:256]<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vld4.8 {d0[1], d1[1], d2[1], d3[1]}, [r4]!<br>
+ vld4.8 {d0[1], d1[1], d2[1], d3[1]}, [r4:16]!<br>
+ vld4.8 {d0[1], d1[1], d2[1], d3[1]}, [r4:32]!<br>
+ vld4.8 {d0[1], d1[1], d2[1], d3[1]}, [r4:64]!<br>
+ vld4.8 {d0[1], d1[1], d2[1], d3[1]}, [r4:128]!<br>
+ vld4.8 {d0[1], d1[1], d2[1], d3[1]}, [r4:256]!<br>
+<br>
+@ CHECK: vld4.8 {d0[1], d1[1], d2[1], d3[1]}, [r4]! @ encoding: [0xa4,0xf9,0x2d,0x03]<br>
+@ CHECK-ERRORS: error: alignment must be 32 or omitted<br>
+@ CHECK-ERRORS: vld4.8 {d0[1], d1[1], d2[1], d3[1]}, [r4:16]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vld4.8 {d0[1], d1[1], d2[1], d3[1]}, [r4:32]! @ encoding: [0xa4,0xf9,0x3d,0x03]<br>
+@ CHECK-ERRORS: error: alignment must be 32 or omitted<br>
+@ CHECK-ERRORS: vld4.8 {d0[1], d1[1], d2[1], d3[1]}, [r4:64]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 32 or omitted<br>
+@ CHECK-ERRORS: vld4.8 {d0[1], d1[1], d2[1], d3[1]}, [r4:128]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 32 or omitted<br>
+@ CHECK-ERRORS: vld4.8 {d0[1], d1[1], d2[1], d3[1]}, [r4:256]!<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vld4.8 {d0[1], d1[1], d2[1], d3[1]}, [r4], r6<br>
+ vld4.8 {d0[1], d1[1], d2[1], d3[1]}, [r4:16], r6<br>
+ vld4.8 {d0[1], d1[1], d2[1], d3[1]}, [r4:32], r6<br>
+ vld4.8 {d0[1], d1[1], d2[1], d3[1]}, [r4:64], r6<br>
+ vld4.8 {d0[1], d1[1], d2[1], d3[1]}, [r4:128], r6<br>
+ vld4.8 {d0[1], d1[1], d2[1], d3[1]}, [r4:256], r6<br>
+<br>
+@ CHECK: vld4.8 {d0[1], d1[1], d2[1], d3[1]}, [r4], r6 @ encoding: [0xa4,0xf9,0x26,0x03]<br>
+@ CHECK-ERRORS: error: alignment must be 32 or omitted<br>
+@ CHECK-ERRORS: vld4.8 {d0[1], d1[1], d2[1], d3[1]}, [r4:16], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vld4.8 {d0[1], d1[1], d2[1], d3[1]}, [r4:32], r6 @ encoding: [0xa4,0xf9,0x36,0x03]<br>
+@ CHECK-ERRORS: error: alignment must be 32 or omitted<br>
+@ CHECK-ERRORS: vld4.8 {d0[1], d1[1], d2[1], d3[1]}, [r4:64], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 32 or omitted<br>
+@ CHECK-ERRORS: vld4.8 {d0[1], d1[1], d2[1], d3[1]}, [r4:128], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 32 or omitted<br>
+@ CHECK-ERRORS: vld4.8 {d0[1], d1[1], d2[1], d3[1]}, [r4:256], r6<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vld4.8 {d0[], d1[], d2[], d3[]}, [r4]<br>
+ vld4.8 {d0[], d1[], d2[], d3[]}, [r4:16]<br>
+ vld4.8 {d0[], d1[], d2[], d3[]}, [r4:32]<br>
+ vld4.8 {d0[], d1[], d2[], d3[]}, [r4:64]<br>
+ vld4.8 {d0[], d1[], d2[], d3[]}, [r4:128]<br>
+ vld4.8 {d0[], d1[], d2[], d3[]}, [r4:256]<br>
+<br>
+@ CHECK: vld4.8 {d0[], d1[], d2[], d3[]}, [r4] @ encoding: [0xa4,0xf9,0x0f,0x0f]<br>
+@ CHECK-ERRORS: error: alignment must be 32 or omitted<br>
+@ CHECK-ERRORS: vld4.8 {d0[], d1[], d2[], d3[]}, [r4:16]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vld4.8 {d0[], d1[], d2[], d3[]}, [r4:32] @ encoding: [0xa4,0xf9,0x1f,0x0f]<br>
+@ CHECK-ERRORS: error: alignment must be 32 or omitted<br>
+@ CHECK-ERRORS: vld4.8 {d0[], d1[], d2[], d3[]}, [r4:64]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 32 or omitted<br>
+@ CHECK-ERRORS: vld4.8 {d0[], d1[], d2[], d3[]}, [r4:128]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 32 or omitted<br>
+@ CHECK-ERRORS: vld4.8 {d0[], d1[], d2[], d3[]}, [r4:256]<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vld4.8 {d0[], d1[], d2[], d3[]}, [r4]!<br>
+ vld4.8 {d0[], d1[], d2[], d3[]}, [r4:16]!<br>
+ vld4.8 {d0[], d1[], d2[], d3[]}, [r4:32]!<br>
+ vld4.8 {d0[], d1[], d2[], d3[]}, [r4:64]!<br>
+ vld4.8 {d0[], d1[], d2[], d3[]}, [r4:128]!<br>
+ vld4.8 {d0[], d1[], d2[], d3[]}, [r4:256]!<br>
+<br>
+@ CHECK: vld4.8 {d0[], d1[], d2[], d3[]}, [r4]! @ encoding: [0xa4,0xf9,0x0d,0x0f]<br>
+@ CHECK-ERRORS: error: alignment must be 32 or omitted<br>
+@ CHECK-ERRORS: vld4.8 {d0[], d1[], d2[], d3[]}, [r4:16]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vld4.8 {d0[], d1[], d2[], d3[]}, [r4:32]! @ encoding: [0xa4,0xf9,0x1d,0x0f]<br>
+@ CHECK-ERRORS: error: alignment must be 32 or omitted<br>
+@ CHECK-ERRORS: vld4.8 {d0[], d1[], d2[], d3[]}, [r4:64]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 32 or omitted<br>
+@ CHECK-ERRORS: vld4.8 {d0[], d1[], d2[], d3[]}, [r4:128]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 32 or omitted<br>
+@ CHECK-ERRORS: vld4.8 {d0[], d1[], d2[], d3[]}, [r4:256]!<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vld4.8 {d0[], d1[], d2[], d3[]}, [r4], r6<br>
+ vld4.8 {d0[], d1[], d2[], d3[]}, [r4:16], r6<br>
+ vld4.8 {d0[], d1[], d2[], d3[]}, [r4:32], r6<br>
+ vld4.8 {d0[], d1[], d2[], d3[]}, [r4:64], r6<br>
+ vld4.8 {d0[], d1[], d2[], d3[]}, [r4:128], r6<br>
+ vld4.8 {d0[], d1[], d2[], d3[]}, [r4:256], r6<br>
+<br>
+@ CHECK: vld4.8 {d0[], d1[], d2[], d3[]}, [r4], r6 @ encoding: [0xa4,0xf9,0x06,0x0f]<br>
+@ CHECK-ERRORS: error: alignment must be 32 or omitted<br>
+@ CHECK-ERRORS: vld4.8 {d0[], d1[], d2[], d3[]}, [r4:16], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vld4.8 {d0[], d1[], d2[], d3[]}, [r4:32], r6 @ encoding: [0xa4,0xf9,0x16,0x0f]<br>
+@ CHECK-ERRORS: error: alignment must be 32 or omitted<br>
+@ CHECK-ERRORS: vld4.8 {d0[], d1[], d2[], d3[]}, [r4:64], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 32 or omitted<br>
+@ CHECK-ERRORS: vld4.8 {d0[], d1[], d2[], d3[]}, [r4:128], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 32 or omitted<br>
+@ CHECK-ERRORS: vld4.8 {d0[], d1[], d2[], d3[]}, [r4:256], r6<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vld4.8 {d0[], d2[], d4[], d6[]}, [r4]<br>
+ vld4.8 {d0[], d2[], d4[], d6[]}, [r4:16]<br>
+ vld4.8 {d0[], d2[], d4[], d6[]}, [r4:32]<br>
+ vld4.8 {d0[], d2[], d4[], d6[]}, [r4:64]<br>
+ vld4.8 {d0[], d2[], d4[], d6[]}, [r4:128]<br>
+ vld4.8 {d0[], d2[], d4[], d6[]}, [r4:256]<br>
+<br>
+@ CHECK: vld4.8 {d0[], d2[], d4[], d6[]}, [r4] @ encoding: [0xa4,0xf9,0x2f,0x0f]<br>
+@ CHECK-ERRORS: error: alignment must be 32 or omitted<br>
+@ CHECK-ERRORS: vld4.8 {d0[], d2[], d4[], d6[]}, [r4:16]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vld4.8 {d0[], d2[], d4[], d6[]}, [r4:32] @ encoding: [0xa4,0xf9,0x3f,0x0f]<br>
+@ CHECK-ERRORS: error: alignment must be 32 or omitted<br>
+@ CHECK-ERRORS: vld4.8 {d0[], d2[], d4[], d6[]}, [r4:64]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 32 or omitted<br>
+@ CHECK-ERRORS: vld4.8 {d0[], d2[], d4[], d6[]}, [r4:128]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 32 or omitted<br>
+@ CHECK-ERRORS: vld4.8 {d0[], d2[], d4[], d6[]}, [r4:256]<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vld4.8 {d0[], d2[], d4[], d6[]}, [r4]!<br>
+ vld4.8 {d0[], d2[], d4[], d6[]}, [r4:16]!<br>
+ vld4.8 {d0[], d2[], d4[], d6[]}, [r4:32]!<br>
+ vld4.8 {d0[], d2[], d4[], d6[]}, [r4:64]!<br>
+ vld4.8 {d0[], d2[], d4[], d6[]}, [r4:128]!<br>
+ vld4.8 {d0[], d2[], d4[], d6[]}, [r4:256]!<br>
+<br>
+@ CHECK: vld4.8 {d0[], d1[], d2[], d3[]}, [r4]! @ encoding: [0xa4,0xf9,0x2d,0x0f]<br>
+@ CHECK-ERRORS: error: alignment must be 32 or omitted<br>
+@ CHECK-ERRORS: vld4.8 {d0[], d2[], d4[], d6[]}, [r4:16]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vld4.8 {d0[], d1[], d2[], d3[]}, [r4:32]! @ encoding: [0xa4,0xf9,0x3d,0x0f]<br>
+@ CHECK-ERRORS: error: alignment must be 32 or omitted<br>
+@ CHECK-ERRORS: vld4.8 {d0[], d2[], d4[], d6[]}, [r4:64]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 32 or omitted<br>
+@ CHECK-ERRORS: vld4.8 {d0[], d2[], d4[], d6[]}, [r4:128]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 32 or omitted<br>
+@ CHECK-ERRORS: vld4.8 {d0[], d2[], d4[], d6[]}, [r4:256]!<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vld4.8 {d0[], d2[], d4[], d6[]}, [r4], r6<br>
+ vld4.8 {d0[], d2[], d4[], d6[]}, [r4:16], r6<br>
+ vld4.8 {d0[], d2[], d4[], d6[]}, [r4:32], r6<br>
+ vld4.8 {d0[], d2[], d4[], d6[]}, [r4:64], r6<br>
+ vld4.8 {d0[], d2[], d4[], d6[]}, [r4:128], r6<br>
+ vld4.8 {d0[], d2[], d4[], d6[]}, [r4:256], r6<br>
+<br>
+@ CHECK: vld4.8 {d0[], d2[], d4[], d6[]}, [r4], r6 @ encoding: [0xa4,0xf9,0x26,0x0f]<br>
+@ CHECK-ERRORS: error: alignment must be 32 or omitted<br>
+@ CHECK-ERRORS: vld4.8 {d0[], d2[], d4[], d6[]}, [r4:16], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vld4.8 {d0[], d2[], d4[], d6[]}, [r4:32], r6 @ encoding: [0xa4,0xf9,0x36,0x0f]<br>
+@ CHECK-ERRORS: error: alignment must be 32 or omitted<br>
+@ CHECK-ERRORS: vld4.8 {d0[], d2[], d4[], d6[]}, [r4:64], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 32 or omitted<br>
+@ CHECK-ERRORS: vld4.8 {d0[], d2[], d4[], d6[]}, [r4:128], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 32 or omitted<br>
+@ CHECK-ERRORS: vld4.8 {d0[], d2[], d4[], d6[]}, [r4:256], r6<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vld4.16 {d0, d1, d2, d3}, [r4]<br>
+ vld4.16 {d0, d1, d2, d3}, [r4:16]<br>
+ vld4.16 {d0, d1, d2, d3}, [r4:32]<br>
+ vld4.16 {d0, d1, d2, d3}, [r4:64]<br>
+ vld4.16 {d0, d1, d2, d3}, [r4:128]<br>
+ vld4.16 {d0, d1, d2, d3}, [r4:256]<br>
+<br>
+@ CHECK: vld4.16 {d0, d1, d2, d3}, [r4] @ encoding: [0x24,0xf9,0x4f,0x00]<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted<br>
+@ CHECK-ERRORS: vld4.16 {d0, d1, d2, d3}, [r4:16]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted<br>
+@ CHECK-ERRORS: vld4.16 {d0, d1, d2, d3}, [r4:32]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vld4.16 {d0, d1, d2, d3}, [r4:64] @ encoding: [0x24,0xf9,0x5f,0x00]<br>
+@ CHECK: vld4.16 {d0, d1, d2, d3}, [r4:128] @ encoding: [0x24,0xf9,0x6f,0x00]<br>
+@ CHECK: vld4.16 {d0, d1, d2, d3}, [r4:256] @ encoding: [0x24,0xf9,0x7f,0x00]<br>
+<br>
+ vld4.16 {d0, d1, d2, d3}, [r4]!<br>
+ vld4.16 {d0, d1, d2, d3}, [r4:16]!<br>
+ vld4.16 {d0, d1, d2, d3}, [r4:32]!<br>
+ vld4.16 {d0, d1, d2, d3}, [r4:64]!<br>
+ vld4.16 {d0, d1, d2, d3}, [r4:128]!<br>
+ vld4.16 {d0, d1, d2, d3}, [r4:256]!<br>
+<br>
+@ CHECK: vld4.16 {d0, d1, d2, d3}, [r4]! @ encoding: [0x24,0xf9,0x4d,0x00]<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted<br>
+@ CHECK-ERRORS: vld4.16 {d0, d1, d2, d3}, [r4:16]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted<br>
+@ CHECK-ERRORS: vld4.16 {d0, d1, d2, d3}, [r4:32]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vld4.16 {d0, d1, d2, d3}, [r4:64]! @ encoding: [0x24,0xf9,0x5d,0x00]<br>
+@ CHECK: vld4.16 {d0, d1, d2, d3}, [r4:128]! @ encoding: [0x24,0xf9,0x6d,0x00]<br>
+@ CHECK: vld4.16 {d0, d1, d2, d3}, [r4:256]! @ encoding: [0x24,0xf9,0x7d,0x00]<br>
+<br>
+ vld4.16 {d0, d1, d2, d3}, [r4], r6<br>
+ vld4.16 {d0, d1, d2, d3}, [r4:16], r6<br>
+ vld4.16 {d0, d1, d2, d3}, [r4:32], r6<br>
+ vld4.16 {d0, d1, d2, d3}, [r4:64], r6<br>
+ vld4.16 {d0, d1, d2, d3}, [r4:128], r6<br>
+ vld4.16 {d0, d1, d2, d3}, [r4:256], r6<br>
+<br>
+@ CHECK: vld4.16 {d0, d1, d2, d3}, [r4], r6 @ encoding: [0x24,0xf9,0x46,0x00]<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted<br>
+@ CHECK-ERRORS: vld4.16 {d0, d1, d2, d3}, [r4:16], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted<br>
+@ CHECK-ERRORS: vld4.16 {d0, d1, d2, d3}, [r4:32], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vld4.16 {d0, d1, d2, d3}, [r4:64], r6 @ encoding: [0x24,0xf9,0x56,0x00]<br>
+@ CHECK: vld4.16 {d0, d1, d2, d3}, [r4:128], r6 @ encoding: [0x24,0xf9,0x66,0x00]<br>
+@ CHECK: vld4.16 {d0, d1, d2, d3}, [r4:256], r6 @ encoding: [0x24,0xf9,0x76,0x00]<br>
+<br>
+ vld4.16 {d0, d2, d4, d6}, [r4]<br>
+ vld4.16 {d0, d2, d4, d6}, [r4:16]<br>
+ vld4.16 {d0, d2, d4, d6}, [r4:32]<br>
+ vld4.16 {d0, d2, d4, d6}, [r4:64]<br>
+ vld4.16 {d0, d2, d4, d6}, [r4:128]<br>
+ vld4.16 {d0, d2, d4, d6}, [r4:256]<br>
+<br>
+@ CHECK: vld4.16 {d0, d2, d4, d6}, [r4] @ encoding: [0x24,0xf9,0x4f,0x01]<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted<br>
+@ CHECK-ERRORS: vld4.16 {d0, d2, d4, d6}, [r4:16]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted<br>
+@ CHECK-ERRORS: vld4.16 {d0, d2, d4, d6}, [r4:32]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vld4.16 {d0, d2, d4, d6}, [r4:64] @ encoding: [0x24,0xf9,0x5f,0x01]<br>
+@ CHECK: vld4.16 {d0, d2, d4, d6}, [r4:128] @ encoding: [0x24,0xf9,0x6f,0x01]<br>
+@ CHECK: vld4.16 {d0, d2, d4, d6}, [r4:256] @ encoding: [0x24,0xf9,0x7f,0x01]<br>
+<br>
+ vld4.16 {d0, d2, d4, d6}, [r4]!<br>
+ vld4.16 {d0, d2, d4, d6}, [r4:16]!<br>
+ vld4.16 {d0, d2, d4, d6}, [r4:32]!<br>
+ vld4.16 {d0, d2, d4, d6}, [r4:64]!<br>
+ vld4.16 {d0, d2, d4, d6}, [r4:128]!<br>
+ vld4.16 {d0, d2, d4, d6}, [r4:256]!<br>
+<br>
+@ CHECK: vld4.16 {d0, d2, d4, d6}, [r4]! @ encoding: [0x24,0xf9,0x4d,0x01]<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted<br>
+@ CHECK-ERRORS: vld4.16 {d0, d2, d4, d6}, [r4:16]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted<br>
+@ CHECK-ERRORS: vld4.16 {d0, d2, d4, d6}, [r4:32]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vld4.16 {d0, d2, d4, d6}, [r4:64]! @ encoding: [0x24,0xf9,0x5d,0x01]<br>
+@ CHECK: vld4.16 {d0, d2, d4, d6}, [r4:128]! @ encoding: [0x24,0xf9,0x6d,0x01]<br>
+@ CHECK: vld4.16 {d0, d2, d4, d6}, [r4:256]! @ encoding: [0x24,0xf9,0x7d,0x01]<br>
+<br>
+ vld4.16 {d0, d2, d4, d6}, [r4], r6<br>
+ vld4.16 {d0, d2, d4, d6}, [r4:16], r6<br>
+ vld4.16 {d0, d2, d4, d6}, [r4:32], r6<br>
+ vld4.16 {d0, d2, d4, d6}, [r4:64], r6<br>
+ vld4.16 {d0, d2, d4, d6}, [r4:128], r6<br>
+ vld4.16 {d0, d2, d4, d6}, [r4:256], r6<br>
+<br>
+@ CHECK: vld4.16 {d0, d2, d4, d6}, [r4], r6 @ encoding: [0x24,0xf9,0x46,0x01]<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted<br>
+@ CHECK-ERRORS: vld4.16 {d0, d2, d4, d6}, [r4:16], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted<br>
+@ CHECK-ERRORS: vld4.16 {d0, d2, d4, d6}, [r4:32], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vld4.16 {d0, d2, d4, d6}, [r4:64], r6 @ encoding: [0x24,0xf9,0x56,0x01]<br>
+@ CHECK: vld4.16 {d0, d2, d4, d6}, [r4:128], r6 @ encoding: [0x24,0xf9,0x66,0x01]<br>
+@ CHECK: vld4.16 {d0, d2, d4, d6}, [r4:256], r6 @ encoding: [0x24,0xf9,0x76,0x01]<br>
+<br>
+ vld4.16 {d0[1], d1[1], d2[1], d3[1]}, [r4]<br>
+ vld4.16 {d0[1], d1[1], d2[1], d3[1]}, [r4:16]<br>
+ vld4.16 {d0[1], d1[1], d2[1], d3[1]}, [r4:32]<br>
+ vld4.16 {d0[1], d1[1], d2[1], d3[1]}, [r4:64]<br>
+ vld4.16 {d0[1], d1[1], d2[1], d3[1]}, [r4:128]<br>
+ vld4.16 {d0[1], d1[1], d2[1], d3[1]}, [r4:256]<br>
+<br>
+@ CHECK: vld4.16 {d0[1], d1[1], d2[1], d3[1]}, [r4] @ encoding: [0xa4,0xf9,0x4f,0x07]<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vld4.16 {d0[1], d1[1], d2[1], d3[1]}, [r4:16]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vld4.16 {d0[1], d1[1], d2[1], d3[1]}, [r4:32]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vld4.16 {d0[1], d1[1], d2[1], d3[1]}, [r4:64] @ encoding: [0xa4,0xf9,0x5f,0x07]<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vld4.16 {d0[1], d1[1], d2[1], d3[1]}, [r4:128]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vld4.16 {d0[1], d1[1], d2[1], d3[1]}, [r4:256]<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vld4.16 {d0[1], d1[1], d2[1], d3[1]}, [r4]!<br>
+ vld4.16 {d0[1], d1[1], d2[1], d3[1]}, [r4:16]!<br>
+ vld4.16 {d0[1], d1[1], d2[1], d3[1]}, [r4:32]!<br>
+ vld4.16 {d0[1], d1[1], d2[1], d3[1]}, [r4:64]!<br>
+ vld4.16 {d0[1], d1[1], d2[1], d3[1]}, [r4:128]!<br>
+ vld4.16 {d0[1], d1[1], d2[1], d3[1]}, [r4:256]!<br>
+<br>
+@ CHECK: vld4.16 {d0[1], d1[1], d2[1], d3[1]}, [r4]! @ encoding: [0xa4,0xf9,0x4d,0x07]<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vld4.16 {d0[1], d1[1], d2[1], d3[1]}, [r4:16]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vld4.16 {d0[1], d1[1], d2[1], d3[1]}, [r4:32]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vld4.16 {d0[1], d1[1], d2[1], d3[1]}, [r4:64]! @ encoding: [0xa4,0xf9,0x5d,0x07]<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vld4.16 {d0[1], d1[1], d2[1], d3[1]}, [r4:128]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vld4.16 {d0[1], d1[1], d2[1], d3[1]}, [r4:256]!<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vld4.16 {d0[1], d1[1], d2[1], d3[1]}, [r4], r6<br>
+ vld4.16 {d0[1], d1[1], d2[1], d3[1]}, [r4:16], r6<br>
+ vld4.16 {d0[1], d1[1], d2[1], d3[1]}, [r4:32], r6<br>
+ vld4.16 {d0[1], d1[1], d2[1], d3[1]}, [r4:64], r6<br>
+ vld4.16 {d0[1], d1[1], d2[1], d3[1]}, [r4:128], r6<br>
+ vld4.16 {d0[1], d1[1], d2[1], d3[1]}, [r4:256], r6<br>
+<br>
+@ CHECK: vld4.16 {d0[1], d1[1], d2[1], d3[1]}, [r4], r6 @ encoding: [0xa4,0xf9,0x46,0x07]<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vld4.16 {d0[1], d1[1], d2[1], d3[1]}, [r4:16], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vld4.16 {d0[1], d1[1], d2[1], d3[1]}, [r4:32], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vld4.16 {d0[1], d1[1], d2[1], d3[1]}, [r4:64], r6 @ encoding: [0xa4,0xf9,0x56,0x07]<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vld4.16 {d0[1], d1[1], d2[1], d3[1]}, [r4:128], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vld4.16 {d0[1], d1[1], d2[1], d3[1]}, [r4:256], r6<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vld4.16 {d0[1], d2[1], d4[1], d6[1]}, [r4]<br>
+ vld4.16 {d0[1], d2[1], d4[1], d6[1]}, [r4:16]<br>
+ vld4.16 {d0[1], d2[1], d4[1], d6[1]}, [r4:32]<br>
+ vld4.16 {d0[1], d2[1], d4[1], d6[1]}, [r4:64]<br>
+ vld4.16 {d0[1], d2[1], d4[1], d6[1]}, [r4:128]<br>
+ vld4.16 {d0[1], d2[1], d4[1], d6[1]}, [r4:256]<br>
+<br>
+@ CHECK: vld4.16 {d0[1], d2[1], d4[1], d6[1]}, [r4] @ encoding: [0xa4,0xf9,0x6f,0x07]<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vld4.16 {d0[1], d2[1], d4[1], d6[1]}, [r4:16]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vld4.16 {d0[1], d2[1], d4[1], d6[1]}, [r4:32]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vld4.16 {d0[1], d2[1], d4[1], d6[1]}, [r4:64] @ encoding: [0xa4,0xf9,0x7f,0x07]<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vld4.16 {d0[1], d2[1], d4[1], d6[1]}, [r4:128]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vld4.16 {d0[1], d2[1], d4[1], d6[1]}, [r4:256]<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vld4.16 {d0[1], d2[1], d4[1], d6[1]}, [r4]!<br>
+ vld4.16 {d0[1], d2[1], d4[1], d6[1]}, [r4:16]!<br>
+ vld4.16 {d0[1], d2[1], d4[1], d6[1]}, [r4:32]!<br>
+ vld4.16 {d0[1], d2[1], d4[1], d6[1]}, [r4:64]!<br>
+ vld4.16 {d0[1], d2[1], d4[1], d6[1]}, [r4:128]!<br>
+ vld4.16 {d0[1], d2[1], d4[1], d6[1]}, [r4:256]!<br>
+<br>
+@ CHECK: vld4.16 {d0[1], d2[1], d4[1], d6[1]}, [r4]! @ encoding: [0xa4,0xf9,0x6d,0x07]<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vld4.16 {d0[1], d2[1], d4[1], d6[1]}, [r4:16]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vld4.16 {d0[1], d2[1], d4[1], d6[1]}, [r4:32]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vld4.16 {d0[1], d2[1], d4[1], d6[1]}, [r4:64]! @ encoding: [0xa4,0xf9,0x7d,0x07]<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vld4.16 {d0[1], d2[1], d4[1], d6[1]}, [r4:128]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vld4.16 {d0[1], d2[1], d4[1], d6[1]}, [r4:256]!<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vld4.16 {d0[1], d2[1], d4[1], d6[1]}, [r4], r6<br>
+ vld4.16 {d0[1], d2[1], d4[1], d6[1]}, [r4:16], r6<br>
+ vld4.16 {d0[1], d2[1], d4[1], d6[1]}, [r4:32], r6<br>
+ vld4.16 {d0[1], d2[1], d4[1], d6[1]}, [r4:64], r6<br>
+ vld4.16 {d0[1], d2[1], d4[1], d6[1]}, [r4:128], r6<br>
+ vld4.16 {d0[1], d2[1], d4[1], d6[1]}, [r4:256], r6<br>
+<br>
+@ CHECK: vld4.16 {d0[1], d2[1], d4[1], d6[1]}, [r4], r6 @ encoding: [0xa4,0xf9,0x66,0x07]<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vld4.16 {d0[1], d2[1], d4[1], d6[1]}, [r4:16], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vld4.16 {d0[1], d2[1], d4[1], d6[1]}, [r4:32], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vld4.16 {d0[1], d2[1], d4[1], d6[1]}, [r4:64], r6 @ encoding: [0xa4,0xf9,0x76,0x07]<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vld4.16 {d0[1], d2[1], d4[1], d6[1]}, [r4:128], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vld4.16 {d0[1], d2[1], d4[1], d6[1]}, [r4:256], r6<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vld4.16 {d0[], d1[], d2[], d3[]}, [r4]<br>
+ vld4.16 {d0[], d1[], d2[], d3[]}, [r4:16]<br>
+ vld4.16 {d0[], d1[], d2[], d3[]}, [r4:32]<br>
+ vld4.16 {d0[], d1[], d2[], d3[]}, [r4:64]<br>
+ vld4.16 {d0[], d1[], d2[], d3[]}, [r4:128]<br>
+ vld4.16 {d0[], d1[], d2[], d3[]}, [r4:256]<br>
+<br>
+@ CHECK: vld4.16 {d0[], d1[], d2[], d3[]}, [r4] @ encoding: [0xa4,0xf9,0x4f,0x0f]<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vld4.16 {d0[], d1[], d2[], d3[]}, [r4:16]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vld4.16 {d0[], d1[], d2[], d3[]}, [r4:32]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vld4.16 {d0[], d1[], d2[], d3[]}, [r4:64] @ encoding: [0xa4,0xf9,0x5f,0x0f]<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vld4.16 {d0[], d1[], d2[], d3[]}, [r4:128]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vld4.16 {d0[], d1[], d2[], d3[]}, [r4:256]<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vld4.16 {d0[], d1[], d2[], d3[]}, [r4]!<br>
+ vld4.16 {d0[], d1[], d2[], d3[]}, [r4:16]!<br>
+ vld4.16 {d0[], d1[], d2[], d3[]}, [r4:32]!<br>
+ vld4.16 {d0[], d1[], d2[], d3[]}, [r4:64]!<br>
+ vld4.16 {d0[], d1[], d2[], d3[]}, [r4:128]!<br>
+ vld4.16 {d0[], d1[], d2[], d3[]}, [r4:256]!<br>
+<br>
+@ CHECK: vld4.16 {d0[], d1[], d2[], d3[]}, [r4]! @ encoding: [0xa4,0xf9,0x4d,0x0f]<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vld4.16 {d0[], d1[], d2[], d3[]}, [r4:16]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vld4.16 {d0[], d1[], d2[], d3[]}, [r4:32]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vld4.16 {d0[], d1[], d2[], d3[]}, [r4:64]! @ encoding: [0xa4,0xf9,0x5d,0x0f]<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vld4.16 {d0[], d1[], d2[], d3[]}, [r4:128]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vld4.16 {d0[], d1[], d2[], d3[]}, [r4:256]!<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vld4.16 {d0[], d1[], d2[], d3[]}, [r4], r6<br>
+ vld4.16 {d0[], d1[], d2[], d3[]}, [r4:16], r6<br>
+ vld4.16 {d0[], d1[], d2[], d3[]}, [r4:32], r6<br>
+ vld4.16 {d0[], d1[], d2[], d3[]}, [r4:64], r6<br>
+ vld4.16 {d0[], d1[], d2[], d3[]}, [r4:128], r6<br>
+ vld4.16 {d0[], d1[], d2[], d3[]}, [r4:256], r6<br>
+<br>
+@ CHECK: vld4.16 {d0[], d1[], d2[], d3[]}, [r4], r6 @ encoding: [0xa4,0xf9,0x46,0x0f]<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vld4.16 {d0[], d1[], d2[], d3[]}, [r4:16], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vld4.16 {d0[], d1[], d2[], d3[]}, [r4:32], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vld4.16 {d0[], d1[], d2[], d3[]}, [r4:64], r6 @ encoding: [0xa4,0xf9,0x56,0x0f]<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vld4.16 {d0[], d1[], d2[], d3[]}, [r4:128], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vld4.16 {d0[], d1[], d2[], d3[]}, [r4:256], r6<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vld4.16 {d0[], d2[], d4[], d6[]}, [r4]<br>
+ vld4.16 {d0[], d2[], d4[], d6[]}, [r4:16]<br>
+ vld4.16 {d0[], d2[], d4[], d6[]}, [r4:32]<br>
+ vld4.16 {d0[], d2[], d4[], d6[]}, [r4:64]<br>
+ vld4.16 {d0[], d2[], d4[], d6[]}, [r4:128]<br>
+ vld4.16 {d0[], d2[], d4[], d6[]}, [r4:256]<br>
+<br>
+@ CHECK: vld4.16 {d0[], d2[], d4[], d6[]}, [r4] @ encoding: [0xa4,0xf9,0x6f,0x0f]<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vld4.16 {d0[], d2[], d4[], d6[]}, [r4:16]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vld4.16 {d0[], d2[], d4[], d6[]}, [r4:32]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vld4.16 {d0[], d2[], d4[], d6[]}, [r4:64] @ encoding: [0xa4,0xf9,0x7f,0x0f]<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vld4.16 {d0[], d2[], d4[], d6[]}, [r4:128]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vld4.16 {d0[], d2[], d4[], d6[]}, [r4:256]<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vld4.16 {d0[], d2[], d4[], d6[]}, [r4]!<br>
+ vld4.16 {d0[], d2[], d4[], d6[]}, [r4:16]!<br>
+ vld4.16 {d0[], d2[], d4[], d6[]}, [r4:32]!<br>
+ vld4.16 {d0[], d2[], d4[], d6[]}, [r4:64]!<br>
+ vld4.16 {d0[], d2[], d4[], d6[]}, [r4:128]!<br>
+ vld4.16 {d0[], d2[], d4[], d6[]}, [r4:256]!<br>
+<br>
+@ CHECK: vld4.16 {d0[], d1[], d2[], d3[]}, [r4]! @ encoding: [0xa4,0xf9,0x6d,0x0f]<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vld4.16 {d0[], d2[], d4[], d6[]}, [r4:16]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vld4.16 {d0[], d2[], d4[], d6[]}, [r4:32]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vld4.16 {d0[], d1[], d2[], d3[]}, [r4:64]! @ encoding: [0xa4,0xf9,0x7d,0x0f]<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vld4.16 {d0[], d2[], d4[], d6[]}, [r4:128]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vld4.16 {d0[], d2[], d4[], d6[]}, [r4:256]!<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vld4.16 {d0[], d2[], d4[], d6[]}, [r4], r6<br>
+ vld4.16 {d0[], d2[], d4[], d6[]}, [r4:16], r6<br>
+ vld4.16 {d0[], d2[], d4[], d6[]}, [r4:32], r6<br>
+ vld4.16 {d0[], d2[], d4[], d6[]}, [r4:64], r6<br>
+ vld4.16 {d0[], d2[], d4[], d6[]}, [r4:128], r6<br>
+ vld4.16 {d0[], d2[], d4[], d6[]}, [r4:256], r6<br>
+<br>
+@ CHECK: vld4.16 {d0[], d2[], d4[], d6[]}, [r4], r6 @ encoding: [0xa4,0xf9,0x66,0x0f]<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vld4.16 {d0[], d2[], d4[], d6[]}, [r4:16], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vld4.16 {d0[], d2[], d4[], d6[]}, [r4:32], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vld4.16 {d0[], d2[], d4[], d6[]}, [r4:64], r6 @ encoding: [0xa4,0xf9,0x76,0x0f]<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vld4.16 {d0[], d2[], d4[], d6[]}, [r4:128], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vld4.16 {d0[], d2[], d4[], d6[]}, [r4:256], r6<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vld4.32 {d0, d1, d2, d3}, [r4]<br>
+ vld4.32 {d0, d1, d2, d3}, [r4:16]<br>
+ vld4.32 {d0, d1, d2, d3}, [r4:32]<br>
+ vld4.32 {d0, d1, d2, d3}, [r4:64]<br>
+ vld4.32 {d0, d1, d2, d3}, [r4:128]<br>
+ vld4.32 {d0, d1, d2, d3}, [r4:256]<br>
+<br>
+@ CHECK: vld4.32 {d0, d1, d2, d3}, [r4] @ encoding: [0x24,0xf9,0x8f,0x00]<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted<br>
+@ CHECK-ERRORS: vld4.32 {d0, d1, d2, d3}, [r4:16]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted<br>
+@ CHECK-ERRORS: vld4.32 {d0, d1, d2, d3}, [r4:32]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vld4.32 {d0, d1, d2, d3}, [r4:64] @ encoding: [0x24,0xf9,0x9f,0x00]<br>
+@ CHECK: vld4.32 {d0, d1, d2, d3}, [r4:128] @ encoding: [0x24,0xf9,0xaf,0x00]<br>
+@ CHECK: vld4.32 {d0, d1, d2, d3}, [r4:256] @ encoding: [0x24,0xf9,0xbf,0x00]<br>
+<br>
+ vld4.32 {d0, d1, d2, d3}, [r4]!<br>
+ vld4.32 {d0, d1, d2, d3}, [r4:16]!<br>
+ vld4.32 {d0, d1, d2, d3}, [r4:32]!<br>
+ vld4.32 {d0, d1, d2, d3}, [r4:64]!<br>
+ vld4.32 {d0, d1, d2, d3}, [r4:128]!<br>
+ vld4.32 {d0, d1, d2, d3}, [r4:256]!<br>
+<br>
+@ CHECK: vld4.32 {d0, d1, d2, d3}, [r4]! @ encoding: [0x24,0xf9,0x8d,0x00]<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted<br>
+@ CHECK-ERRORS: vld4.32 {d0, d1, d2, d3}, [r4:16]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted<br>
+@ CHECK-ERRORS: vld4.32 {d0, d1, d2, d3}, [r4:32]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vld4.32 {d0, d1, d2, d3}, [r4:64]! @ encoding: [0x24,0xf9,0x9d,0x00]<br>
+@ CHECK: vld4.32 {d0, d1, d2, d3}, [r4:128]! @ encoding: [0x24,0xf9,0xad,0x00]<br>
+@ CHECK: vld4.32 {d0, d1, d2, d3}, [r4:256]! @ encoding: [0x24,0xf9,0xbd,0x00]<br>
+<br>
+ vld4.32 {d0, d1, d2, d3}, [r4], r6<br>
+ vld4.32 {d0, d1, d2, d3}, [r4:16], r6<br>
+ vld4.32 {d0, d1, d2, d3}, [r4:32], r6<br>
+ vld4.32 {d0, d1, d2, d3}, [r4:64], r6<br>
+ vld4.32 {d0, d1, d2, d3}, [r4:128], r6<br>
+ vld4.32 {d0, d1, d2, d3}, [r4:256], r6<br>
+<br>
+@ CHECK: vld4.32 {d0, d1, d2, d3}, [r4], r6 @ encoding: [0x24,0xf9,0x86,0x00]<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted<br>
+@ CHECK-ERRORS: vld4.32 {d0, d1, d2, d3}, [r4:16], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted<br>
+@ CHECK-ERRORS: vld4.32 {d0, d1, d2, d3}, [r4:32], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vld4.32 {d0, d1, d2, d3}, [r4:64], r6 @ encoding: [0x24,0xf9,0x96,0x00]<br>
+@ CHECK: vld4.32 {d0, d1, d2, d3}, [r4:128], r6 @ encoding: [0x24,0xf9,0xa6,0x00]<br>
+@ CHECK: vld4.32 {d0, d1, d2, d3}, [r4:256], r6 @ encoding: [0x24,0xf9,0xb6,0x00]<br>
+<br>
+ vld4.32 {d0, d2, d4, d6}, [r4]<br>
+ vld4.32 {d0, d2, d4, d6}, [r4:16]<br>
+ vld4.32 {d0, d2, d4, d6}, [r4:32]<br>
+ vld4.32 {d0, d2, d4, d6}, [r4:64]<br>
+ vld4.32 {d0, d2, d4, d6}, [r4:128]<br>
+ vld4.32 {d0, d2, d4, d6}, [r4:256]<br>
+<br>
+@ CHECK: vld4.32 {d0, d2, d4, d6}, [r4] @ encoding: [0x24,0xf9,0x8f,0x01]<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted<br>
+@ CHECK-ERRORS: vld4.32 {d0, d2, d4, d6}, [r4:16]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted<br>
+@ CHECK-ERRORS: vld4.32 {d0, d2, d4, d6}, [r4:32]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vld4.32 {d0, d2, d4, d6}, [r4:64] @ encoding: [0x24,0xf9,0x9f,0x01]<br>
+@ CHECK: vld4.32 {d0, d2, d4, d6}, [r4:128] @ encoding: [0x24,0xf9,0xaf,0x01]<br>
+@ CHECK: vld4.32 {d0, d2, d4, d6}, [r4:256] @ encoding: [0x24,0xf9,0xbf,0x01]<br>
+<br>
+ vld4.32 {d0, d2, d4, d6}, [r4]!<br>
+ vld4.32 {d0, d2, d4, d6}, [r4:16]!<br>
+ vld4.32 {d0, d2, d4, d6}, [r4:32]!<br>
+ vld4.32 {d0, d2, d4, d6}, [r4:64]!<br>
+ vld4.32 {d0, d2, d4, d6}, [r4:128]!<br>
+ vld4.32 {d0, d2, d4, d6}, [r4:256]!<br>
+<br>
+@ CHECK: vld4.32 {d0, d2, d4, d6}, [r4]! @ encoding: [0x24,0xf9,0x8d,0x01]<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted<br>
+@ CHECK-ERRORS: vld4.32 {d0, d2, d4, d6}, [r4:16]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted<br>
+@ CHECK-ERRORS: vld4.32 {d0, d2, d4, d6}, [r4:32]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vld4.32 {d0, d2, d4, d6}, [r4:64]! @ encoding: [0x24,0xf9,0x9d,0x01]<br>
+@ CHECK: vld4.32 {d0, d2, d4, d6}, [r4:128]! @ encoding: [0x24,0xf9,0xad,0x01]<br>
+@ CHECK: vld4.32 {d0, d2, d4, d6}, [r4:256]! @ encoding: [0x24,0xf9,0xbd,0x01]<br>
+<br>
+ vld4.32 {d0, d2, d4, d6}, [r4], r6<br>
+ vld4.32 {d0, d2, d4, d6}, [r4:16], r6<br>
+ vld4.32 {d0, d2, d4, d6}, [r4:32], r6<br>
+ vld4.32 {d0, d2, d4, d6}, [r4:64], r6<br>
+ vld4.32 {d0, d2, d4, d6}, [r4:128], r6<br>
+ vld4.32 {d0, d2, d4, d6}, [r4:256], r6<br>
+<br>
+@ CHECK: vld4.32 {d0, d2, d4, d6}, [r4], r6 @ encoding: [0x24,0xf9,0x86,0x01]<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted<br>
+@ CHECK-ERRORS: vld4.32 {d0, d2, d4, d6}, [r4:16], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted<br>
+@ CHECK-ERRORS: vld4.32 {d0, d2, d4, d6}, [r4:32], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vld4.32 {d0, d2, d4, d6}, [r4:64], r6 @ encoding: [0x24,0xf9,0x96,0x01]<br>
+@ CHECK: vld4.32 {d0, d2, d4, d6}, [r4:128], r6 @ encoding: [0x24,0xf9,0xa6,0x01]<br>
+@ CHECK: vld4.32 {d0, d2, d4, d6}, [r4:256], r6 @ encoding: [0x24,0xf9,0xb6,0x01]<br>
+<br>
+ vld4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4]<br>
+ vld4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:16]<br>
+ vld4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:32]<br>
+ vld4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:64]<br>
+ vld4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:128]<br>
+ vld4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:256]<br>
+<br>
+@ CHECK: vld4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4] @ encoding: [0xa4,0xf9,0x8f,0x0b]<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted<br>
+@ CHECK-ERRORS: vld4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:16]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted<br>
+@ CHECK-ERRORS: vld4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:32]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vld4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:64] @ encoding: [0xa4,0xf9,0x9f,0x0b]<br>
+@ CHECK: vld4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:128] @ encoding: [0xa4,0xf9,0xaf,0x0b]<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted<br>
+@ CHECK-ERRORS: vld4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:256]<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vld4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4]!<br>
+ vld4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:16]!<br>
+ vld4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:32]!<br>
+ vld4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:64]!<br>
+ vld4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:128]!<br>
+ vld4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:256]!<br>
+<br>
+@ CHECK: vld4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4]! @ encoding: [0xa4,0xf9,0x8d,0x0b]<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted<br>
+@ CHECK-ERRORS: vld4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:16]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted<br>
+@ CHECK-ERRORS: vld4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:32]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vld4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:64]! @ encoding: [0xa4,0xf9,0x9d,0x0b]<br>
+@ CHECK: vld4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:128]! @ encoding: [0xa4,0xf9,0xad,0x0b]<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted<br>
+@ CHECK-ERRORS: vld4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:256]!<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vld4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4], r6<br>
+ vld4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:16], r6<br>
+ vld4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:32], r6<br>
+ vld4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:64], r6<br>
+ vld4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:128], r6<br>
+ vld4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:256], r6<br>
+<br>
+@ CHECK: vld4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4], r6 @ encoding: [0xa4,0xf9,0x86,0x0b]<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted<br>
+@ CHECK-ERRORS: vld4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:16], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted<br>
+@ CHECK-ERRORS: vld4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:32], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vld4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:64], r6 @ encoding: [0xa4,0xf9,0x96,0x0b]<br>
+@ CHECK: vld4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:128], r6 @ encoding: [0xa4,0xf9,0xa6,0x0b]<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted<br>
+@ CHECK-ERRORS: vld4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:256], r6<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vld4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4]<br>
+ vld4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:16]<br>
+ vld4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:32]<br>
+ vld4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:64]<br>
+ vld4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:128]<br>
+ vld4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:256]<br>
+<br>
+@ CHECK: vld4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4] @ encoding: [0xa4,0xf9,0xcf,0x0b]<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted<br>
+@ CHECK-ERRORS: vld4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:16]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted<br>
+@ CHECK-ERRORS: vld4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:32]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vld4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:64] @ encoding: [0xa4,0xf9,0xdf,0x0b]<br>
+@ CHECK: vld4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:128] @ encoding: [0xa4,0xf9,0xef,0x0b]<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted<br>
+@ CHECK-ERRORS: vld4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:256]<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vld4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4]!<br>
+ vld4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:16]!<br>
+ vld4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:32]!<br>
+ vld4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:64]!<br>
+ vld4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:128]!<br>
+ vld4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:256]!<br>
+<br>
+@ CHECK: vld4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4]! @ encoding: [0xa4,0xf9,0xcd,0x0b]<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted<br>
+@ CHECK-ERRORS: vld4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:16]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted<br>
+@ CHECK-ERRORS: vld4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:32]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vld4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:64]! @ encoding: [0xa4,0xf9,0xdd,0x0b]<br>
+@ CHECK: vld4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:128]! @ encoding: [0xa4,0xf9,0xed,0x0b]<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted<br>
+@ CHECK-ERRORS: vld4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:256]!<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vld4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4], r6<br>
+ vld4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:16], r6<br>
+ vld4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:32], r6<br>
+ vld4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:64], r6<br>
+ vld4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:128], r6<br>
+ vld4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:256], r6<br>
+<br>
+@ CHECK: vld4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4], r6 @ encoding: [0xa4,0xf9,0xc6,0x0b]<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted<br>
+@ CHECK-ERRORS: vld4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:16], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted<br>
+@ CHECK-ERRORS: vld4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:32], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vld4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:64], r6 @ encoding: [0xa4,0xf9,0xd6,0x0b]<br>
+@ CHECK: vld4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:128], r6 @ encoding: [0xa4,0xf9,0xe6,0x0b]<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted<br>
+@ CHECK-ERRORS: vld4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:256], r6<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vld4.32 {d0[], d1[], d2[], d3[]}, [r4]<br>
+ vld4.32 {d0[], d1[], d2[], d3[]}, [r4:16]<br>
+ vld4.32 {d0[], d1[], d2[], d3[]}, [r4:32]<br>
+ vld4.32 {d0[], d1[], d2[], d3[]}, [r4:64]<br>
+ vld4.32 {d0[], d1[], d2[], d3[]}, [r4:128]<br>
+ vld4.32 {d0[], d1[], d2[], d3[]}, [r4:256]<br>
+<br>
+@ CHECK: vld4.32 {d0[], d1[], d2[], d3[]}, [r4] @ encoding: [0xa4,0xf9,0x8f,0x0f]<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted<br>
+@ CHECK-ERRORS: vld4.32 {d0[], d1[], d2[], d3[]}, [r4:16]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted<br>
+@ CHECK-ERRORS: vld4.32 {d0[], d1[], d2[], d3[]}, [r4:32]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vld4.32 {d0[], d1[], d2[], d3[]}, [r4:64] @ encoding: [0xa4,0xf9,0x9f,0x0f]<br>
+@ CHECK: vld4.32 {d0[], d1[], d2[], d3[]}, [r4:128] @ encoding: [0xa4,0xf9,0xdf,0x0f]<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted<br>
+@ CHECK-ERRORS: vld4.32 {d0[], d1[], d2[], d3[]}, [r4:256]<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vld4.32 {d0[], d1[], d2[], d3[]}, [r4]!<br>
+ vld4.32 {d0[], d1[], d2[], d3[]}, [r4:16]!<br>
+ vld4.32 {d0[], d1[], d2[], d3[]}, [r4:32]!<br>
+ vld4.32 {d0[], d1[], d2[], d3[]}, [r4:64]!<br>
+ vld4.32 {d0[], d1[], d2[], d3[]}, [r4:128]!<br>
+ vld4.32 {d0[], d1[], d2[], d3[]}, [r4:256]!<br>
+<br>
+@ CHECK: vld4.32 {d0[], d1[], d2[], d3[]}, [r4]! @ encoding: [0xa4,0xf9,0x8d,0x0f]<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted<br>
+@ CHECK-ERRORS: vld4.32 {d0[], d1[], d2[], d3[]}, [r4:16]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted<br>
+@ CHECK-ERRORS: vld4.32 {d0[], d1[], d2[], d3[]}, [r4:32]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vld4.32 {d0[], d1[], d2[], d3[]}, [r4:64]! @ encoding: [0xa4,0xf9,0x9d,0x0f]<br>
+@ CHECK: vld4.32 {d0[], d1[], d2[], d3[]}, [r4:128]! @ encoding: [0xa4,0xf9,0xdd,0x0f]<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted<br>
+@ CHECK-ERRORS: vld4.32 {d0[], d1[], d2[], d3[]}, [r4:256]!<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vld4.32 {d0[], d1[], d2[], d3[]}, [r4], r6<br>
+ vld4.32 {d0[], d1[], d2[], d3[]}, [r4:16], r6<br>
+ vld4.32 {d0[], d1[], d2[], d3[]}, [r4:32], r6<br>
+ vld4.32 {d0[], d1[], d2[], d3[]}, [r4:64], r6<br>
+ vld4.32 {d0[], d1[], d2[], d3[]}, [r4:128], r6<br>
+ vld4.32 {d0[], d1[], d2[], d3[]}, [r4:256], r6<br>
+<br>
+@ CHECK: vld4.32 {d0[], d1[], d2[], d3[]}, [r4], r6 @ encoding: [0xa4,0xf9,0x86,0x0f]<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted<br>
+@ CHECK-ERRORS: vld4.32 {d0[], d1[], d2[], d3[]}, [r4:16], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted<br>
+@ CHECK-ERRORS: vld4.32 {d0[], d1[], d2[], d3[]}, [r4:32], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vld4.32 {d0[], d1[], d2[], d3[]}, [r4:64], r6 @ encoding: [0xa4,0xf9,0x96,0x0f]<br>
+@ CHECK: vld4.32 {d0[], d1[], d2[], d3[]}, [r4:128], r6 @ encoding: [0xa4,0xf9,0xd6,0x0f]<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted<br>
+@ CHECK-ERRORS: vld4.32 {d0[], d1[], d2[], d3[]}, [r4:256], r6<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vld4.32 {d0[], d2[], d4[], d6[]}, [r4]<br>
+ vld4.32 {d0[], d2[], d4[], d6[]}, [r4:16]<br>
+ vld4.32 {d0[], d2[], d4[], d6[]}, [r4:32]<br>
+ vld4.32 {d0[], d2[], d4[], d6[]}, [r4:64]<br>
+ vld4.32 {d0[], d2[], d4[], d6[]}, [r4:128]<br>
+ vld4.32 {d0[], d2[], d4[], d6[]}, [r4:256]<br>
+<br>
+@ CHECK: vld4.32 {d0[], d2[], d4[], d6[]}, [r4] @ encoding: [0xa4,0xf9,0xaf,0x0f]<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted<br>
+@ CHECK-ERRORS: vld4.32 {d0[], d2[], d4[], d6[]}, [r4:16]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted<br>
+@ CHECK-ERRORS: vld4.32 {d0[], d2[], d4[], d6[]}, [r4:32]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vld4.32 {d0[], d2[], d4[], d6[]}, [r4:64] @ encoding: [0xa4,0xf9,0xbf,0x0f]<br>
+@ CHECK: vld4.32 {d0[], d2[], d4[], d6[]}, [r4:128] @ encoding: [0xa4,0xf9,0xff,0x0f]<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted<br>
+@ CHECK-ERRORS: vld4.32 {d0[], d2[], d4[], d6[]}, [r4:256]<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vld4.32 {d0[], d2[], d4[], d6[]}, [r4]!<br>
+ vld4.32 {d0[], d2[], d4[], d6[]}, [r4:16]!<br>
+ vld4.32 {d0[], d2[], d4[], d6[]}, [r4:32]!<br>
+ vld4.32 {d0[], d2[], d4[], d6[]}, [r4:64]!<br>
+ vld4.32 {d0[], d2[], d4[], d6[]}, [r4:128]!<br>
+ vld4.32 {d0[], d2[], d4[], d6[]}, [r4:256]!<br>
+<br>
+@ CHECK: vld4.32 {d0[], d2[], d4[], d6[]}, [r4]! @ encoding: [0xa4,0xf9,0xad,0x0f]<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted<br>
+@ CHECK-ERRORS: vld4.32 {d0[], d2[], d4[], d6[]}, [r4:16]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted<br>
+@ CHECK-ERRORS: vld4.32 {d0[], d2[], d4[], d6[]}, [r4:32]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vld4.32 {d0[], d2[], d4[], d6[]}, [r4:64]! @ encoding: [0xa4,0xf9,0xbd,0x0f]<br>
+@ CHECK: vld4.32 {d0[], d2[], d4[], d6[]}, [r4:128]! @ encoding: [0xa4,0xf9,0xfd,0x0f]<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted<br>
+@ CHECK-ERRORS: vld4.32 {d0[], d2[], d4[], d6[]}, [r4:256]!<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vld4.32 {d0[], d2[], d4[], d6[]}, [r4], r6<br>
+ vld4.32 {d0[], d2[], d4[], d6[]}, [r4:16], r6<br>
+ vld4.32 {d0[], d2[], d4[], d6[]}, [r4:32], r6<br>
+ vld4.32 {d0[], d2[], d4[], d6[]}, [r4:64], r6<br>
+ vld4.32 {d0[], d2[], d4[], d6[]}, [r4:128], r6<br>
+ vld4.32 {d0[], d2[], d4[], d6[]}, [r4:256], r6<br>
+<br>
+@ CHECK: vld4.32 {d0[], d2[], d4[], d6[]}, [r4], r6 @ encoding: [0xa4,0xf9,0xa6,0x0f]<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted<br>
+@ CHECK-ERRORS: vld4.32 {d0[], d2[], d4[], d6[]}, [r4:16], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted<br>
+@ CHECK-ERRORS: vld4.32 {d0[], d2[], d4[], d6[]}, [r4:32], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vld4.32 {d0[], d2[], d4[], d6[]}, [r4:64], r6 @ encoding: [0xa4,0xf9,0xb6,0x0f]<br>
+@ CHECK: vld4.32 {d0[], d2[], d4[], d6[]}, [r4:128], r6 @ encoding: [0xa4,0xf9,0xf6,0x0f]<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted<br>
+@ CHECK-ERRORS: vld4.32 {d0[], d2[], d4[], d6[]}, [r4:256], r6<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vst1.8 {d0}, [r4]<br>
+ vst1.8 {d0}, [r4:16]<br>
+ vst1.8 {d0}, [r4:32]<br>
+ vst1.8 {d0}, [r4:64]<br>
+ vst1.8 {d0}, [r4:128]<br>
+ vst1.8 {d0}, [r4:256]<br>
+<br>
+@ CHECK: vst1.8 {d0}, [r4] @ encoding: [0x04,0xf9,0x0f,0x07]<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vst1.8 {d0}, [r4:16]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vst1.8 {d0}, [r4:32]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vst1.8 {d0}, [r4:64] @ encoding: [0x04,0xf9,0x1f,0x07]<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vst1.8 {d0}, [r4:128]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vst1.8 {d0}, [r4:256]<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vst1.8 {d0}, [r4]!<br>
+ vst1.8 {d0}, [r4:16]!<br>
+ vst1.8 {d0}, [r4:32]!<br>
+ vst1.8 {d0}, [r4:64]!<br>
+ vst1.8 {d0}, [r4:128]!<br>
+ vst1.8 {d0}, [r4:256]!<br>
+<br>
+@ CHECK: vst1.8 {d0}, [r4]! @ encoding: [0x04,0xf9,0x0d,0x07]<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vst1.8 {d0}, [r4:16]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vst1.8 {d0}, [r4:32]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vst1.8 {d0}, [r4:64]! @ encoding: [0x04,0xf9,0x1d,0x07]<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vst1.8 {d0}, [r4:128]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vst1.8 {d0}, [r4:256]!<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vst1.8 {d0}, [r4], r6<br>
+ vst1.8 {d0}, [r4:16], r6<br>
+ vst1.8 {d0}, [r4:32], r6<br>
+ vst1.8 {d0}, [r4:64], r6<br>
+ vst1.8 {d0}, [r4:128], r6<br>
+ vst1.8 {d0}, [r4:256], r6<br>
+<br>
+@ CHECK: vst1.8 {d0}, [r4], r6 @ encoding: [0x04,0xf9,0x06,0x07]<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vst1.8 {d0}, [r4:16], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vst1.8 {d0}, [r4:32], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vst1.8 {d0}, [r4:64], r6 @ encoding: [0x04,0xf9,0x16,0x07]<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vst1.8 {d0}, [r4:128], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vst1.8 {d0}, [r4:256], r6<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vst1.8 {d0, d1}, [r4]<br>
+ vst1.8 {d0, d1}, [r4:16]<br>
+ vst1.8 {d0, d1}, [r4:32]<br>
+ vst1.8 {d0, d1}, [r4:64]<br>
+ vst1.8 {d0, d1}, [r4:128]<br>
+ vst1.8 {d0, d1}, [r4:256]<br>
+<br>
+@ CHECK: vst1.8 {d0, d1}, [r4] @ encoding: [0x04,0xf9,0x0f,0x0a]<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted<br>
+@ CHECK-ERRORS: vst1.8 {d0, d1}, [r4:16]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted<br>
+@ CHECK-ERRORS: vst1.8 {d0, d1}, [r4:32]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vst1.8 {d0, d1}, [r4:64] @ encoding: [0x04,0xf9,0x1f,0x0a]<br>
+@ CHECK: vst1.8 {d0, d1}, [r4:128] @ encoding: [0x04,0xf9,0x2f,0x0a]<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted<br>
+@ CHECK-ERRORS: vst1.8 {d0, d1}, [r4:256]<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vst1.8 {d0, d1}, [r4]!<br>
+ vst1.8 {d0, d1}, [r4:16]!<br>
+ vst1.8 {d0, d1}, [r4:32]!<br>
+ vst1.8 {d0, d1}, [r4:64]!<br>
+ vst1.8 {d0, d1}, [r4:128]!<br>
+ vst1.8 {d0, d1}, [r4:256]!<br>
+<br>
+@ CHECK: vst1.8 {d0, d1}, [r4]! @ encoding: [0x04,0xf9,0x0d,0x0a]<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted<br>
+@ CHECK-ERRORS: vst1.8 {d0, d1}, [r4:16]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted<br>
+@ CHECK-ERRORS: vst1.8 {d0, d1}, [r4:32]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vst1.8 {d0, d1}, [r4:64]! @ encoding: [0x04,0xf9,0x1d,0x0a]<br>
+@ CHECK: vst1.8 {d0, d1}, [r4:128]! @ encoding: [0x04,0xf9,0x2d,0x0a]<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted<br>
+@ CHECK-ERRORS: vst1.8 {d0, d1}, [r4:256]!<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vst1.8 {d0, d1}, [r4], r6<br>
+ vst1.8 {d0, d1}, [r4:16], r6<br>
+ vst1.8 {d0, d1}, [r4:32], r6<br>
+ vst1.8 {d0, d1}, [r4:64], r6<br>
+ vst1.8 {d0, d1}, [r4:128], r6<br>
+ vst1.8 {d0, d1}, [r4:256], r6<br>
+<br>
+@ CHECK: vst1.8 {d0, d1}, [r4], r6 @ encoding: [0x04,0xf9,0x06,0x0a]<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted<br>
+@ CHECK-ERRORS: vst1.8 {d0, d1}, [r4:16], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted<br>
+@ CHECK-ERRORS: vst1.8 {d0, d1}, [r4:32], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vst1.8 {d0, d1}, [r4:64], r6 @ encoding: [0x04,0xf9,0x16,0x0a]<br>
+@ CHECK: vst1.8 {d0, d1}, [r4:128], r6 @ encoding: [0x04,0xf9,0x26,0x0a]<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted<br>
+@ CHECK-ERRORS: vst1.8 {d0, d1}, [r4:256], r6<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vst1.8 {d0, d1, d2}, [r4]<br>
+ vst1.8 {d0, d1, d2}, [r4:16]<br>
+ vst1.8 {d0, d1, d2}, [r4:32]<br>
+ vst1.8 {d0, d1, d2}, [r4:64]<br>
+ vst1.8 {d0, d1, d2}, [r4:128]<br>
+ vst1.8 {d0, d1, d2}, [r4:256]<br>
+<br>
+@ CHECK: vst1.8 {d0, d1, d2}, [r4] @ encoding: [0x04,0xf9,0x0f,0x06]<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vst1.8 {d0, d1, d2}, [r4:16]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vst1.8 {d0, d1, d2}, [r4:32]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vst1.8 {d0, d1, d2}, [r4:64] @ encoding: [0x04,0xf9,0x1f,0x06]<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vst1.8 {d0, d1, d2}, [r4:128]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vst1.8 {d0, d1, d2}, [r4:256]<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vst1.8 {d0, d1, d2}, [r4]!<br>
+ vst1.8 {d0, d1, d2}, [r4:16]!<br>
+ vst1.8 {d0, d1, d2}, [r4:32]!<br>
+ vst1.8 {d0, d1, d2}, [r4:64]!<br>
+ vst1.8 {d0, d1, d2}, [r4:128]!<br>
+ vst1.8 {d0, d1, d2}, [r4:256]!<br>
+<br>
+@ CHECK: vst1.8 {d0, d1, d2}, [r4]! @ encoding: [0x04,0xf9,0x0d,0x06]<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vst1.8 {d0, d1, d2}, [r4:16]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vst1.8 {d0, d1, d2}, [r4:32]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vst1.8 {d0, d1, d2}, [r4:64]! @ encoding: [0x04,0xf9,0x1d,0x06]<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vst1.8 {d0, d1, d2}, [r4:128]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vst1.8 {d0, d1, d2}, [r4:256]!<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vst1.8 {d0, d1, d2}, [r4], r6<br>
+ vst1.8 {d0, d1, d2}, [r4:16], r6<br>
+ vst1.8 {d0, d1, d2}, [r4:32], r6<br>
+ vst1.8 {d0, d1, d2}, [r4:64], r6<br>
+ vst1.8 {d0, d1, d2}, [r4:128], r6<br>
+ vst1.8 {d0, d1, d2}, [r4:256], r6<br>
+<br>
+@ CHECK: vst1.8 {d0, d1, d2}, [r4], r6 @ encoding: [0x04,0xf9,0x06,0x06]<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vst1.8 {d0, d1, d2}, [r4:16], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vst1.8 {d0, d1, d2}, [r4:32], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vst1.8 {d0, d1, d2}, [r4:64], r6 @ encoding: [0x04,0xf9,0x16,0x06]<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vst1.8 {d0, d1, d2}, [r4:128], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vst1.8 {d0, d1, d2}, [r4:256], r6<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vst1.8 {d0, d1, d2, d3}, [r4]<br>
+ vst1.8 {d0, d1, d2, d3}, [r4:16]<br>
+ vst1.8 {d0, d1, d2, d3}, [r4:32]<br>
+ vst1.8 {d0, d1, d2, d3}, [r4:64]<br>
+ vst1.8 {d0, d1, d2, d3}, [r4:128]<br>
+ vst1.8 {d0, d1, d2, d3}, [r4:256]<br>
+<br>
+@ CHECK: vst1.8 {d0, d1, d2, d3}, [r4] @ encoding: [0x04,0xf9,0x0f,0x02]<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted<br>
+@ CHECK-ERRORS: vst1.8 {d0, d1, d2, d3}, [r4:16]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted<br>
+@ CHECK-ERRORS: vst1.8 {d0, d1, d2, d3}, [r4:32]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vst1.8 {d0, d1, d2, d3}, [r4:64] @ encoding: [0x04,0xf9,0x1f,0x02]<br>
+@ CHECK: vst1.8 {d0, d1, d2, d3}, [r4:128] @ encoding: [0x04,0xf9,0x2f,0x02]<br>
+@ CHECK: vst1.8 {d0, d1, d2, d3}, [r4:256] @ encoding: [0x04,0xf9,0x3f,0x02]<br>
+<br>
+ vst1.8 {d0, d1, d2, d3}, [r4]!<br>
+ vst1.8 {d0, d1, d2, d3}, [r4:16]!<br>
+ vst1.8 {d0, d1, d2, d3}, [r4:32]!<br>
+ vst1.8 {d0, d1, d2, d3}, [r4:64]!<br>
+ vst1.8 {d0, d1, d2, d3}, [r4:128]!<br>
+ vst1.8 {d0, d1, d2, d3}, [r4:256]!<br>
+<br>
+@ CHECK: vst1.8 {d0, d1, d2, d3}, [r4]! @ encoding: [0x04,0xf9,0x0d,0x02]<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted<br>
+@ CHECK-ERRORS: vst1.8 {d0, d1, d2, d3}, [r4:16]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted<br>
+@ CHECK-ERRORS: vst1.8 {d0, d1, d2, d3}, [r4:32]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vst1.8 {d0, d1, d2, d3}, [r4:64]! @ encoding: [0x04,0xf9,0x1d,0x02]<br>
+@ CHECK: vst1.8 {d0, d1, d2, d3}, [r4:128]! @ encoding: [0x04,0xf9,0x2d,0x02]<br>
+@ CHECK: vst1.8 {d0, d1, d2, d3}, [r4:256]! @ encoding: [0x04,0xf9,0x3d,0x02]<br>
+<br>
+ vst1.8 {d0, d1, d2, d3}, [r4], r6<br>
+ vst1.8 {d0, d1, d2, d3}, [r4:16], r6<br>
+ vst1.8 {d0, d1, d2, d3}, [r4:32], r6<br>
+ vst1.8 {d0, d1, d2, d3}, [r4:64], r6<br>
+ vst1.8 {d0, d1, d2, d3}, [r4:128], r6<br>
+ vst1.8 {d0, d1, d2, d3}, [r4:256], r6<br>
+<br>
+@ CHECK: vst1.8 {d0, d1, d2, d3}, [r4], r6 @ encoding: [0x04,0xf9,0x06,0x02]<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted<br>
+@ CHECK-ERRORS: vst1.8 {d0, d1, d2, d3}, [r4:16], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted<br>
+@ CHECK-ERRORS: vst1.8 {d0, d1, d2, d3}, [r4:32], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vst1.8 {d0, d1, d2, d3}, [r4:64], r6 @ encoding: [0x04,0xf9,0x16,0x02]<br>
+@ CHECK: vst1.8 {d0, d1, d2, d3}, [r4:128], r6 @ encoding: [0x04,0xf9,0x26,0x02]<br>
+@ CHECK: vst1.8 {d0, d1, d2, d3}, [r4:256], r6 @ encoding: [0x04,0xf9,0x36,0x02]<br>
+<br>
+ vst1.8 {d0[2]}, [r4]<br>
+ vst1.8 {d0[2]}, [r4:16]<br>
+ vst1.8 {d0[2]}, [r4:32]<br>
+ vst1.8 {d0[2]}, [r4:64]<br>
+ vst1.8 {d0[2]}, [r4:128]<br>
+ vst1.8 {d0[2]}, [r4:256]<br>
+<br>
+@ CHECK: vst1.8 {d0[2]}, [r4] @ encoding: [0x84,0xf9,0x4f,0x00]<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vst1.8 {d0[2]}, [r4:16]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vst1.8 {d0[2]}, [r4:32]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vst1.8 {d0[2]}, [r4:64]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vst1.8 {d0[2]}, [r4:128]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vst1.8 {d0[2]}, [r4:256]<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vst1.8 {d0[2]}, [r4]!<br>
+ vst1.8 {d0[2]}, [r4:16]!<br>
+ vst1.8 {d0[2]}, [r4:32]!<br>
+ vst1.8 {d0[2]}, [r4:64]!<br>
+ vst1.8 {d0[2]}, [r4:128]!<br>
+ vst1.8 {d0[2]}, [r4:256]!<br>
+<br>
+@ CHECK: vst1.8 {d0[2]}, [r4]! @ encoding: [0x84,0xf9,0x4d,0x00]<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vst1.8 {d0[2]}, [r4:16]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vst1.8 {d0[2]}, [r4:32]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vst1.8 {d0[2]}, [r4:64]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vst1.8 {d0[2]}, [r4:128]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vst1.8 {d0[2]}, [r4:256]!<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vst1.8 {d0[2]}, [r4], r6<br>
+ vst1.8 {d0[2]}, [r4:16], r6<br>
+ vst1.8 {d0[2]}, [r4:32], r6<br>
+ vst1.8 {d0[2]}, [r4:64], r6<br>
+ vst1.8 {d0[2]}, [r4:128], r6<br>
+ vst1.8 {d0[2]}, [r4:256], r6<br>
+<br>
+@ CHECK: vst1.8 {d0[2]}, [r4], r6 @ encoding: [0x84,0xf9,0x46,0x00]<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vst1.8 {d0[2]}, [r4:16], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vst1.8 {d0[2]}, [r4:32], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vst1.8 {d0[2]}, [r4:64], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vst1.8 {d0[2]}, [r4:128], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vst1.8 {d0[2]}, [r4:256], r6<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vst1.16 {d0}, [r4]<br>
+ vst1.16 {d0}, [r4:16]<br>
+ vst1.16 {d0}, [r4:32]<br>
+ vst1.16 {d0}, [r4:64]<br>
+ vst1.16 {d0}, [r4:128]<br>
+ vst1.16 {d0}, [r4:256]<br>
+<br>
+@ CHECK: vst1.16 {d0}, [r4] @ encoding: [0x04,0xf9,0x4f,0x07]<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vst1.16 {d0}, [r4:16]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vst1.16 {d0}, [r4:32]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vst1.16 {d0}, [r4:64] @ encoding: [0x04,0xf9,0x5f,0x07]<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vst1.16 {d0}, [r4:128]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vst1.16 {d0}, [r4:256]<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vst1.16 {d0}, [r4]!<br>
+ vst1.16 {d0}, [r4:16]!<br>
+ vst1.16 {d0}, [r4:32]!<br>
+ vst1.16 {d0}, [r4:64]!<br>
+ vst1.16 {d0}, [r4:128]!<br>
+ vst1.16 {d0}, [r4:256]!<br>
+<br>
+@ CHECK: vst1.16 {d0}, [r4]! @ encoding: [0x04,0xf9,0x4d,0x07]<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vst1.16 {d0}, [r4:16]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vst1.16 {d0}, [r4:32]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vst1.16 {d0}, [r4:64]! @ encoding: [0x04,0xf9,0x5d,0x07]<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vst1.16 {d0}, [r4:128]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vst1.16 {d0}, [r4:256]!<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vst1.16 {d0}, [r4], r6<br>
+ vst1.16 {d0}, [r4:16], r6<br>
+ vst1.16 {d0}, [r4:32], r6<br>
+ vst1.16 {d0}, [r4:64], r6<br>
+ vst1.16 {d0}, [r4:128], r6<br>
+ vst1.16 {d0}, [r4:256], r6<br>
+<br>
+@ CHECK: vst1.16 {d0}, [r4], r6 @ encoding: [0x04,0xf9,0x46,0x07]<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vst1.16 {d0}, [r4:16], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vst1.16 {d0}, [r4:32], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vst1.16 {d0}, [r4:64], r6 @ encoding: [0x04,0xf9,0x56,0x07]<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vst1.16 {d0}, [r4:128], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vst1.16 {d0}, [r4:256], r6<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vst1.16 {d0, d1}, [r4]<br>
+ vst1.16 {d0, d1}, [r4:16]<br>
+ vst1.16 {d0, d1}, [r4:32]<br>
+ vst1.16 {d0, d1}, [r4:64]<br>
+ vst1.16 {d0, d1}, [r4:128]<br>
+ vst1.16 {d0, d1}, [r4:256]<br>
+<br>
+@ CHECK: vst1.16 {d0, d1}, [r4] @ encoding: [0x04,0xf9,0x4f,0x0a]<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted<br>
+@ CHECK-ERRORS: vst1.16 {d0, d1}, [r4:16]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted<br>
+@ CHECK-ERRORS: vst1.16 {d0, d1}, [r4:32]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vst1.16 {d0, d1}, [r4:64] @ encoding: [0x04,0xf9,0x5f,0x0a]<br>
+@ CHECK: vst1.16 {d0, d1}, [r4:128] @ encoding: [0x04,0xf9,0x6f,0x0a]<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted<br>
+@ CHECK-ERRORS: vst1.16 {d0, d1}, [r4:256]<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vst1.16 {d0, d1}, [r4]!<br>
+ vst1.16 {d0, d1}, [r4:16]!<br>
+ vst1.16 {d0, d1}, [r4:32]!<br>
+ vst1.16 {d0, d1}, [r4:64]!<br>
+ vst1.16 {d0, d1}, [r4:128]!<br>
+ vst1.16 {d0, d1}, [r4:256]!<br>
+<br>
+@ CHECK: vst1.16 {d0, d1}, [r4]! @ encoding: [0x04,0xf9,0x4d,0x0a]<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted<br>
+@ CHECK-ERRORS: vst1.16 {d0, d1}, [r4:16]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted<br>
+@ CHECK-ERRORS: vst1.16 {d0, d1}, [r4:32]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vst1.16 {d0, d1}, [r4:64]! @ encoding: [0x04,0xf9,0x5d,0x0a]<br>
+@ CHECK: vst1.16 {d0, d1}, [r4:128]! @ encoding: [0x04,0xf9,0x6d,0x0a]<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted<br>
+@ CHECK-ERRORS: vst1.16 {d0, d1}, [r4:256]!<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vst1.16 {d0, d1}, [r4], r6<br>
+ vst1.16 {d0, d1}, [r4:16], r6<br>
+ vst1.16 {d0, d1}, [r4:32], r6<br>
+ vst1.16 {d0, d1}, [r4:64], r6<br>
+ vst1.16 {d0, d1}, [r4:128], r6<br>
+ vst1.16 {d0, d1}, [r4:256], r6<br>
+<br>
+@ CHECK: vst1.16 {d0, d1}, [r4], r6 @ encoding: [0x04,0xf9,0x46,0x0a]<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted<br>
+@ CHECK-ERRORS: vst1.16 {d0, d1}, [r4:16], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted<br>
+@ CHECK-ERRORS: vst1.16 {d0, d1}, [r4:32], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vst1.16 {d0, d1}, [r4:64], r6 @ encoding: [0x04,0xf9,0x56,0x0a]<br>
+@ CHECK: vst1.16 {d0, d1}, [r4:128], r6 @ encoding: [0x04,0xf9,0x66,0x0a]<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted<br>
+@ CHECK-ERRORS: vst1.16 {d0, d1}, [r4:256], r6<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vst1.16 {d0, d1, d2}, [r4]<br>
+ vst1.16 {d0, d1, d2}, [r4:16]<br>
+ vst1.16 {d0, d1, d2}, [r4:32]<br>
+ vst1.16 {d0, d1, d2}, [r4:64]<br>
+ vst1.16 {d0, d1, d2}, [r4:128]<br>
+ vst1.16 {d0, d1, d2}, [r4:256]<br>
+<br>
+@ CHECK: vst1.16 {d0, d1, d2}, [r4] @ encoding: [0x04,0xf9,0x4f,0x06]<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vst1.16 {d0, d1, d2}, [r4:16]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vst1.16 {d0, d1, d2}, [r4:32]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vst1.16 {d0, d1, d2}, [r4:64] @ encoding: [0x04,0xf9,0x5f,0x06]<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vst1.16 {d0, d1, d2}, [r4:128]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vst1.16 {d0, d1, d2}, [r4:256]<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vst1.16 {d0, d1, d2}, [r4]!<br>
+ vst1.16 {d0, d1, d2}, [r4:16]!<br>
+ vst1.16 {d0, d1, d2}, [r4:32]!<br>
+ vst1.16 {d0, d1, d2}, [r4:64]!<br>
+ vst1.16 {d0, d1, d2}, [r4:128]!<br>
+ vst1.16 {d0, d1, d2}, [r4:256]!<br>
+<br>
+@ CHECK: vst1.16 {d0, d1, d2}, [r4]! @ encoding: [0x04,0xf9,0x4d,0x06]<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vst1.16 {d0, d1, d2}, [r4:16]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vst1.16 {d0, d1, d2}, [r4:32]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vst1.16 {d0, d1, d2}, [r4:64]! @ encoding: [0x04,0xf9,0x5d,0x06]<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vst1.16 {d0, d1, d2}, [r4:128]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vst1.16 {d0, d1, d2}, [r4:256]!<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vst1.16 {d0, d1, d2}, [r4], r6<br>
+ vst1.16 {d0, d1, d2}, [r4:16], r6<br>
+ vst1.16 {d0, d1, d2}, [r4:32], r6<br>
+ vst1.16 {d0, d1, d2}, [r4:64], r6<br>
+ vst1.16 {d0, d1, d2}, [r4:128], r6<br>
+ vst1.16 {d0, d1, d2}, [r4:256], r6<br>
+<br>
+@ CHECK: vst1.16 {d0, d1, d2}, [r4], r6 @ encoding: [0x04,0xf9,0x46,0x06]<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vst1.16 {d0, d1, d2}, [r4:16], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vst1.16 {d0, d1, d2}, [r4:32], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vst1.16 {d0, d1, d2}, [r4:64], r6 @ encoding: [0x04,0xf9,0x56,0x06]<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vst1.16 {d0, d1, d2}, [r4:128], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vst1.16 {d0, d1, d2}, [r4:256], r6<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vst1.16 {d0, d1, d2, d3}, [r4]<br>
+ vst1.16 {d0, d1, d2, d3}, [r4:16]<br>
+ vst1.16 {d0, d1, d2, d3}, [r4:32]<br>
+ vst1.16 {d0, d1, d2, d3}, [r4:64]<br>
+ vst1.16 {d0, d1, d2, d3}, [r4:128]<br>
+ vst1.16 {d0, d1, d2, d3}, [r4:256]<br>
+<br>
+@ CHECK: vst1.16 {d0, d1, d2, d3}, [r4] @ encoding: [0x04,0xf9,0x4f,0x02]<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted<br>
+@ CHECK-ERRORS: vst1.16 {d0, d1, d2, d3}, [r4:16]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted<br>
+@ CHECK-ERRORS: vst1.16 {d0, d1, d2, d3}, [r4:32]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vst1.16 {d0, d1, d2, d3}, [r4:64] @ encoding: [0x04,0xf9,0x5f,0x02]<br>
+@ CHECK: vst1.16 {d0, d1, d2, d3}, [r4:128] @ encoding: [0x04,0xf9,0x6f,0x02]<br>
+@ CHECK: vst1.16 {d0, d1, d2, d3}, [r4:256] @ encoding: [0x04,0xf9,0x7f,0x02]<br>
+<br>
+ vst1.16 {d0, d1, d2, d3}, [r4]!<br>
+ vst1.16 {d0, d1, d2, d3}, [r4:16]!<br>
+ vst1.16 {d0, d1, d2, d3}, [r4:32]!<br>
+ vst1.16 {d0, d1, d2, d3}, [r4:64]!<br>
+ vst1.16 {d0, d1, d2, d3}, [r4:128]!<br>
+ vst1.16 {d0, d1, d2, d3}, [r4:256]!<br>
+<br>
+@ CHECK: vst1.16 {d0, d1, d2, d3}, [r4]! @ encoding: [0x04,0xf9,0x4d,0x02]<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted<br>
+@ CHECK-ERRORS: vst1.16 {d0, d1, d2, d3}, [r4:16]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted<br>
+@ CHECK-ERRORS: vst1.16 {d0, d1, d2, d3}, [r4:32]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vst1.16 {d0, d1, d2, d3}, [r4:64]! @ encoding: [0x04,0xf9,0x5d,0x02]<br>
+@ CHECK: vst1.16 {d0, d1, d2, d3}, [r4:128]! @ encoding: [0x04,0xf9,0x6d,0x02]<br>
+@ CHECK: vst1.16 {d0, d1, d2, d3}, [r4:256]! @ encoding: [0x04,0xf9,0x7d,0x02]<br>
+<br>
+ vst1.16 {d0, d1, d2, d3}, [r4], r6<br>
+ vst1.16 {d0, d1, d2, d3}, [r4:16], r6<br>
+ vst1.16 {d0, d1, d2, d3}, [r4:32], r6<br>
+ vst1.16 {d0, d1, d2, d3}, [r4:64], r6<br>
+ vst1.16 {d0, d1, d2, d3}, [r4:128], r6<br>
+ vst1.16 {d0, d1, d2, d3}, [r4:256], r6<br>
+<br>
+@ CHECK: vst1.16 {d0, d1, d2, d3}, [r4], r6 @ encoding: [0x04,0xf9,0x46,0x02]<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted<br>
+@ CHECK-ERRORS: vst1.16 {d0, d1, d2, d3}, [r4:16], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted<br>
+@ CHECK-ERRORS: vst1.16 {d0, d1, d2, d3}, [r4:32], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vst1.16 {d0, d1, d2, d3}, [r4:64], r6 @ encoding: [0x04,0xf9,0x56,0x02]<br>
+@ CHECK: vst1.16 {d0, d1, d2, d3}, [r4:128], r6 @ encoding: [0x04,0xf9,0x66,0x02]<br>
+@ CHECK: vst1.16 {d0, d1, d2, d3}, [r4:256], r6 @ encoding: [0x04,0xf9,0x76,0x02]<br>
+<br>
+ vst1.16 {d0[2]}, [r4]<br>
+ vst1.16 {d0[2]}, [r4:16]<br>
+ vst1.16 {d0[2]}, [r4:32]<br>
+ vst1.16 {d0[2]}, [r4:64]<br>
+ vst1.16 {d0[2]}, [r4:128]<br>
+ vst1.16 {d0[2]}, [r4:256]<br>
+<br>
+@ CHECK: vst1.16 {d0[2]}, [r4] @ encoding: [0x84,0xf9,0x8f,0x04]<br>
+@ CHECK: vst1.16 {d0[2]}, [r4:16] @ encoding: [0x84,0xf9,0x9f,0x04]<br>
+@ CHECK-ERRORS: error: alignment must be 16 or omitted<br>
+@ CHECK-ERRORS: vst1.16 {d0[2]}, [r4:32]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 16 or omitted<br>
+@ CHECK-ERRORS: vst1.16 {d0[2]}, [r4:64]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 16 or omitted<br>
+@ CHECK-ERRORS: vst1.16 {d0[2]}, [r4:128]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 16 or omitted<br>
+@ CHECK-ERRORS: vst1.16 {d0[2]}, [r4:256]<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vst1.16 {d0[2]}, [r4]!<br>
+ vst1.16 {d0[2]}, [r4:16]!<br>
+ vst1.16 {d0[2]}, [r4:32]!<br>
+ vst1.16 {d0[2]}, [r4:64]!<br>
+ vst1.16 {d0[2]}, [r4:128]!<br>
+ vst1.16 {d0[2]}, [r4:256]!<br>
+<br>
+@ CHECK: vst1.16 {d0[2]}, [r4]! @ encoding: [0x84,0xf9,0x8d,0x04]<br>
+@ CHECK: vst1.16 {d0[2]}, [r4:16]! @ encoding: [0x84,0xf9,0x9d,0x04]<br>
+@ CHECK-ERRORS: error: alignment must be 16 or omitted<br>
+@ CHECK-ERRORS: vst1.16 {d0[2]}, [r4:32]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 16 or omitted<br>
+@ CHECK-ERRORS: vst1.16 {d0[2]}, [r4:64]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 16 or omitted<br>
+@ CHECK-ERRORS: vst1.16 {d0[2]}, [r4:128]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 16 or omitted<br>
+@ CHECK-ERRORS: vst1.16 {d0[2]}, [r4:256]!<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vst1.16 {d0[2]}, [r4], r6<br>
+ vst1.16 {d0[2]}, [r4:16], r6<br>
+ vst1.16 {d0[2]}, [r4:32], r6<br>
+ vst1.16 {d0[2]}, [r4:64], r6<br>
+ vst1.16 {d0[2]}, [r4:128], r6<br>
+ vst1.16 {d0[2]}, [r4:256], r6<br>
+<br>
+@ CHECK: vst1.16 {d0[2]}, [r4], r6 @ encoding: [0x84,0xf9,0x86,0x04]<br>
+@ CHECK: vst1.16 {d0[2]}, [r4:16], r6 @ encoding: [0x84,0xf9,0x96,0x04]<br>
+@ CHECK-ERRORS: error: alignment must be 16 or omitted<br>
+@ CHECK-ERRORS: vst1.16 {d0[2]}, [r4:32], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 16 or omitted<br>
+@ CHECK-ERRORS: vst1.16 {d0[2]}, [r4:64], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 16 or omitted<br>
+@ CHECK-ERRORS: vst1.16 {d0[2]}, [r4:128], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 16 or omitted<br>
+@ CHECK-ERRORS: vst1.16 {d0[2]}, [r4:256], r6<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vst1.32 {d0}, [r4]<br>
+ vst1.32 {d0}, [r4:16]<br>
+ vst1.32 {d0}, [r4:32]<br>
+ vst1.32 {d0}, [r4:64]<br>
+ vst1.32 {d0}, [r4:128]<br>
+ vst1.32 {d0}, [r4:256]<br>
+<br>
+@ CHECK: vst1.32 {d0}, [r4] @ encoding: [0x04,0xf9,0x8f,0x07]<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vst1.32 {d0}, [r4:16]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vst1.32 {d0}, [r4:32]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vst1.32 {d0}, [r4:64] @ encoding: [0x04,0xf9,0x9f,0x07]<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vst1.32 {d0}, [r4:128]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vst1.32 {d0}, [r4:256]<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vst1.32 {d0}, [r4]!<br>
+ vst1.32 {d0}, [r4:16]!<br>
+ vst1.32 {d0}, [r4:32]!<br>
+ vst1.32 {d0}, [r4:64]!<br>
+ vst1.32 {d0}, [r4:128]!<br>
+ vst1.32 {d0}, [r4:256]!<br>
+<br>
+@ CHECK: vst1.32 {d0}, [r4]! @ encoding: [0x04,0xf9,0x8d,0x07]<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vst1.32 {d0}, [r4:16]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vst1.32 {d0}, [r4:32]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vst1.32 {d0}, [r4:64]! @ encoding: [0x04,0xf9,0x9d,0x07]<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vst1.32 {d0}, [r4:128]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vst1.32 {d0}, [r4:256]!<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vst1.32 {d0}, [r4], r6<br>
+ vst1.32 {d0}, [r4:16], r6<br>
+ vst1.32 {d0}, [r4:32], r6<br>
+ vst1.32 {d0}, [r4:64], r6<br>
+ vst1.32 {d0}, [r4:128], r6<br>
+ vst1.32 {d0}, [r4:256], r6<br>
+<br>
+@ CHECK: vst1.32 {d0}, [r4], r6 @ encoding: [0x04,0xf9,0x86,0x07]<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vst1.32 {d0}, [r4:16], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vst1.32 {d0}, [r4:32], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vst1.32 {d0}, [r4:64], r6 @ encoding: [0x04,0xf9,0x96,0x07]<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vst1.32 {d0}, [r4:128], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vst1.32 {d0}, [r4:256], r6<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vst1.32 {d0, d1}, [r4]<br>
+ vst1.32 {d0, d1}, [r4:16]<br>
+ vst1.32 {d0, d1}, [r4:32]<br>
+ vst1.32 {d0, d1}, [r4:64]<br>
+ vst1.32 {d0, d1}, [r4:128]<br>
+ vst1.32 {d0, d1}, [r4:256]<br>
+<br>
+@ CHECK: vst1.32 {d0, d1}, [r4] @ encoding: [0x04,0xf9,0x8f,0x0a]<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted<br>
+@ CHECK-ERRORS: vst1.32 {d0, d1}, [r4:16]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted<br>
+@ CHECK-ERRORS: vst1.32 {d0, d1}, [r4:32]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vst1.32 {d0, d1}, [r4:64] @ encoding: [0x04,0xf9,0x9f,0x0a]<br>
+@ CHECK: vst1.32 {d0, d1}, [r4:128] @ encoding: [0x04,0xf9,0xaf,0x0a]<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted<br>
+@ CHECK-ERRORS: vst1.32 {d0, d1}, [r4:256]<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vst1.32 {d0, d1}, [r4]!<br>
+ vst1.32 {d0, d1}, [r4:16]!<br>
+ vst1.32 {d0, d1}, [r4:32]!<br>
+ vst1.32 {d0, d1}, [r4:64]!<br>
+ vst1.32 {d0, d1}, [r4:128]!<br>
+ vst1.32 {d0, d1}, [r4:256]!<br>
+<br>
+@ CHECK: vst1.32 {d0, d1}, [r4]! @ encoding: [0x04,0xf9,0x8d,0x0a]<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted<br>
+@ CHECK-ERRORS: vst1.32 {d0, d1}, [r4:16]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted<br>
+@ CHECK-ERRORS: vst1.32 {d0, d1}, [r4:32]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vst1.32 {d0, d1}, [r4:64]! @ encoding: [0x04,0xf9,0x9d,0x0a]<br>
+@ CHECK: vst1.32 {d0, d1}, [r4:128]! @ encoding: [0x04,0xf9,0xad,0x0a]<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted<br>
+@ CHECK-ERRORS: vst1.32 {d0, d1}, [r4:256]!<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vst1.32 {d0, d1}, [r4], r6<br>
+ vst1.32 {d0, d1}, [r4:16], r6<br>
+ vst1.32 {d0, d1}, [r4:32], r6<br>
+ vst1.32 {d0, d1}, [r4:64], r6<br>
+ vst1.32 {d0, d1}, [r4:128], r6<br>
+ vst1.32 {d0, d1}, [r4:256], r6<br>
+<br>
+@ CHECK: vst1.32 {d0, d1}, [r4], r6 @ encoding: [0x04,0xf9,0x86,0x0a]<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted<br>
+@ CHECK-ERRORS: vst1.32 {d0, d1}, [r4:16], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted<br>
+@ CHECK-ERRORS: vst1.32 {d0, d1}, [r4:32], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vst1.32 {d0, d1}, [r4:64], r6 @ encoding: [0x04,0xf9,0x96,0x0a]<br>
+@ CHECK: vst1.32 {d0, d1}, [r4:128], r6 @ encoding: [0x04,0xf9,0xa6,0x0a]<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted<br>
+@ CHECK-ERRORS: vst1.32 {d0, d1}, [r4:256], r6<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vst1.32 {d0, d1, d2}, [r4]<br>
+ vst1.32 {d0, d1, d2}, [r4:16]<br>
+ vst1.32 {d0, d1, d2}, [r4:32]<br>
+ vst1.32 {d0, d1, d2}, [r4:64]<br>
+ vst1.32 {d0, d1, d2}, [r4:128]<br>
+ vst1.32 {d0, d1, d2}, [r4:256]<br>
+<br>
+@ CHECK: vst1.32 {d0, d1, d2}, [r4] @ encoding: [0x04,0xf9,0x8f,0x06]<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vst1.32 {d0, d1, d2}, [r4:16]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vst1.32 {d0, d1, d2}, [r4:32]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vst1.32 {d0, d1, d2}, [r4:64] @ encoding: [0x04,0xf9,0x9f,0x06]<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vst1.32 {d0, d1, d2}, [r4:128]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vst1.32 {d0, d1, d2}, [r4:256]<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vst1.32 {d0, d1, d2}, [r4]!<br>
+ vst1.32 {d0, d1, d2}, [r4:16]!<br>
+ vst1.32 {d0, d1, d2}, [r4:32]!<br>
+ vst1.32 {d0, d1, d2}, [r4:64]!<br>
+ vst1.32 {d0, d1, d2}, [r4:128]!<br>
+ vst1.32 {d0, d1, d2}, [r4:256]!<br>
+<br>
+@ CHECK: vst1.32 {d0, d1, d2}, [r4]! @ encoding: [0x04,0xf9,0x8d,0x06]<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vst1.32 {d0, d1, d2}, [r4:16]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vst1.32 {d0, d1, d2}, [r4:32]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vst1.32 {d0, d1, d2}, [r4:64]! @ encoding: [0x04,0xf9,0x9d,0x06]<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vst1.32 {d0, d1, d2}, [r4:128]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vst1.32 {d0, d1, d2}, [r4:256]!<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vst1.32 {d0, d1, d2}, [r4], r6<br>
+ vst1.32 {d0, d1, d2}, [r4:16], r6<br>
+ vst1.32 {d0, d1, d2}, [r4:32], r6<br>
+ vst1.32 {d0, d1, d2}, [r4:64], r6<br>
+ vst1.32 {d0, d1, d2}, [r4:128], r6<br>
+ vst1.32 {d0, d1, d2}, [r4:256], r6<br>
+<br>
+@ CHECK: vst1.32 {d0, d1, d2}, [r4], r6 @ encoding: [0x04,0xf9,0x86,0x06]<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vst1.32 {d0, d1, d2}, [r4:16], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vst1.32 {d0, d1, d2}, [r4:32], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vst1.32 {d0, d1, d2}, [r4:64], r6 @ encoding: [0x04,0xf9,0x96,0x06]<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vst1.32 {d0, d1, d2}, [r4:128], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vst1.32 {d0, d1, d2}, [r4:256], r6<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vst1.32 {d0, d1, d2, d3}, [r4]<br>
+ vst1.32 {d0, d1, d2, d3}, [r4:16]<br>
+ vst1.32 {d0, d1, d2, d3}, [r4:32]<br>
+ vst1.32 {d0, d1, d2, d3}, [r4:64]<br>
+ vst1.32 {d0, d1, d2, d3}, [r4:128]<br>
+ vst1.32 {d0, d1, d2, d3}, [r4:256]<br>
+<br>
+@ CHECK: vst1.32 {d0, d1, d2, d3}, [r4] @ encoding: [0x04,0xf9,0x8f,0x02]<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted<br>
+@ CHECK-ERRORS: vst1.32 {d0, d1, d2, d3}, [r4:16]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted<br>
+@ CHECK-ERRORS: vst1.32 {d0, d1, d2, d3}, [r4:32]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vst1.32 {d0, d1, d2, d3}, [r4:64] @ encoding: [0x04,0xf9,0x9f,0x02]<br>
+@ CHECK: vst1.32 {d0, d1, d2, d3}, [r4:128] @ encoding: [0x04,0xf9,0xaf,0x02]<br>
+@ CHECK: vst1.32 {d0, d1, d2, d3}, [r4:256] @ encoding: [0x04,0xf9,0xbf,0x02]<br>
+<br>
+ vst1.32 {d0, d1, d2, d3}, [r4]!<br>
+ vst1.32 {d0, d1, d2, d3}, [r4:16]!<br>
+ vst1.32 {d0, d1, d2, d3}, [r4:32]!<br>
+ vst1.32 {d0, d1, d2, d3}, [r4:64]!<br>
+ vst1.32 {d0, d1, d2, d3}, [r4:128]!<br>
+ vst1.32 {d0, d1, d2, d3}, [r4:256]!<br>
+<br>
+@ CHECK: vst1.32 {d0, d1, d2, d3}, [r4]! @ encoding: [0x04,0xf9,0x8d,0x02]<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted<br>
+@ CHECK-ERRORS: vst1.32 {d0, d1, d2, d3}, [r4:16]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted<br>
+@ CHECK-ERRORS: vst1.32 {d0, d1, d2, d3}, [r4:32]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vst1.32 {d0, d1, d2, d3}, [r4:64]! @ encoding: [0x04,0xf9,0x9d,0x02]<br>
+@ CHECK: vst1.32 {d0, d1, d2, d3}, [r4:128]! @ encoding: [0x04,0xf9,0xad,0x02]<br>
+@ CHECK: vst1.32 {d0, d1, d2, d3}, [r4:256]! @ encoding: [0x04,0xf9,0xbd,0x02]<br>
+<br>
+ vst1.32 {d0, d1, d2, d3}, [r4], r6<br>
+ vst1.32 {d0, d1, d2, d3}, [r4:16], r6<br>
+ vst1.32 {d0, d1, d2, d3}, [r4:32], r6<br>
+ vst1.32 {d0, d1, d2, d3}, [r4:64], r6<br>
+ vst1.32 {d0, d1, d2, d3}, [r4:128], r6<br>
+ vst1.32 {d0, d1, d2, d3}, [r4:256], r6<br>
+<br>
+@ CHECK: vst1.32 {d0, d1, d2, d3}, [r4], r6 @ encoding: [0x04,0xf9,0x86,0x02]<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted<br>
+@ CHECK-ERRORS: vst1.32 {d0, d1, d2, d3}, [r4:16], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted<br>
+@ CHECK-ERRORS: vst1.32 {d0, d1, d2, d3}, [r4:32], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vst1.32 {d0, d1, d2, d3}, [r4:64], r6 @ encoding: [0x04,0xf9,0x96,0x02]<br>
+@ CHECK: vst1.32 {d0, d1, d2, d3}, [r4:128], r6 @ encoding: [0x04,0xf9,0xa6,0x02]<br>
+@ CHECK: vst1.32 {d0, d1, d2, d3}, [r4:256], r6 @ encoding: [0x04,0xf9,0xb6,0x02]<br>
+<br>
+ vst1.32 {d0[1]}, [r4]<br>
+ vst1.32 {d0[1]}, [r4:16]<br>
+ vst1.32 {d0[1]}, [r4:32]<br>
+ vst1.32 {d0[1]}, [r4:64]<br>
+ vst1.32 {d0[1]}, [r4:128]<br>
+ vst1.32 {d0[1]}, [r4:256]<br>
+<br>
+@ CHECK: vst1.32 {d0[1]}, [r4] @ encoding: [0x84,0xf9,0x8f,0x08]<br>
+@ CHECK-ERRORS: error: alignment must be 32 or omitted<br>
+@ CHECK-ERRORS: vst1.32 {d0[1]}, [r4:16]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vst1.32 {d0[1]}, [r4:32] @ encoding: [0x84,0xf9,0xbf,0x08]<br>
+@ CHECK-ERRORS: error: alignment must be 32 or omitted<br>
+@ CHECK-ERRORS: vst1.32 {d0[1]}, [r4:64]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 32 or omitted<br>
+@ CHECK-ERRORS: vst1.32 {d0[1]}, [r4:128]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 32 or omitted<br>
+@ CHECK-ERRORS: vst1.32 {d0[1]}, [r4:256]<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vst1.32 {d0[1]}, [r4]!<br>
+ vst1.32 {d0[1]}, [r4:16]!<br>
+ vst1.32 {d0[1]}, [r4:32]!<br>
+ vst1.32 {d0[1]}, [r4:64]!<br>
+ vst1.32 {d0[1]}, [r4:128]!<br>
+ vst1.32 {d0[1]}, [r4:256]!<br>
+<br>
+@ CHECK: vst1.32 {d0[1]}, [r4]! @ encoding: [0x84,0xf9,0x8d,0x08]<br>
+@ CHECK-ERRORS: error: alignment must be 32 or omitted<br>
+@ CHECK-ERRORS: vst1.32 {d0[1]}, [r4:16]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vst1.32 {d0[1]}, [r4:32]! @ encoding: [0x84,0xf9,0xbd,0x08]<br>
+@ CHECK-ERRORS: error: alignment must be 32 or omitted<br>
+@ CHECK-ERRORS: vst1.32 {d0[1]}, [r4:64]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 32 or omitted<br>
+@ CHECK-ERRORS: vst1.32 {d0[1]}, [r4:128]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 32 or omitted<br>
+@ CHECK-ERRORS: vst1.32 {d0[1]}, [r4:256]!<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vst1.32 {d0[1]}, [r4], r6<br>
+ vst1.32 {d0[1]}, [r4:16], r6<br>
+ vst1.32 {d0[1]}, [r4:32], r6<br>
+ vst1.32 {d0[1]}, [r4:64], r6<br>
+ vst1.32 {d0[1]}, [r4:128], r6<br>
+ vst1.32 {d0[1]}, [r4:256], r6<br>
+<br>
+@ CHECK: vst1.32 {d0[1]}, [r4], r6 @ encoding: [0x84,0xf9,0x86,0x08]<br>
+@ CHECK-ERRORS: error: alignment must be 32 or omitted<br>
+@ CHECK-ERRORS: vst1.32 {d0[1]}, [r4:16], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vst1.32 {d0[1]}, [r4:32], r6 @ encoding: [0x84,0xf9,0xb6,0x08]<br>
+@ CHECK-ERRORS: error: alignment must be 32 or omitted<br>
+@ CHECK-ERRORS: vst1.32 {d0[1]}, [r4:64], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 32 or omitted<br>
+@ CHECK-ERRORS: vst1.32 {d0[1]}, [r4:128], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 32 or omitted<br>
+@ CHECK-ERRORS: vst1.32 {d0[1]}, [r4:256], r6<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vst1.64 {d0}, [r4]<br>
+ vst1.64 {d0}, [r4:16]<br>
+ vst1.64 {d0}, [r4:32]<br>
+ vst1.64 {d0}, [r4:64]<br>
+ vst1.64 {d0}, [r4:128]<br>
+ vst1.64 {d0}, [r4:256]<br>
+<br>
+@ CHECK: vst1.64 {d0}, [r4] @ encoding: [0x04,0xf9,0xcf,0x07]<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vst1.64 {d0}, [r4:16]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vst1.64 {d0}, [r4:32]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vst1.64 {d0}, [r4:64] @ encoding: [0x04,0xf9,0xdf,0x07]<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vst1.64 {d0}, [r4:128]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vst1.64 {d0}, [r4:256]<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vst1.64 {d0}, [r4]!<br>
+ vst1.64 {d0}, [r4:16]!<br>
+ vst1.64 {d0}, [r4:32]!<br>
+ vst1.64 {d0}, [r4:64]!<br>
+ vst1.64 {d0}, [r4:128]!<br>
+ vst1.64 {d0}, [r4:256]!<br>
+<br>
+@ CHECK: vst1.64 {d0}, [r4]! @ encoding: [0x04,0xf9,0xcd,0x07]<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vst1.64 {d0}, [r4:16]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vst1.64 {d0}, [r4:32]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vst1.64 {d0}, [r4:64]! @ encoding: [0x04,0xf9,0xdd,0x07]<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vst1.64 {d0}, [r4:128]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vst1.64 {d0}, [r4:256]!<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vst1.64 {d0}, [r4], r6<br>
+ vst1.64 {d0}, [r4:16], r6<br>
+ vst1.64 {d0}, [r4:32], r6<br>
+ vst1.64 {d0}, [r4:64], r6<br>
+ vst1.64 {d0}, [r4:128], r6<br>
+ vst1.64 {d0}, [r4:256], r6<br>
+<br>
+@ CHECK: vst1.64 {d0}, [r4], r6 @ encoding: [0x04,0xf9,0xc6,0x07]<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vst1.64 {d0}, [r4:16], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vst1.64 {d0}, [r4:32], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vst1.64 {d0}, [r4:64], r6 @ encoding: [0x04,0xf9,0xd6,0x07]<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vst1.64 {d0}, [r4:128], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vst1.64 {d0}, [r4:256], r6<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vst1.64 {d0, d1}, [r4]<br>
+ vst1.64 {d0, d1}, [r4:16]<br>
+ vst1.64 {d0, d1}, [r4:32]<br>
+ vst1.64 {d0, d1}, [r4:64]<br>
+ vst1.64 {d0, d1}, [r4:128]<br>
+ vst1.64 {d0, d1}, [r4:256]<br>
+<br>
+@ CHECK: vst1.64 {d0, d1}, [r4] @ encoding: [0x04,0xf9,0xcf,0x0a]<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted<br>
+@ CHECK-ERRORS: vst1.64 {d0, d1}, [r4:16]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted<br>
+@ CHECK-ERRORS: vst1.64 {d0, d1}, [r4:32]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vst1.64 {d0, d1}, [r4:64] @ encoding: [0x04,0xf9,0xdf,0x0a]<br>
+@ CHECK: vst1.64 {d0, d1}, [r4:128] @ encoding: [0x04,0xf9,0xef,0x0a]<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted<br>
+@ CHECK-ERRORS: vst1.64 {d0, d1}, [r4:256]<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vst1.64 {d0, d1}, [r4]!<br>
+ vst1.64 {d0, d1}, [r4:16]!<br>
+ vst1.64 {d0, d1}, [r4:32]!<br>
+ vst1.64 {d0, d1}, [r4:64]!<br>
+ vst1.64 {d0, d1}, [r4:128]!<br>
+ vst1.64 {d0, d1}, [r4:256]!<br>
+<br>
+@ CHECK: vst1.64 {d0, d1}, [r4]! @ encoding: [0x04,0xf9,0xcd,0x0a]<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted<br>
+@ CHECK-ERRORS: vst1.64 {d0, d1}, [r4:16]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted<br>
+@ CHECK-ERRORS: vst1.64 {d0, d1}, [r4:32]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vst1.64 {d0, d1}, [r4:64]! @ encoding: [0x04,0xf9,0xdd,0x0a]<br>
+@ CHECK: vst1.64 {d0, d1}, [r4:128]! @ encoding: [0x04,0xf9,0xed,0x0a]<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted<br>
+@ CHECK-ERRORS: vst1.64 {d0, d1}, [r4:256]!<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vst1.64 {d0, d1}, [r4], r6<br>
+ vst1.64 {d0, d1}, [r4:16], r6<br>
+ vst1.64 {d0, d1}, [r4:32], r6<br>
+ vst1.64 {d0, d1}, [r4:64], r6<br>
+ vst1.64 {d0, d1}, [r4:128], r6<br>
+ vst1.64 {d0, d1}, [r4:256], r6<br>
+<br>
+@ CHECK: vst1.64 {d0, d1}, [r4], r6 @ encoding: [0x04,0xf9,0xc6,0x0a]<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted<br>
+@ CHECK-ERRORS: vst1.64 {d0, d1}, [r4:16], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted<br>
+@ CHECK-ERRORS: vst1.64 {d0, d1}, [r4:32], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vst1.64 {d0, d1}, [r4:64], r6 @ encoding: [0x04,0xf9,0xd6,0x0a]<br>
+@ CHECK: vst1.64 {d0, d1}, [r4:128], r6 @ encoding: [0x04,0xf9,0xe6,0x0a]<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted<br>
+@ CHECK-ERRORS: vst1.64 {d0, d1}, [r4:256], r6<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vst1.64 {d0, d1, d2}, [r4]<br>
+ vst1.64 {d0, d1, d2}, [r4:16]<br>
+ vst1.64 {d0, d1, d2}, [r4:32]<br>
+ vst1.64 {d0, d1, d2}, [r4:64]<br>
+ vst1.64 {d0, d1, d2}, [r4:128]<br>
+ vst1.64 {d0, d1, d2}, [r4:256]<br>
+<br>
+@ CHECK: vst1.64 {d0, d1, d2}, [r4] @ encoding: [0x04,0xf9,0xcf,0x06]<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vst1.64 {d0, d1, d2}, [r4:16]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vst1.64 {d0, d1, d2}, [r4:32]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vst1.64 {d0, d1, d2}, [r4:64] @ encoding: [0x04,0xf9,0xdf,0x06]<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vst1.64 {d0, d1, d2}, [r4:128]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vst1.64 {d0, d1, d2}, [r4:256]<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vst1.64 {d0, d1, d2}, [r4]!<br>
+ vst1.64 {d0, d1, d2}, [r4:16]!<br>
+ vst1.64 {d0, d1, d2}, [r4:32]!<br>
+ vst1.64 {d0, d1, d2}, [r4:64]!<br>
+ vst1.64 {d0, d1, d2}, [r4:128]!<br>
+ vst1.64 {d0, d1, d2}, [r4:256]!<br>
+<br>
+@ CHECK: vst1.64 {d0, d1, d2}, [r4]! @ encoding: [0x04,0xf9,0xcd,0x06]<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vst1.64 {d0, d1, d2}, [r4:16]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vst1.64 {d0, d1, d2}, [r4:32]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vst1.64 {d0, d1, d2}, [r4:64]! @ encoding: [0x04,0xf9,0xdd,0x06]<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vst1.64 {d0, d1, d2}, [r4:128]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vst1.64 {d0, d1, d2}, [r4:256]!<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vst1.64 {d0, d1, d2}, [r4], r6<br>
+ vst1.64 {d0, d1, d2}, [r4:16], r6<br>
+ vst1.64 {d0, d1, d2}, [r4:32], r6<br>
+ vst1.64 {d0, d1, d2}, [r4:64], r6<br>
+ vst1.64 {d0, d1, d2}, [r4:128], r6<br>
+ vst1.64 {d0, d1, d2}, [r4:256], r6<br>
+<br>
+@ CHECK: vst1.64 {d0, d1, d2}, [r4], r6 @ encoding: [0x04,0xf9,0xc6,0x06]<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vst1.64 {d0, d1, d2}, [r4:16], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vst1.64 {d0, d1, d2}, [r4:32], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vst1.64 {d0, d1, d2}, [r4:64], r6 @ encoding: [0x04,0xf9,0xd6,0x06]<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vst1.64 {d0, d1, d2}, [r4:128], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vst1.64 {d0, d1, d2}, [r4:256], r6<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vst1.64 {d0, d1, d2, d3}, [r4]<br>
+ vst1.64 {d0, d1, d2, d3}, [r4:16]<br>
+ vst1.64 {d0, d1, d2, d3}, [r4:32]<br>
+ vst1.64 {d0, d1, d2, d3}, [r4:64]<br>
+ vst1.64 {d0, d1, d2, d3}, [r4:128]<br>
+ vst1.64 {d0, d1, d2, d3}, [r4:256]<br>
+<br>
+@ CHECK: vst1.64 {d0, d1, d2, d3}, [r4] @ encoding: [0x04,0xf9,0xcf,0x02]<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted<br>
+@ CHECK-ERRORS: vst1.64 {d0, d1, d2, d3}, [r4:16]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted<br>
+@ CHECK-ERRORS: vst1.64 {d0, d1, d2, d3}, [r4:32]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vst1.64 {d0, d1, d2, d3}, [r4:64] @ encoding: [0x04,0xf9,0xdf,0x02]<br>
+@ CHECK: vst1.64 {d0, d1, d2, d3}, [r4:128] @ encoding: [0x04,0xf9,0xef,0x02]<br>
+@ CHECK: vst1.64 {d0, d1, d2, d3}, [r4:256] @ encoding: [0x04,0xf9,0xff,0x02]<br>
+<br>
+ vst1.64 {d0, d1, d2, d3}, [r4]!<br>
+ vst1.64 {d0, d1, d2, d3}, [r4:16]!<br>
+ vst1.64 {d0, d1, d2, d3}, [r4:32]!<br>
+ vst1.64 {d0, d1, d2, d3}, [r4:64]!<br>
+ vst1.64 {d0, d1, d2, d3}, [r4:128]!<br>
+ vst1.64 {d0, d1, d2, d3}, [r4:256]!<br>
+<br>
+@ CHECK: vst1.64 {d0, d1, d2, d3}, [r4]! @ encoding: [0x04,0xf9,0xcd,0x02]<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted<br>
+@ CHECK-ERRORS: vst1.64 {d0, d1, d2, d3}, [r4:16]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted<br>
+@ CHECK-ERRORS: vst1.64 {d0, d1, d2, d3}, [r4:32]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vst1.64 {d0, d1, d2, d3}, [r4:64]! @ encoding: [0x04,0xf9,0xdd,0x02]<br>
+@ CHECK: vst1.64 {d0, d1, d2, d3}, [r4:128]! @ encoding: [0x04,0xf9,0xed,0x02]<br>
+@ CHECK: vst1.64 {d0, d1, d2, d3}, [r4:256]! @ encoding: [0x04,0xf9,0xfd,0x02]<br>
+<br>
+ vst1.64 {d0, d1, d2, d3}, [r4], r6<br>
+ vst1.64 {d0, d1, d2, d3}, [r4:16], r6<br>
+ vst1.64 {d0, d1, d2, d3}, [r4:32], r6<br>
+ vst1.64 {d0, d1, d2, d3}, [r4:64], r6<br>
+ vst1.64 {d0, d1, d2, d3}, [r4:128], r6<br>
+ vst1.64 {d0, d1, d2, d3}, [r4:256], r6<br>
+<br>
+@ CHECK: vst1.64 {d0, d1, d2, d3}, [r4], r6 @ encoding: [0x04,0xf9,0xc6,0x02]<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted<br>
+@ CHECK-ERRORS: vst1.64 {d0, d1, d2, d3}, [r4:16], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted<br>
+@ CHECK-ERRORS: vst1.64 {d0, d1, d2, d3}, [r4:32], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vst1.64 {d0, d1, d2, d3}, [r4:64], r6 @ encoding: [0x04,0xf9,0xd6,0x02]<br>
+@ CHECK: vst1.64 {d0, d1, d2, d3}, [r4:128], r6 @ encoding: [0x04,0xf9,0xe6,0x02]<br>
+@ CHECK: vst1.64 {d0, d1, d2, d3}, [r4:256], r6 @ encoding: [0x04,0xf9,0xf6,0x02]<br>
+<br>
+ vst2.8 {d0, d1}, [r4]<br>
+ vst2.8 {d0, d1}, [r4:16]<br>
+ vst2.8 {d0, d1}, [r4:32]<br>
+ vst2.8 {d0, d1}, [r4:64]<br>
+ vst2.8 {d0, d1}, [r4:128]<br>
+ vst2.8 {d0, d1}, [r4:256]<br>
+<br>
+@ CHECK: vst2.8 {d0, d1}, [r4] @ encoding: [0x04,0xf9,0x0f,0x08]<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted<br>
+@ CHECK-ERRORS: vst2.8 {d0, d1}, [r4:16]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted<br>
+@ CHECK-ERRORS: vst2.8 {d0, d1}, [r4:32]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vst2.8 {d0, d1}, [r4:64] @ encoding: [0x04,0xf9,0x1f,0x08]<br>
+@ CHECK: vst2.8 {d0, d1}, [r4:128] @ encoding: [0x04,0xf9,0x2f,0x08]<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted<br>
+@ CHECK-ERRORS: vst2.8 {d0, d1}, [r4:256]<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vst2.8 {d0, d1}, [r4]!<br>
+ vst2.8 {d0, d1}, [r4:16]!<br>
+ vst2.8 {d0, d1}, [r4:32]!<br>
+ vst2.8 {d0, d1}, [r4:64]!<br>
+ vst2.8 {d0, d1}, [r4:128]!<br>
+ vst2.8 {d0, d1}, [r4:256]!<br>
+<br>
+@ CHECK: vst2.8 {d0, d1}, [r4]! @ encoding: [0x04,0xf9,0x0d,0x08]<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted<br>
+@ CHECK-ERRORS: vst2.8 {d0, d1}, [r4:16]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted<br>
+@ CHECK-ERRORS: vst2.8 {d0, d1}, [r4:32]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vst2.8 {d0, d1}, [r4:64]! @ encoding: [0x04,0xf9,0x1d,0x08]<br>
+@ CHECK: vst2.8 {d0, d1}, [r4:128]! @ encoding: [0x04,0xf9,0x2d,0x08]<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted<br>
+@ CHECK-ERRORS: vst2.8 {d0, d1}, [r4:256]!<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vst2.8 {d0, d1}, [r4], r6<br>
+ vst2.8 {d0, d1}, [r4:16], r6<br>
+ vst2.8 {d0, d1}, [r4:32], r6<br>
+ vst2.8 {d0, d1}, [r4:64], r6<br>
+ vst2.8 {d0, d1}, [r4:128], r6<br>
+ vst2.8 {d0, d1}, [r4:256], r6<br>
+<br>
+@ CHECK: vst2.8 {d0, d1}, [r4], r6 @ encoding: [0x04,0xf9,0x06,0x08]<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted<br>
+@ CHECK-ERRORS: vst2.8 {d0, d1}, [r4:16], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted<br>
+@ CHECK-ERRORS: vst2.8 {d0, d1}, [r4:32], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vst2.8 {d0, d1}, [r4:64], r6 @ encoding: [0x04,0xf9,0x16,0x08]<br>
+@ CHECK: vst2.8 {d0, d1}, [r4:128], r6 @ encoding: [0x04,0xf9,0x26,0x08]<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted<br>
+@ CHECK-ERRORS: vst2.8 {d0, d1}, [r4:256], r6<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vst2.8 {d0, d2}, [r4]<br>
+ vst2.8 {d0, d2}, [r4:16]<br>
+ vst2.8 {d0, d2}, [r4:32]<br>
+ vst2.8 {d0, d2}, [r4:64]<br>
+ vst2.8 {d0, d2}, [r4:128]<br>
+ vst2.8 {d0, d2}, [r4:256]<br>
+<br>
+@ CHECK: vst2.8 {d0, d2}, [r4] @ encoding: [0x04,0xf9,0x0f,0x09]<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted<br>
+@ CHECK-ERRORS: vst2.8 {d0, d2}, [r4:16]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted<br>
+@ CHECK-ERRORS: vst2.8 {d0, d2}, [r4:32]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vst2.8 {d0, d2}, [r4:64] @ encoding: [0x04,0xf9,0x1f,0x09]<br>
+@ CHECK: vst2.8 {d0, d2}, [r4:128] @ encoding: [0x04,0xf9,0x2f,0x09]<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted<br>
+@ CHECK-ERRORS: vst2.8 {d0, d2}, [r4:256]<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vst2.8 {d0, d2}, [r4]!<br>
+ vst2.8 {d0, d2}, [r4:16]!<br>
+ vst2.8 {d0, d2}, [r4:32]!<br>
+ vst2.8 {d0, d2}, [r4:64]!<br>
+ vst2.8 {d0, d2}, [r4:128]!<br>
+ vst2.8 {d0, d2}, [r4:256]!<br>
+<br>
+@ CHECK: vst2.8 {d0, d2}, [r4]! @ encoding: [0x04,0xf9,0x0d,0x09]<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted<br>
+@ CHECK-ERRORS: vst2.8 {d0, d2}, [r4:16]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted<br>
+@ CHECK-ERRORS: vst2.8 {d0, d2}, [r4:32]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vst2.8 {d0, d2}, [r4:64]! @ encoding: [0x04,0xf9,0x1d,0x09]<br>
+@ CHECK: vst2.8 {d0, d2}, [r4:128]! @ encoding: [0x04,0xf9,0x2d,0x09]<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted<br>
+@ CHECK-ERRORS: vst2.8 {d0, d2}, [r4:256]!<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vst2.8 {d0, d2}, [r4], r6<br>
+ vst2.8 {d0, d2}, [r4:16], r6<br>
+ vst2.8 {d0, d2}, [r4:32], r6<br>
+ vst2.8 {d0, d2}, [r4:64], r6<br>
+ vst2.8 {d0, d2}, [r4:128], r6<br>
+ vst2.8 {d0, d2}, [r4:256], r6<br>
+<br>
+@ CHECK: vst2.8 {d0, d2}, [r4], r6 @ encoding: [0x04,0xf9,0x06,0x09]<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted<br>
+@ CHECK-ERRORS: vst2.8 {d0, d2}, [r4:16], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted<br>
+@ CHECK-ERRORS: vst2.8 {d0, d2}, [r4:32], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vst2.8 {d0, d2}, [r4:64], r6 @ encoding: [0x04,0xf9,0x16,0x09]<br>
+@ CHECK: vst2.8 {d0, d2}, [r4:128], r6 @ encoding: [0x04,0xf9,0x26,0x09]<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted<br>
+@ CHECK-ERRORS: vst2.8 {d0, d2}, [r4:256], r6<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vst2.8 {d0, d1, d2, d3}, [r4]<br>
+ vst2.8 {d0, d1, d2, d3}, [r4:16]<br>
+ vst2.8 {d0, d1, d2, d3}, [r4:32]<br>
+ vst2.8 {d0, d1, d2, d3}, [r4:64]<br>
+ vst2.8 {d0, d1, d2, d3}, [r4:128]<br>
+ vst2.8 {d0, d1, d2, d3}, [r4:256]<br>
+<br>
+@ CHECK: vst2.8 {d0, d1, d2, d3}, [r4] @ encoding: [0x04,0xf9,0x0f,0x03]<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted<br>
+@ CHECK-ERRORS: vst2.8 {d0, d1, d2, d3}, [r4:16]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted<br>
+@ CHECK-ERRORS: vst2.8 {d0, d1, d2, d3}, [r4:32]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vst2.8 {d0, d1, d2, d3}, [r4:64] @ encoding: [0x04,0xf9,0x1f,0x03]<br>
+@ CHECK: vst2.8 {d0, d1, d2, d3}, [r4:128] @ encoding: [0x04,0xf9,0x2f,0x03]<br>
+@ CHECK: vst2.8 {d0, d1, d2, d3}, [r4:256] @ encoding: [0x04,0xf9,0x3f,0x03]<br>
+<br>
+ vst2.8 {d0, d1, d2, d3}, [r4]!<br>
+ vst2.8 {d0, d1, d2, d3}, [r4:16]!<br>
+ vst2.8 {d0, d1, d2, d3}, [r4:32]!<br>
+ vst2.8 {d0, d1, d2, d3}, [r4:64]!<br>
+ vst2.8 {d0, d1, d2, d3}, [r4:128]!<br>
+ vst2.8 {d0, d1, d2, d3}, [r4:256]!<br>
+<br>
+@ CHECK: vst2.8 {d0, d1, d2, d3}, [r4]! @ encoding: [0x04,0xf9,0x0d,0x03]<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted<br>
+@ CHECK-ERRORS: vst2.8 {d0, d1, d2, d3}, [r4:16]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted<br>
+@ CHECK-ERRORS: vst2.8 {d0, d1, d2, d3}, [r4:32]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vst2.8 {d0, d1, d2, d3}, [r4:64]! @ encoding: [0x04,0xf9,0x1d,0x03]<br>
+@ CHECK: vst2.8 {d0, d1, d2, d3}, [r4:128]! @ encoding: [0x04,0xf9,0x2d,0x03]<br>
+@ CHECK: vst2.8 {d0, d1, d2, d3}, [r4:256]! @ encoding: [0x04,0xf9,0x3d,0x03]<br>
+<br>
+ vst2.8 {d0, d1, d2, d3}, [r4], r6<br>
+ vst2.8 {d0, d1, d2, d3}, [r4:16], r6<br>
+ vst2.8 {d0, d1, d2, d3}, [r4:32], r6<br>
+ vst2.8 {d0, d1, d2, d3}, [r4:64], r6<br>
+ vst2.8 {d0, d1, d2, d3}, [r4:128], r6<br>
+ vst2.8 {d0, d1, d2, d3}, [r4:256], r6<br>
+<br>
+@ CHECK: vst2.8 {d0, d1, d2, d3}, [r4], r6 @ encoding: [0x04,0xf9,0x06,0x03]<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted<br>
+@ CHECK-ERRORS: vst2.8 {d0, d1, d2, d3}, [r4:16], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted<br>
+@ CHECK-ERRORS: vst2.8 {d0, d1, d2, d3}, [r4:32], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vst2.8 {d0, d1, d2, d3}, [r4:64], r6 @ encoding: [0x04,0xf9,0x16,0x03]<br>
+@ CHECK: vst2.8 {d0, d1, d2, d3}, [r4:128], r6 @ encoding: [0x04,0xf9,0x26,0x03]<br>
+@ CHECK: vst2.8 {d0, d1, d2, d3}, [r4:256], r6 @ encoding: [0x04,0xf9,0x36,0x03]<br>
+<br>
+ vst2.8 {d0[2], d1[2]}, [r4]<br>
+ vst2.8 {d0[2], d1[2]}, [r4:16]<br>
+ vst2.8 {d0[2], d1[2]}, [r4:32]<br>
+ vst2.8 {d0[2], d1[2]}, [r4:64]<br>
+ vst2.8 {d0[2], d1[2]}, [r4:128]<br>
+ vst2.8 {d0[2], d1[2]}, [r4:256]<br>
+<br>
+@ CHECK: vst2.8 {d0[2], d1[2]}, [r4] @ encoding: [0x84,0xf9,0x4f,0x01]<br>
+@ CHECK: vst2.8 {d0[2], d1[2]}, [r4:16] @ encoding: [0x84,0xf9,0x5f,0x01]<br>
+@ CHECK-ERRORS: error: alignment must be 16 or omitted<br>
+@ CHECK-ERRORS: vst2.8 {d0[2], d1[2]}, [r4:32]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 16 or omitted<br>
+@ CHECK-ERRORS: vst2.8 {d0[2], d1[2]}, [r4:64]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 16 or omitted<br>
+@ CHECK-ERRORS: vst2.8 {d0[2], d1[2]}, [r4:128]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 16 or omitted<br>
+@ CHECK-ERRORS: vst2.8 {d0[2], d1[2]}, [r4:256]<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vst2.8 {d0[2], d1[2]}, [r4]!<br>
+ vst2.8 {d0[2], d1[2]}, [r4:16]!<br>
+ vst2.8 {d0[2], d1[2]}, [r4:32]!<br>
+ vst2.8 {d0[2], d1[2]}, [r4:64]!<br>
+ vst2.8 {d0[2], d1[2]}, [r4:128]!<br>
+ vst2.8 {d0[2], d1[2]}, [r4:256]!<br>
+<br>
+@ CHECK: vst2.8 {d0[2], d1[2]}, [r4]! @ encoding: [0x84,0xf9,0x4d,0x01]<br>
+@ CHECK: vst2.8 {d0[2], d1[2]}, [r4:16]! @ encoding: [0x84,0xf9,0x5d,0x01]<br>
+@ CHECK-ERRORS: error: alignment must be 16 or omitted<br>
+@ CHECK-ERRORS: vst2.8 {d0[2], d1[2]}, [r4:32]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 16 or omitted<br>
+@ CHECK-ERRORS: vst2.8 {d0[2], d1[2]}, [r4:64]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 16 or omitted<br>
+@ CHECK-ERRORS: vst2.8 {d0[2], d1[2]}, [r4:128]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 16 or omitted<br>
+@ CHECK-ERRORS: vst2.8 {d0[2], d1[2]}, [r4:256]!<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vst2.8 {d0[2], d1[2]}, [r4], r6<br>
+ vst2.8 {d0[2], d1[2]}, [r4:16], r6<br>
+ vst2.8 {d0[2], d1[2]}, [r4:32], r6<br>
+ vst2.8 {d0[2], d1[2]}, [r4:64], r6<br>
+ vst2.8 {d0[2], d1[2]}, [r4:128], r6<br>
+ vst2.8 {d0[2], d1[2]}, [r4:256], r6<br>
+<br>
+@ CHECK: vst2.8 {d0[2], d1[2]}, [r4], r6 @ encoding: [0x84,0xf9,0x46,0x01]<br>
+@ CHECK: vst2.8 {d0[2], d1[2]}, [r4:16], r6 @ encoding: [0x84,0xf9,0x56,0x01]<br>
+@ CHECK-ERRORS: error: alignment must be 16 or omitted<br>
+@ CHECK-ERRORS: vst2.8 {d0[2], d1[2]}, [r4:32], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 16 or omitted<br>
+@ CHECK-ERRORS: vst2.8 {d0[2], d1[2]}, [r4:64], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 16 or omitted<br>
+@ CHECK-ERRORS: vst2.8 {d0[2], d1[2]}, [r4:128], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 16 or omitted<br>
+@ CHECK-ERRORS: vst2.8 {d0[2], d1[2]}, [r4:256], r6<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vst2.32 {d0, d1}, [r4]<br>
+ vst2.32 {d0, d1}, [r4:16]<br>
+ vst2.32 {d0, d1}, [r4:32]<br>
+ vst2.32 {d0, d1}, [r4:64]<br>
+ vst2.32 {d0, d1}, [r4:128]<br>
+ vst2.32 {d0, d1}, [r4:256]<br>
+<br>
+@ CHECK: vst2.32 {d0, d1}, [r4] @ encoding: [0x04,0xf9,0x8f,0x08]<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted<br>
+@ CHECK-ERRORS: vst2.32 {d0, d1}, [r4:16]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted<br>
+@ CHECK-ERRORS: vst2.32 {d0, d1}, [r4:32]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vst2.32 {d0, d1}, [r4:64] @ encoding: [0x04,0xf9,0x9f,0x08]<br>
+@ CHECK: vst2.32 {d0, d1}, [r4:128] @ encoding: [0x04,0xf9,0xaf,0x08]<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted<br>
+@ CHECK-ERRORS: vst2.32 {d0, d1}, [r4:256]<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vst2.32 {d0, d1}, [r4]!<br>
+ vst2.32 {d0, d1}, [r4:16]!<br>
+ vst2.32 {d0, d1}, [r4:32]!<br>
+ vst2.32 {d0, d1}, [r4:64]!<br>
+ vst2.32 {d0, d1}, [r4:128]!<br>
+ vst2.32 {d0, d1}, [r4:256]!<br>
+<br>
+@ CHECK: vst2.32 {d0, d1}, [r4]! @ encoding: [0x04,0xf9,0x8d,0x08]<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted<br>
+@ CHECK-ERRORS: vst2.32 {d0, d1}, [r4:16]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted<br>
+@ CHECK-ERRORS: vst2.32 {d0, d1}, [r4:32]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vst2.32 {d0, d1}, [r4:64]! @ encoding: [0x04,0xf9,0x9d,0x08]<br>
+@ CHECK: vst2.32 {d0, d1}, [r4:128]! @ encoding: [0x04,0xf9,0xad,0x08]<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted<br>
+@ CHECK-ERRORS: vst2.32 {d0, d1}, [r4:256]!<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vst2.32 {d0, d1}, [r4], r6<br>
+ vst2.32 {d0, d1}, [r4:16], r6<br>
+ vst2.32 {d0, d1}, [r4:32], r6<br>
+ vst2.32 {d0, d1}, [r4:64], r6<br>
+ vst2.32 {d0, d1}, [r4:128], r6<br>
+ vst2.32 {d0, d1}, [r4:256], r6<br>
+<br>
+@ CHECK: vst2.32 {d0, d1}, [r4], r6 @ encoding: [0x04,0xf9,0x86,0x08]<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted<br>
+@ CHECK-ERRORS: vst2.32 {d0, d1}, [r4:16], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted<br>
+@ CHECK-ERRORS: vst2.32 {d0, d1}, [r4:32], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vst2.32 {d0, d1}, [r4:64], r6 @ encoding: [0x04,0xf9,0x96,0x08]<br>
+@ CHECK: vst2.32 {d0, d1}, [r4:128], r6 @ encoding: [0x04,0xf9,0xa6,0x08]<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted<br>
+@ CHECK-ERRORS: vst2.32 {d0, d1}, [r4:256], r6<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vst2.32 {d0, d2}, [r4]<br>
+ vst2.32 {d0, d2}, [r4:16]<br>
+ vst2.32 {d0, d2}, [r4:32]<br>
+ vst2.32 {d0, d2}, [r4:64]<br>
+ vst2.32 {d0, d2}, [r4:128]<br>
+ vst2.32 {d0, d2}, [r4:256]<br>
+<br>
+@ CHECK: vst2.32 {d0, d2}, [r4] @ encoding: [0x04,0xf9,0x8f,0x09]<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted<br>
+@ CHECK-ERRORS: vst2.32 {d0, d2}, [r4:16]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted<br>
+@ CHECK-ERRORS: vst2.32 {d0, d2}, [r4:32]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vst2.32 {d0, d2}, [r4:64] @ encoding: [0x04,0xf9,0x9f,0x09]<br>
+@ CHECK: vst2.32 {d0, d2}, [r4:128] @ encoding: [0x04,0xf9,0xaf,0x09]<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted<br>
+@ CHECK-ERRORS: vst2.32 {d0, d2}, [r4:256]<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vst2.32 {d0, d2}, [r4]!<br>
+ vst2.32 {d0, d2}, [r4:16]!<br>
+ vst2.32 {d0, d2}, [r4:32]!<br>
+ vst2.32 {d0, d2}, [r4:64]!<br>
+ vst2.32 {d0, d2}, [r4:128]!<br>
+ vst2.32 {d0, d2}, [r4:256]!<br>
+<br>
+@ CHECK: vst2.32 {d0, d2}, [r4]! @ encoding: [0x04,0xf9,0x8d,0x09]<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted<br>
+@ CHECK-ERRORS: vst2.32 {d0, d2}, [r4:16]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted<br>
+@ CHECK-ERRORS: vst2.32 {d0, d2}, [r4:32]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vst2.32 {d0, d2}, [r4:64]! @ encoding: [0x04,0xf9,0x9d,0x09]<br>
+@ CHECK: vst2.32 {d0, d2}, [r4:128]! @ encoding: [0x04,0xf9,0xad,0x09]<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted<br>
+@ CHECK-ERRORS: vst2.32 {d0, d2}, [r4:256]!<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vst2.32 {d0, d2}, [r4], r6<br>
+ vst2.32 {d0, d2}, [r4:16], r6<br>
+ vst2.32 {d0, d2}, [r4:32], r6<br>
+ vst2.32 {d0, d2}, [r4:64], r6<br>
+ vst2.32 {d0, d2}, [r4:128], r6<br>
+ vst2.32 {d0, d2}, [r4:256], r6<br>
+<br>
+@ CHECK: vst2.32 {d0, d2}, [r4], r6 @ encoding: [0x04,0xf9,0x86,0x09]<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted<br>
+@ CHECK-ERRORS: vst2.32 {d0, d2}, [r4:16], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted<br>
+@ CHECK-ERRORS: vst2.32 {d0, d2}, [r4:32], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vst2.32 {d0, d2}, [r4:64], r6 @ encoding: [0x04,0xf9,0x96,0x09]<br>
+@ CHECK: vst2.32 {d0, d2}, [r4:128], r6 @ encoding: [0x04,0xf9,0xa6,0x09]<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted<br>
+@ CHECK-ERRORS: vst2.32 {d0, d2}, [r4:256], r6<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vst2.32 {d0, d1, d2, d3}, [r4]<br>
+ vst2.32 {d0, d1, d2, d3}, [r4:16]<br>
+ vst2.32 {d0, d1, d2, d3}, [r4:32]<br>
+ vst2.32 {d0, d1, d2, d3}, [r4:64]<br>
+ vst2.32 {d0, d1, d2, d3}, [r4:128]<br>
+ vst2.32 {d0, d1, d2, d3}, [r4:256]<br>
+<br>
+@ CHECK: vst2.32 {d0, d1, d2, d3}, [r4] @ encoding: [0x04,0xf9,0x8f,0x03]<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted<br>
+@ CHECK-ERRORS: vst2.32 {d0, d1, d2, d3}, [r4:16]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted<br>
+@ CHECK-ERRORS: vst2.32 {d0, d1, d2, d3}, [r4:32]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vst2.32 {d0, d1, d2, d3}, [r4:64] @ encoding: [0x04,0xf9,0x9f,0x03]<br>
+@ CHECK: vst2.32 {d0, d1, d2, d3}, [r4:128] @ encoding: [0x04,0xf9,0xaf,0x03]<br>
+@ CHECK: vst2.32 {d0, d1, d2, d3}, [r4:256] @ encoding: [0x04,0xf9,0xbf,0x03]<br>
+<br>
+ vst2.32 {d0, d1, d2, d3}, [r4]!<br>
+ vst2.32 {d0, d1, d2, d3}, [r4:16]!<br>
+ vst2.32 {d0, d1, d2, d3}, [r4:32]!<br>
+ vst2.32 {d0, d1, d2, d3}, [r4:64]!<br>
+ vst2.32 {d0, d1, d2, d3}, [r4:128]!<br>
+ vst2.32 {d0, d1, d2, d3}, [r4:256]!<br>
+<br>
+@ CHECK: vst2.32 {d0, d1, d2, d3}, [r4]! @ encoding: [0x04,0xf9,0x8d,0x03]<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted<br>
+@ CHECK-ERRORS: vst2.32 {d0, d1, d2, d3}, [r4:16]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted<br>
+@ CHECK-ERRORS: vst2.32 {d0, d1, d2, d3}, [r4:32]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vst2.32 {d0, d1, d2, d3}, [r4:64]! @ encoding: [0x04,0xf9,0x9d,0x03]<br>
+@ CHECK: vst2.32 {d0, d1, d2, d3}, [r4:128]! @ encoding: [0x04,0xf9,0xad,0x03]<br>
+@ CHECK: vst2.32 {d0, d1, d2, d3}, [r4:256]! @ encoding: [0x04,0xf9,0xbd,0x03]<br>
+<br>
+ vst2.32 {d0, d1, d2, d3}, [r4], r6<br>
+ vst2.32 {d0, d1, d2, d3}, [r4:16], r6<br>
+ vst2.32 {d0, d1, d2, d3}, [r4:32], r6<br>
+ vst2.32 {d0, d1, d2, d3}, [r4:64], r6<br>
+ vst2.32 {d0, d1, d2, d3}, [r4:128], r6<br>
+ vst2.32 {d0, d1, d2, d3}, [r4:256], r6<br>
+<br>
+@ CHECK: vst2.32 {d0, d1, d2, d3}, [r4], r6 @ encoding: [0x04,0xf9,0x86,0x03]<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted<br>
+@ CHECK-ERRORS: vst2.32 {d0, d1, d2, d3}, [r4:16], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted<br>
+@ CHECK-ERRORS: vst2.32 {d0, d1, d2, d3}, [r4:32], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vst2.32 {d0, d1, d2, d3}, [r4:64], r6 @ encoding: [0x04,0xf9,0x96,0x03]<br>
+@ CHECK: vst2.32 {d0, d1, d2, d3}, [r4:128], r6 @ encoding: [0x04,0xf9,0xa6,0x03]<br>
+@ CHECK: vst2.32 {d0, d1, d2, d3}, [r4:256], r6 @ encoding: [0x04,0xf9,0xb6,0x03]<br>
+<br>
+ vst2.32 {d0[1], d1[1]}, [r4]<br>
+ vst2.32 {d0[1], d1[1]}, [r4:16]<br>
+ vst2.32 {d0[1], d1[1]}, [r4:32]<br>
+ vst2.32 {d0[1], d1[1]}, [r4:64]<br>
+ vst2.32 {d0[1], d1[1]}, [r4:128]<br>
+ vst2.32 {d0[1], d1[1]}, [r4:256]<br>
+<br>
+@ CHECK: vst2.32 {d0[1], d1[1]}, [r4] @ encoding: [0x84,0xf9,0x8f,0x09]<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vst2.32 {d0[1], d1[1]}, [r4:16]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vst2.32 {d0[1], d1[1]}, [r4:32]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vst2.32 {d0[1], d1[1]}, [r4:64] @ encoding: [0x84,0xf9,0x9f,0x09]<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vst2.32 {d0[1], d1[1]}, [r4:128]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vst2.32 {d0[1], d1[1]}, [r4:256]<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vst2.32 {d0[1], d1[1]}, [r4]!<br>
+ vst2.32 {d0[1], d1[1]}, [r4:16]!<br>
+ vst2.32 {d0[1], d1[1]}, [r4:32]!<br>
+ vst2.32 {d0[1], d1[1]}, [r4:64]!<br>
+ vst2.32 {d0[1], d1[1]}, [r4:128]!<br>
+ vst2.32 {d0[1], d1[1]}, [r4:256]!<br>
+<br>
+@ CHECK: vst2.32 {d0[1], d1[1]}, [r4]! @ encoding: [0x84,0xf9,0x8d,0x09]<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vst2.32 {d0[1], d1[1]}, [r4:16]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vst2.32 {d0[1], d1[1]}, [r4:32]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vst2.32 {d0[1], d1[1]}, [r4:64]! @ encoding: [0x84,0xf9,0x9d,0x09]<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vst2.32 {d0[1], d1[1]}, [r4:128]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vst2.32 {d0[1], d1[1]}, [r4:256]!<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vst2.32 {d0[1], d1[1]}, [r4], r6<br>
+ vst2.32 {d0[1], d1[1]}, [r4:16], r6<br>
+ vst2.32 {d0[1], d1[1]}, [r4:32], r6<br>
+ vst2.32 {d0[1], d1[1]}, [r4:64], r6<br>
+ vst2.32 {d0[1], d1[1]}, [r4:128], r6<br>
+ vst2.32 {d0[1], d1[1]}, [r4:256], r6<br>
+<br>
+@ CHECK: vst2.32 {d0[1], d1[1]}, [r4], r6 @ encoding: [0x84,0xf9,0x86,0x09]<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vst2.32 {d0[1], d1[1]}, [r4:16], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vst2.32 {d0[1], d1[1]}, [r4:32], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vst2.32 {d0[1], d1[1]}, [r4:64], r6 @ encoding: [0x84,0xf9,0x96,0x09]<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vst2.32 {d0[1], d1[1]}, [r4:128], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vst2.32 {d0[1], d1[1]}, [r4:256], r6<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vst2.32 {d0[1], d2[1]}, [r4]<br>
+ vst2.32 {d0[1], d2[1]}, [r4:16]<br>
+ vst2.32 {d0[1], d2[1]}, [r4:32]<br>
+ vst2.32 {d0[1], d2[1]}, [r4:64]<br>
+ vst2.32 {d0[1], d2[1]}, [r4:128]<br>
+ vst2.32 {d0[1], d2[1]}, [r4:256]<br>
+<br>
+@ CHECK: vst2.32 {d0[1], d2[1]}, [r4] @ encoding: [0x84,0xf9,0xcf,0x09]<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vst2.32 {d0[1], d2[1]}, [r4:16]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vst2.32 {d0[1], d2[1]}, [r4:32]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vst2.32 {d0[1], d2[1]}, [r4:64] @ encoding: [0x84,0xf9,0xdf,0x09]<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vst2.32 {d0[1], d2[1]}, [r4:128]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vst2.32 {d0[1], d2[1]}, [r4:256]<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vst2.32 {d0[1], d2[1]}, [r4]!<br>
+ vst2.32 {d0[1], d2[1]}, [r4:16]!<br>
+ vst2.32 {d0[1], d2[1]}, [r4:32]!<br>
+ vst2.32 {d0[1], d2[1]}, [r4:64]!<br>
+ vst2.32 {d0[1], d2[1]}, [r4:128]!<br>
+ vst2.32 {d0[1], d2[1]}, [r4:256]!<br>
+<br>
+@ CHECK: vst2.32 {d0[1], d2[1]}, [r4]! @ encoding: [0x84,0xf9,0xcd,0x09]<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vst2.32 {d0[1], d2[1]}, [r4:16]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vst2.32 {d0[1], d2[1]}, [r4:32]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vst2.32 {d0[1], d2[1]}, [r4:64]! @ encoding: [0x84,0xf9,0xdd,0x09]<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vst2.32 {d0[1], d2[1]}, [r4:128]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vst2.32 {d0[1], d2[1]}, [r4:256]!<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vst2.32 {d0[1], d2[1]}, [r4], r6<br>
+ vst2.32 {d0[1], d2[1]}, [r4:16], r6<br>
+ vst2.32 {d0[1], d2[1]}, [r4:32], r6<br>
+ vst2.32 {d0[1], d2[1]}, [r4:64], r6<br>
+ vst2.32 {d0[1], d2[1]}, [r4:128], r6<br>
+ vst2.32 {d0[1], d2[1]}, [r4:256], r6<br>
+<br>
+@ CHECK: vst2.32 {d0[1], d2[1]}, [r4], r6 @ encoding: [0x84,0xf9,0xc6,0x09]<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vst2.32 {d0[1], d2[1]}, [r4:16], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vst2.32 {d0[1], d2[1]}, [r4:32], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vst2.32 {d0[1], d2[1]}, [r4:64], r6 @ encoding: [0x84,0xf9,0xd6,0x09]<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vst2.32 {d0[1], d2[1]}, [r4:128], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vst2.32 {d0[1], d2[1]}, [r4:256], r6<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vst3.8 {d0, d1, d2}, [r4]<br>
+ vst3.8 {d0, d1, d2}, [r4:16]<br>
+ vst3.8 {d0, d1, d2}, [r4:32]<br>
+ vst3.8 {d0, d1, d2}, [r4:64]<br>
+ vst3.8 {d0, d1, d2}, [r4:128]<br>
+ vst3.8 {d0, d1, d2}, [r4:256]<br>
+<br>
+@ CHECK: vst3.8 {d0, d1, d2}, [r4] @ encoding: [0x04,0xf9,0x0f,0x04]<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vst3.8 {d0, d1, d2}, [r4:16]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vst3.8 {d0, d1, d2}, [r4:32]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vst3.8 {d0, d1, d2}, [r4:64] @ encoding: [0x04,0xf9,0x1f,0x04]<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vst3.8 {d0, d1, d2}, [r4:128]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vst3.8 {d0, d1, d2}, [r4:256]<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vst3.8 {d0, d1, d2}, [r4]!<br>
+ vst3.8 {d0, d1, d2}, [r4:16]!<br>
+ vst3.8 {d0, d1, d2}, [r4:32]!<br>
+ vst3.8 {d0, d1, d2}, [r4:64]!<br>
+ vst3.8 {d0, d1, d2}, [r4:128]!<br>
+ vst3.8 {d0, d1, d2}, [r4:256]!<br>
+<br>
+@ CHECK: vst3.8 {d0, d1, d2}, [r4]! @ encoding: [0x04,0xf9,0x0d,0x04]<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vst3.8 {d0, d1, d2}, [r4:16]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vst3.8 {d0, d1, d2}, [r4:32]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vst3.8 {d0, d1, d2}, [r4:64]! @ encoding: [0x04,0xf9,0x1d,0x04]<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vst3.8 {d0, d1, d2}, [r4:128]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vst3.8 {d0, d1, d2}, [r4:256]!<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vst3.8 {d0, d1, d2}, [r4], r6<br>
+ vst3.8 {d0, d1, d2}, [r4:16], r6<br>
+ vst3.8 {d0, d1, d2}, [r4:32], r6<br>
+ vst3.8 {d0, d1, d2}, [r4:64], r6<br>
+ vst3.8 {d0, d1, d2}, [r4:128], r6<br>
+ vst3.8 {d0, d1, d2}, [r4:256], r6<br>
+<br>
+@ CHECK: vst3.8 {d0, d1, d2}, [r4], r6 @ encoding: [0x04,0xf9,0x06,0x04]<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vst3.8 {d0, d1, d2}, [r4:16], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vst3.8 {d0, d1, d2}, [r4:32], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vst3.8 {d0, d1, d2}, [r4:64], r6 @ encoding: [0x04,0xf9,0x16,0x04]<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vst3.8 {d0, d1, d2}, [r4:128], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vst3.8 {d0, d1, d2}, [r4:256], r6<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vst3.8 {d0, d2, d4}, [r4]<br>
+ vst3.8 {d0, d2, d4}, [r4:16]<br>
+ vst3.8 {d0, d2, d4}, [r4:32]<br>
+ vst3.8 {d0, d2, d4}, [r4:64]<br>
+ vst3.8 {d0, d2, d4}, [r4:128]<br>
+ vst3.8 {d0, d2, d4}, [r4:256]<br>
+<br>
+@ CHECK: vst3.8 {d0, d2, d4}, [r4] @ encoding: [0x04,0xf9,0x0f,0x05]<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vst3.8 {d0, d2, d4}, [r4:16]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vst3.8 {d0, d2, d4}, [r4:32]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vst3.8 {d0, d2, d4}, [r4:64] @ encoding: [0x04,0xf9,0x1f,0x05]<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vst3.8 {d0, d2, d4}, [r4:128]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vst3.8 {d0, d2, d4}, [r4:256]<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vst3.8 {d0, d2, d4}, [r4]!<br>
+ vst3.8 {d0, d2, d4}, [r4:16]!<br>
+ vst3.8 {d0, d2, d4}, [r4:32]!<br>
+ vst3.8 {d0, d2, d4}, [r4:64]!<br>
+ vst3.8 {d0, d2, d4}, [r4:128]!<br>
+ vst3.8 {d0, d2, d4}, [r4:256]!<br>
+<br>
+@ CHECK: vst3.8 {d0, d2, d4}, [r4]! @ encoding: [0x04,0xf9,0x0d,0x05]<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vst3.8 {d0, d2, d4}, [r4:16]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vst3.8 {d0, d2, d4}, [r4:32]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vst3.8 {d0, d2, d4}, [r4:64]! @ encoding: [0x04,0xf9,0x1d,0x05]<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vst3.8 {d0, d2, d4}, [r4:128]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vst3.8 {d0, d2, d4}, [r4:256]!<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vst3.8 {d0, d2, d4}, [r4], r6<br>
+ vst3.8 {d0, d2, d4}, [r4:16], r6<br>
+ vst3.8 {d0, d2, d4}, [r4:32], r6<br>
+ vst3.8 {d0, d2, d4}, [r4:64], r6<br>
+ vst3.8 {d0, d2, d4}, [r4:128], r6<br>
+ vst3.8 {d0, d2, d4}, [r4:256], r6<br>
+<br>
+@ CHECK: vst3.8 {d0, d2, d4}, [r4], r6 @ encoding: [0x04,0xf9,0x06,0x05]<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vst3.8 {d0, d2, d4}, [r4:16], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vst3.8 {d0, d2, d4}, [r4:32], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vst3.8 {d0, d2, d4}, [r4:64], r6 @ encoding: [0x04,0xf9,0x16,0x05]<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vst3.8 {d0, d2, d4}, [r4:128], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vst3.8 {d0, d2, d4}, [r4:256], r6<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vst3.8 {d0[1], d1[1], d2[1]}, [r4]<br>
+ vst3.8 {d0[1], d1[1], d2[1]}, [r4:16]<br>
+ vst3.8 {d0[1], d1[1], d2[1]}, [r4:32]<br>
+ vst3.8 {d0[1], d1[1], d2[1]}, [r4:64]<br>
+ vst3.8 {d0[1], d1[1], d2[1]}, [r4:128]<br>
+ vst3.8 {d0[1], d1[1], d2[1]}, [r4:256]<br>
+<br>
+@ CHECK: vst3.8 {d0[1], d1[1], d2[1]}, [r4] @ encoding: [0x84,0xf9,0x2f,0x02]<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vst3.8 {d0[1], d1[1], d2[1]}, [r4:16]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vst3.8 {d0[1], d1[1], d2[1]}, [r4:32]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vst3.8 {d0[1], d1[1], d2[1]}, [r4:64]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vst3.8 {d0[1], d1[1], d2[1]}, [r4:128]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vst3.8 {d0[1], d1[1], d2[1]}, [r4:256]<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vst3.8 {d0[1], d1[1], d2[1]}, [r4]!<br>
+ vst3.8 {d0[1], d1[1], d2[1]}, [r4:16]!<br>
+ vst3.8 {d0[1], d1[1], d2[1]}, [r4:32]!<br>
+ vst3.8 {d0[1], d1[1], d2[1]}, [r4:64]!<br>
+ vst3.8 {d0[1], d1[1], d2[1]}, [r4:128]!<br>
+ vst3.8 {d0[1], d1[1], d2[1]}, [r4:256]!<br>
+<br>
+@ CHECK: vst3.8 {d0[1], d1[1], d2[1]}, [r4]! @ encoding: [0x84,0xf9,0x2d,0x02]<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vst3.8 {d0[1], d1[1], d2[1]}, [r4:16]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vst3.8 {d0[1], d1[1], d2[1]}, [r4:32]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vst3.8 {d0[1], d1[1], d2[1]}, [r4:64]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vst3.8 {d0[1], d1[1], d2[1]}, [r4:128]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vst3.8 {d0[1], d1[1], d2[1]}, [r4:256]!<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vst3.8 {d0[1], d1[1], d2[1]}, [r4], r6<br>
+ vst3.8 {d0[1], d1[1], d2[1]}, [r4:16], r6<br>
+ vst3.8 {d0[1], d1[1], d2[1]}, [r4:32], r6<br>
+ vst3.8 {d0[1], d1[1], d2[1]}, [r4:64], r6<br>
+ vst3.8 {d0[1], d1[1], d2[1]}, [r4:128], r6<br>
+ vst3.8 {d0[1], d1[1], d2[1]}, [r4:256], r6<br>
+<br>
+@ CHECK: vst3.8 {d0[1], d1[1], d2[1]}, [r4], r6 @ encoding: [0x84,0xf9,0x26,0x02]<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vst3.8 {d0[1], d1[1], d2[1]}, [r4:16], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vst3.8 {d0[1], d1[1], d2[1]}, [r4:32], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vst3.8 {d0[1], d1[1], d2[1]}, [r4:64], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vst3.8 {d0[1], d1[1], d2[1]}, [r4:128], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vst3.8 {d0[1], d1[1], d2[1]}, [r4:256], r6<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vst3.16 {d0, d1, d2}, [r4]<br>
+ vst3.16 {d0, d1, d2}, [r4:16]<br>
+ vst3.16 {d0, d1, d2}, [r4:32]<br>
+ vst3.16 {d0, d1, d2}, [r4:64]<br>
+ vst3.16 {d0, d1, d2}, [r4:128]<br>
+ vst3.16 {d0, d1, d2}, [r4:256]<br>
+<br>
+@ CHECK: vst3.16 {d0, d1, d2}, [r4] @ encoding: [0x04,0xf9,0x4f,0x04]<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vst3.16 {d0, d1, d2}, [r4:16]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vst3.16 {d0, d1, d2}, [r4:32]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vst3.16 {d0, d1, d2}, [r4:64] @ encoding: [0x04,0xf9,0x5f,0x04]<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vst3.16 {d0, d1, d2}, [r4:128]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vst3.16 {d0, d1, d2}, [r4:256]<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vst3.16 {d0, d1, d2}, [r4]!<br>
+ vst3.16 {d0, d1, d2}, [r4:16]!<br>
+ vst3.16 {d0, d1, d2}, [r4:32]!<br>
+ vst3.16 {d0, d1, d2}, [r4:64]!<br>
+ vst3.16 {d0, d1, d2}, [r4:128]!<br>
+ vst3.16 {d0, d1, d2}, [r4:256]!<br>
+<br>
+@ CHECK: vst3.16 {d0, d1, d2}, [r4]! @ encoding: [0x04,0xf9,0x4d,0x04]<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vst3.16 {d0, d1, d2}, [r4:16]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vst3.16 {d0, d1, d2}, [r4:32]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vst3.16 {d0, d1, d2}, [r4:64]! @ encoding: [0x04,0xf9,0x5d,0x04]<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vst3.16 {d0, d1, d2}, [r4:128]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vst3.16 {d0, d1, d2}, [r4:256]!<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vst3.16 {d0, d1, d2}, [r4], r6<br>
+ vst3.16 {d0, d1, d2}, [r4:16], r6<br>
+ vst3.16 {d0, d1, d2}, [r4:32], r6<br>
+ vst3.16 {d0, d1, d2}, [r4:64], r6<br>
+ vst3.16 {d0, d1, d2}, [r4:128], r6<br>
+ vst3.16 {d0, d1, d2}, [r4:256], r6<br>
+<br>
+@ CHECK: vst3.16 {d0, d1, d2}, [r4], r6 @ encoding: [0x04,0xf9,0x46,0x04]<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vst3.16 {d0, d1, d2}, [r4:16], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vst3.16 {d0, d1, d2}, [r4:32], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vst3.16 {d0, d1, d2}, [r4:64], r6 @ encoding: [0x04,0xf9,0x56,0x04]<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vst3.16 {d0, d1, d2}, [r4:128], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vst3.16 {d0, d1, d2}, [r4:256], r6<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vst3.16 {d0, d2, d4}, [r4]<br>
+ vst3.16 {d0, d2, d4}, [r4:16]<br>
+ vst3.16 {d0, d2, d4}, [r4:32]<br>
+ vst3.16 {d0, d2, d4}, [r4:64]<br>
+ vst3.16 {d0, d2, d4}, [r4:128]<br>
+ vst3.16 {d0, d2, d4}, [r4:256]<br>
+<br>
+@ CHECK: vst3.16 {d0, d2, d4}, [r4] @ encoding: [0x04,0xf9,0x4f,0x05]<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vst3.16 {d0, d2, d4}, [r4:16]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vst3.16 {d0, d2, d4}, [r4:32]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vst3.16 {d0, d2, d4}, [r4:64] @ encoding: [0x04,0xf9,0x5f,0x05]<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vst3.16 {d0, d2, d4}, [r4:128]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vst3.16 {d0, d2, d4}, [r4:256]<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vst3.16 {d0, d2, d4}, [r4]!<br>
+ vst3.16 {d0, d2, d4}, [r4:16]!<br>
+ vst3.16 {d0, d2, d4}, [r4:32]!<br>
+ vst3.16 {d0, d2, d4}, [r4:64]!<br>
+ vst3.16 {d0, d2, d4}, [r4:128]!<br>
+ vst3.16 {d0, d2, d4}, [r4:256]!<br>
+<br>
+@ CHECK: vst3.16 {d0, d2, d4}, [r4]! @ encoding: [0x04,0xf9,0x4d,0x05]<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vst3.16 {d0, d2, d4}, [r4:16]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vst3.16 {d0, d2, d4}, [r4:32]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vst3.16 {d0, d2, d4}, [r4:64]! @ encoding: [0x04,0xf9,0x5d,0x05]<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vst3.16 {d0, d2, d4}, [r4:128]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vst3.16 {d0, d2, d4}, [r4:256]!<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vst3.16 {d0, d2, d4}, [r4], r6<br>
+ vst3.16 {d0, d2, d4}, [r4:16], r6<br>
+ vst3.16 {d0, d2, d4}, [r4:32], r6<br>
+ vst3.16 {d0, d2, d4}, [r4:64], r6<br>
+ vst3.16 {d0, d2, d4}, [r4:128], r6<br>
+ vst3.16 {d0, d2, d4}, [r4:256], r6<br>
+<br>
+@ CHECK: vst3.16 {d0, d2, d4}, [r4], r6 @ encoding: [0x04,0xf9,0x46,0x05]<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vst3.16 {d0, d2, d4}, [r4:16], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vst3.16 {d0, d2, d4}, [r4:32], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vst3.16 {d0, d2, d4}, [r4:64], r6 @ encoding: [0x04,0xf9,0x56,0x05]<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vst3.16 {d0, d2, d4}, [r4:128], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vst3.16 {d0, d2, d4}, [r4:256], r6<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vst3.16 {d0[1], d1[1], d2[1]}, [r4]<br>
+ vst3.16 {d0[1], d1[1], d2[1]}, [r4:16]<br>
+ vst3.16 {d0[1], d1[1], d2[1]}, [r4:32]<br>
+ vst3.16 {d0[1], d1[1], d2[1]}, [r4:64]<br>
+ vst3.16 {d0[1], d1[1], d2[1]}, [r4:128]<br>
+ vst3.16 {d0[1], d1[1], d2[1]}, [r4:256]<br>
+<br>
+@ CHECK: vst3.16 {d0[1], d1[1], d2[1]}, [r4] @ encoding: [0x84,0xf9,0x4f,0x06]<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vst3.16 {d0[1], d1[1], d2[1]}, [r4:16]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vst3.16 {d0[1], d1[1], d2[1]}, [r4:32]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vst3.16 {d0[1], d1[1], d2[1]}, [r4:64]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vst3.16 {d0[1], d1[1], d2[1]}, [r4:128]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vst3.16 {d0[1], d1[1], d2[1]}, [r4:256]<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vst3.16 {d0[1], d1[1], d2[1]}, [r4]!<br>
+ vst3.16 {d0[1], d1[1], d2[1]}, [r4:16]!<br>
+ vst3.16 {d0[1], d1[1], d2[1]}, [r4:32]!<br>
+ vst3.16 {d0[1], d1[1], d2[1]}, [r4:64]!<br>
+ vst3.16 {d0[1], d1[1], d2[1]}, [r4:128]!<br>
+ vst3.16 {d0[1], d1[1], d2[1]}, [r4:256]!<br>
+<br>
+@ CHECK: vst3.16 {d0[1], d1[1], d2[1]}, [r4]! @ encoding: [0x84,0xf9,0x4d,0x06]<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vst3.16 {d0[1], d1[1], d2[1]}, [r4:16]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vst3.16 {d0[1], d1[1], d2[1]}, [r4:32]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vst3.16 {d0[1], d1[1], d2[1]}, [r4:64]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vst3.16 {d0[1], d1[1], d2[1]}, [r4:128]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vst3.16 {d0[1], d1[1], d2[1]}, [r4:256]!<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vst3.16 {d0[1], d1[1], d2[1]}, [r4], r6<br>
+ vst3.16 {d0[1], d1[1], d2[1]}, [r4:16], r6<br>
+ vst3.16 {d0[1], d1[1], d2[1]}, [r4:32], r6<br>
+ vst3.16 {d0[1], d1[1], d2[1]}, [r4:64], r6<br>
+ vst3.16 {d0[1], d1[1], d2[1]}, [r4:128], r6<br>
+ vst3.16 {d0[1], d1[1], d2[1]}, [r4:256], r6<br>
+<br>
+@ CHECK: vst3.16 {d0[1], d1[1], d2[1]}, [r4], r6 @ encoding: [0x84,0xf9,0x46,0x06]<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vst3.16 {d0[1], d1[1], d2[1]}, [r4:16], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vst3.16 {d0[1], d1[1], d2[1]}, [r4:32], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vst3.16 {d0[1], d1[1], d2[1]}, [r4:64], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vst3.16 {d0[1], d1[1], d2[1]}, [r4:128], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vst3.16 {d0[1], d1[1], d2[1]}, [r4:256], r6<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vst3.16 {d0[1], d2[1], d4[1]}, [r4]<br>
+ vst3.16 {d0[1], d2[1], d4[1]}, [r4:16]<br>
+ vst3.16 {d0[1], d2[1], d4[1]}, [r4:32]<br>
+ vst3.16 {d0[1], d2[1], d4[1]}, [r4:64]<br>
+ vst3.16 {d0[1], d2[1], d4[1]}, [r4:128]<br>
+ vst3.16 {d0[1], d2[1], d4[1]}, [r4:256]<br>
+<br>
+@ CHECK: vst3.16 {d0[1], d2[1], d4[1]}, [r4] @ encoding: [0x84,0xf9,0x6f,0x06]<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vst3.16 {d0[1], d2[1], d4[1]}, [r4:16]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vst3.16 {d0[1], d2[1], d4[1]}, [r4:32]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vst3.16 {d0[1], d2[1], d4[1]}, [r4:64]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vst3.16 {d0[1], d2[1], d4[1]}, [r4:128]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vst3.16 {d0[1], d2[1], d4[1]}, [r4:256]<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vst3.16 {d0[1], d2[1], d4[1]}, [r4]!<br>
+ vst3.16 {d0[1], d2[1], d4[1]}, [r4:16]!<br>
+ vst3.16 {d0[1], d2[1], d4[1]}, [r4:32]!<br>
+ vst3.16 {d0[1], d2[1], d4[1]}, [r4:64]!<br>
+ vst3.16 {d0[1], d2[1], d4[1]}, [r4:128]!<br>
+ vst3.16 {d0[1], d2[1], d4[1]}, [r4:256]!<br>
+<br>
+@ CHECK: vst3.16 {d0[1], d1[1], d2[1]}, [r4]! @ encoding: [0x84,0xf9,0x6d,0x06]<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vst3.16 {d0[1], d2[1], d4[1]}, [r4:16]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vst3.16 {d0[1], d2[1], d4[1]}, [r4:32]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vst3.16 {d0[1], d2[1], d4[1]}, [r4:64]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vst3.16 {d0[1], d2[1], d4[1]}, [r4:128]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vst3.16 {d0[1], d2[1], d4[1]}, [r4:256]!<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vst3.16 {d0[1], d2[1], d4[1]}, [r4], r6<br>
+ vst3.16 {d0[1], d2[1], d4[1]}, [r4:16], r6<br>
+ vst3.16 {d0[1], d2[1], d4[1]}, [r4:32], r6<br>
+ vst3.16 {d0[1], d2[1], d4[1]}, [r4:64], r6<br>
+ vst3.16 {d0[1], d2[1], d4[1]}, [r4:128], r6<br>
+ vst3.16 {d0[1], d2[1], d4[1]}, [r4:256], r6<br>
+<br>
+@ CHECK: vst3.16 {d0[1], d2[1], d4[1]}, [r4], r6 @ encoding: [0x84,0xf9,0x66,0x06]<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vst3.16 {d0[1], d2[1], d4[1]}, [r4:16], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vst3.16 {d0[1], d2[1], d4[1]}, [r4:32], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vst3.16 {d0[1], d2[1], d4[1]}, [r4:64], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vst3.16 {d0[1], d2[1], d4[1]}, [r4:128], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vst3.16 {d0[1], d2[1], d4[1]}, [r4:256], r6<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vst3.32 {d0, d1, d2}, [r4]<br>
+ vst3.32 {d0, d1, d2}, [r4:16]<br>
+ vst3.32 {d0, d1, d2}, [r4:32]<br>
+ vst3.32 {d0, d1, d2}, [r4:64]<br>
+ vst3.32 {d0, d1, d2}, [r4:128]<br>
+ vst3.32 {d0, d1, d2}, [r4:256]<br>
+<br>
+@ CHECK: vst3.32 {d0, d1, d2}, [r4] @ encoding: [0x04,0xf9,0x8f,0x04]<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vst3.32 {d0, d1, d2}, [r4:16]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vst3.32 {d0, d1, d2}, [r4:32]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vst3.32 {d0, d1, d2}, [r4:64] @ encoding: [0x04,0xf9,0x9f,0x04]<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vst3.32 {d0, d1, d2}, [r4:128]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vst3.32 {d0, d1, d2}, [r4:256]<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vst3.32 {d0, d1, d2}, [r4]!<br>
+ vst3.32 {d0, d1, d2}, [r4:16]!<br>
+ vst3.32 {d0, d1, d2}, [r4:32]!<br>
+ vst3.32 {d0, d1, d2}, [r4:64]!<br>
+ vst3.32 {d0, d1, d2}, [r4:128]!<br>
+ vst3.32 {d0, d1, d2}, [r4:256]!<br>
+<br>
+@ CHECK: vst3.32 {d0, d1, d2}, [r4]! @ encoding: [0x04,0xf9,0x8d,0x04]<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vst3.32 {d0, d1, d2}, [r4:16]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vst3.32 {d0, d1, d2}, [r4:32]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vst3.32 {d0, d1, d2}, [r4:64]! @ encoding: [0x04,0xf9,0x9d,0x04]<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vst3.32 {d0, d1, d2}, [r4:128]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vst3.32 {d0, d1, d2}, [r4:256]!<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vst3.32 {d0, d1, d2}, [r4], r6<br>
+ vst3.32 {d0, d1, d2}, [r4:16], r6<br>
+ vst3.32 {d0, d1, d2}, [r4:32], r6<br>
+ vst3.32 {d0, d1, d2}, [r4:64], r6<br>
+ vst3.32 {d0, d1, d2}, [r4:128], r6<br>
+ vst3.32 {d0, d1, d2}, [r4:256], r6<br>
+<br>
+@ CHECK: vst3.32 {d0, d1, d2}, [r4], r6 @ encoding: [0x04,0xf9,0x86,0x04]<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vst3.32 {d0, d1, d2}, [r4:16], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vst3.32 {d0, d1, d2}, [r4:32], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vst3.32 {d0, d1, d2}, [r4:64], r6 @ encoding: [0x04,0xf9,0x96,0x04]<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vst3.32 {d0, d1, d2}, [r4:128], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vst3.32 {d0, d1, d2}, [r4:256], r6<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vst3.32 {d0, d2, d4}, [r4]<br>
+ vst3.32 {d0, d2, d4}, [r4:16]<br>
+ vst3.32 {d0, d2, d4}, [r4:32]<br>
+ vst3.32 {d0, d2, d4}, [r4:64]<br>
+ vst3.32 {d0, d2, d4}, [r4:128]<br>
+ vst3.32 {d0, d2, d4}, [r4:256]<br>
+<br>
+@ CHECK: vst3.32 {d0, d2, d4}, [r4] @ encoding: [0x04,0xf9,0x8f,0x05]<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vst3.32 {d0, d2, d4}, [r4:16]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vst3.32 {d0, d2, d4}, [r4:32]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vst3.32 {d0, d2, d4}, [r4:64] @ encoding: [0x04,0xf9,0x9f,0x05]<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vst3.32 {d0, d2, d4}, [r4:128]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vst3.32 {d0, d2, d4}, [r4:256]<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vst3.32 {d0, d2, d4}, [r4]!<br>
+ vst3.32 {d0, d2, d4}, [r4:16]!<br>
+ vst3.32 {d0, d2, d4}, [r4:32]!<br>
+ vst3.32 {d0, d2, d4}, [r4:64]!<br>
+ vst3.32 {d0, d2, d4}, [r4:128]!<br>
+ vst3.32 {d0, d2, d4}, [r4:256]!<br>
+<br>
+@ CHECK: vst3.32 {d0, d2, d4}, [r4]! @ encoding: [0x04,0xf9,0x8d,0x05]<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vst3.32 {d0, d2, d4}, [r4:16]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vst3.32 {d0, d2, d4}, [r4:32]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vst3.32 {d0, d2, d4}, [r4:64]! @ encoding: [0x04,0xf9,0x9d,0x05]<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vst3.32 {d0, d2, d4}, [r4:128]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vst3.32 {d0, d2, d4}, [r4:256]!<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vst3.32 {d0, d2, d4}, [r4], r6<br>
+ vst3.32 {d0, d2, d4}, [r4:16], r6<br>
+ vst3.32 {d0, d2, d4}, [r4:32], r6<br>
+ vst3.32 {d0, d2, d4}, [r4:64], r6<br>
+ vst3.32 {d0, d2, d4}, [r4:128], r6<br>
+ vst3.32 {d0, d2, d4}, [r4:256], r6<br>
+<br>
+@ CHECK: vst3.32 {d0, d2, d4}, [r4], r6 @ encoding: [0x04,0xf9,0x86,0x05]<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vst3.32 {d0, d2, d4}, [r4:16], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vst3.32 {d0, d2, d4}, [r4:32], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vst3.32 {d0, d2, d4}, [r4:64], r6 @ encoding: [0x04,0xf9,0x96,0x05]<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vst3.32 {d0, d2, d4}, [r4:128], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vst3.32 {d0, d2, d4}, [r4:256], r6<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vst3.32 {d0[1], d1[1], d2[1]}, [r4]<br>
+ vst3.32 {d0[1], d1[1], d2[1]}, [r4:16]<br>
+ vst3.32 {d0[1], d1[1], d2[1]}, [r4:32]<br>
+ vst3.32 {d0[1], d1[1], d2[1]}, [r4:64]<br>
+ vst3.32 {d0[1], d1[1], d2[1]}, [r4:128]<br>
+ vst3.32 {d0[1], d1[1], d2[1]}, [r4:256]<br>
+<br>
+@ CHECK: vst3.32 {d0[1], d1[1], d2[1]}, [r4] @ encoding: [0x84,0xf9,0x8f,0x0a]<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vst3.32 {d0[1], d1[1], d2[1]}, [r4:16]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vst3.32 {d0[1], d1[1], d2[1]}, [r4:32]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vst3.32 {d0[1], d1[1], d2[1]}, [r4:64]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vst3.32 {d0[1], d1[1], d2[1]}, [r4:128]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vst3.32 {d0[1], d1[1], d2[1]}, [r4:256]<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vst3.32 {d0[1], d1[1], d2[1]}, [r4]!<br>
+ vst3.32 {d0[1], d1[1], d2[1]}, [r4:16]!<br>
+ vst3.32 {d0[1], d1[1], d2[1]}, [r4:32]!<br>
+ vst3.32 {d0[1], d1[1], d2[1]}, [r4:64]!<br>
+ vst3.32 {d0[1], d1[1], d2[1]}, [r4:128]!<br>
+ vst3.32 {d0[1], d1[1], d2[1]}, [r4:256]!<br>
+<br>
+@ CHECK: vst3.32 {d0[1], d1[1], d2[1]}, [r4]! @ encoding: [0x84,0xf9,0x8d,0x0a]<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vst3.32 {d0[1], d1[1], d2[1]}, [r4:16]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vst3.32 {d0[1], d1[1], d2[1]}, [r4:32]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vst3.32 {d0[1], d1[1], d2[1]}, [r4:64]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vst3.32 {d0[1], d1[1], d2[1]}, [r4:128]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vst3.32 {d0[1], d1[1], d2[1]}, [r4:256]!<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vst3.32 {d0[1], d1[1], d2[1]}, [r4], r6<br>
+ vst3.32 {d0[1], d1[1], d2[1]}, [r4:16], r6<br>
+ vst3.32 {d0[1], d1[1], d2[1]}, [r4:32], r6<br>
+ vst3.32 {d0[1], d1[1], d2[1]}, [r4:64], r6<br>
+ vst3.32 {d0[1], d1[1], d2[1]}, [r4:128], r6<br>
+ vst3.32 {d0[1], d1[1], d2[1]}, [r4:256], r6<br>
+<br>
+@ CHECK: vst3.32 {d0[1], d1[1], d2[1]}, [r4], r6 @ encoding: [0x84,0xf9,0x86,0x0a]<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vst3.32 {d0[1], d1[1], d2[1]}, [r4:16], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vst3.32 {d0[1], d1[1], d2[1]}, [r4:32], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vst3.32 {d0[1], d1[1], d2[1]}, [r4:64], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vst3.32 {d0[1], d1[1], d2[1]}, [r4:128], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vst3.32 {d0[1], d1[1], d2[1]}, [r4:256], r6<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vst3.32 {d0[1], d2[1], d4[1]}, [r4]<br>
+ vst3.32 {d0[1], d2[1], d4[1]}, [r4:16]<br>
+ vst3.32 {d0[1], d2[1], d4[1]}, [r4:32]<br>
+ vst3.32 {d0[1], d2[1], d4[1]}, [r4:64]<br>
+ vst3.32 {d0[1], d2[1], d4[1]}, [r4:128]<br>
+ vst3.32 {d0[1], d2[1], d4[1]}, [r4:256]<br>
+<br>
+@ CHECK: vst3.32 {d0[1], d2[1], d4[1]}, [r4] @ encoding: [0x84,0xf9,0xcf,0x0a]<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vst3.32 {d0[1], d2[1], d4[1]}, [r4:16]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vst3.32 {d0[1], d2[1], d4[1]}, [r4:32]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vst3.32 {d0[1], d2[1], d4[1]}, [r4:64]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vst3.32 {d0[1], d2[1], d4[1]}, [r4:128]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vst3.32 {d0[1], d2[1], d4[1]}, [r4:256]<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vst3.32 {d0[1], d2[1], d4[1]}, [r4]!<br>
+ vst3.32 {d0[1], d2[1], d4[1]}, [r4:16]!<br>
+ vst3.32 {d0[1], d2[1], d4[1]}, [r4:32]!<br>
+ vst3.32 {d0[1], d2[1], d4[1]}, [r4:64]!<br>
+ vst3.32 {d0[1], d2[1], d4[1]}, [r4:128]!<br>
+ vst3.32 {d0[1], d2[1], d4[1]}, [r4:256]!<br>
+<br>
+@ CHECK: vst3.32 {d0[1], d2[1], d4[1]}, [r4]! @ encoding: [0x84,0xf9,0xcd,0x0a]<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vst3.32 {d0[1], d2[1], d4[1]}, [r4:16]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vst3.32 {d0[1], d2[1], d4[1]}, [r4:32]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vst3.32 {d0[1], d2[1], d4[1]}, [r4:64]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vst3.32 {d0[1], d2[1], d4[1]}, [r4:128]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vst3.32 {d0[1], d2[1], d4[1]}, [r4:256]!<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vst3.32 {d0[1], d2[1], d4[1]}, [r4], r6<br>
+ vst3.32 {d0[1], d2[1], d4[1]}, [r4:16], r6<br>
+ vst3.32 {d0[1], d2[1], d4[1]}, [r4:32], r6<br>
+ vst3.32 {d0[1], d2[1], d4[1]}, [r4:64], r6<br>
+ vst3.32 {d0[1], d2[1], d4[1]}, [r4:128], r6<br>
+ vst3.32 {d0[1], d2[1], d4[1]}, [r4:256], r6<br>
+<br>
+@ CHECK: vst3.32 {d0[1], d2[1], d4[1]}, [r4], r6 @ encoding: [0x84,0xf9,0xc6,0x0a]<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vst3.32 {d0[1], d2[1], d4[1]}, [r4:16], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vst3.32 {d0[1], d2[1], d4[1]}, [r4:32], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vst3.32 {d0[1], d2[1], d4[1]}, [r4:64], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vst3.32 {d0[1], d2[1], d4[1]}, [r4:128], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be omitted<br>
+@ CHECK-ERRORS: vst3.32 {d0[1], d2[1], d4[1]}, [r4:256], r6<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vst4.8 {d0, d1, d2, d3}, [r4]<br>
+ vst4.8 {d0, d1, d2, d3}, [r4:16]<br>
+ vst4.8 {d0, d1, d2, d3}, [r4:32]<br>
+ vst4.8 {d0, d1, d2, d3}, [r4:64]<br>
+ vst4.8 {d0, d1, d2, d3}, [r4:128]<br>
+ vst4.8 {d0, d1, d2, d3}, [r4:256]<br>
+<br>
+@ CHECK: vst4.8 {d0, d1, d2, d3}, [r4] @ encoding: [0x04,0xf9,0x0f,0x00]<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted<br>
+@ CHECK-ERRORS: vst4.8 {d0, d1, d2, d3}, [r4:16]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted<br>
+@ CHECK-ERRORS: vst4.8 {d0, d1, d2, d3}, [r4:32]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vst4.8 {d0, d1, d2, d3}, [r4:64] @ encoding: [0x04,0xf9,0x1f,0x00]<br>
+@ CHECK: vst4.8 {d0, d1, d2, d3}, [r4:128] @ encoding: [0x04,0xf9,0x2f,0x00]<br>
+@ CHECK: vst4.8 {d0, d1, d2, d3}, [r4:256] @ encoding: [0x04,0xf9,0x3f,0x00]<br>
+<br>
+ vst4.8 {d0, d1, d2, d3}, [r4]!<br>
+ vst4.8 {d0, d1, d2, d3}, [r4:16]!<br>
+ vst4.8 {d0, d1, d2, d3}, [r4:32]!<br>
+ vst4.8 {d0, d1, d2, d3}, [r4:64]!<br>
+ vst4.8 {d0, d1, d2, d3}, [r4:128]!<br>
+ vst4.8 {d0, d1, d2, d3}, [r4:256]!<br>
+<br>
+@ CHECK: vst4.8 {d0, d1, d2, d3}, [r4]! @ encoding: [0x04,0xf9,0x0d,0x00]<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted<br>
+@ CHECK-ERRORS: vst4.8 {d0, d1, d2, d3}, [r4:16]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted<br>
+@ CHECK-ERRORS: vst4.8 {d0, d1, d2, d3}, [r4:32]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vst4.8 {d0, d1, d2, d3}, [r4:64]! @ encoding: [0x04,0xf9,0x1d,0x00]<br>
+@ CHECK: vst4.8 {d0, d1, d2, d3}, [r4:128]! @ encoding: [0x04,0xf9,0x2d,0x00]<br>
+@ CHECK: vst4.8 {d0, d1, d2, d3}, [r4:256]! @ encoding: [0x04,0xf9,0x3d,0x00]<br>
+<br>
+ vst4.8 {d0, d1, d2, d3}, [r4], r6<br>
+ vst4.8 {d0, d1, d2, d3}, [r4:16], r6<br>
+ vst4.8 {d0, d1, d2, d3}, [r4:32], r6<br>
+ vst4.8 {d0, d1, d2, d3}, [r4:64], r6<br>
+ vst4.8 {d0, d1, d2, d3}, [r4:128], r6<br>
+ vst4.8 {d0, d1, d2, d3}, [r4:256], r6<br>
+<br>
+@ CHECK: vst4.8 {d0, d1, d2, d3}, [r4], r6 @ encoding: [0x04,0xf9,0x06,0x00]<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted<br>
+@ CHECK-ERRORS: vst4.8 {d0, d1, d2, d3}, [r4:16], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted<br>
+@ CHECK-ERRORS: vst4.8 {d0, d1, d2, d3}, [r4:32], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vst4.8 {d0, d1, d2, d3}, [r4:64], r6 @ encoding: [0x04,0xf9,0x16,0x00]<br>
+@ CHECK: vst4.8 {d0, d1, d2, d3}, [r4:128], r6 @ encoding: [0x04,0xf9,0x26,0x00]<br>
+@ CHECK: vst4.8 {d0, d1, d2, d3}, [r4:256], r6 @ encoding: [0x04,0xf9,0x36,0x00]<br>
+<br>
+ vst4.8 {d0, d2, d4, d6}, [r4]<br>
+ vst4.8 {d0, d2, d4, d6}, [r4:16]<br>
+ vst4.8 {d0, d2, d4, d6}, [r4:32]<br>
+ vst4.8 {d0, d2, d4, d6}, [r4:64]<br>
+ vst4.8 {d0, d2, d4, d6}, [r4:128]<br>
+ vst4.8 {d0, d2, d4, d6}, [r4:256]<br>
+<br>
+@ CHECK: vst4.8 {d0, d2, d4, d6}, [r4] @ encoding: [0x04,0xf9,0x0f,0x01]<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted<br>
+@ CHECK-ERRORS: vst4.8 {d0, d2, d4, d6}, [r4:16]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted<br>
+@ CHECK-ERRORS: vst4.8 {d0, d2, d4, d6}, [r4:32]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vst4.8 {d0, d2, d4, d6}, [r4:64] @ encoding: [0x04,0xf9,0x1f,0x01]<br>
+@ CHECK: vst4.8 {d0, d2, d4, d6}, [r4:128] @ encoding: [0x04,0xf9,0x2f,0x01]<br>
+@ CHECK: vst4.8 {d0, d2, d4, d6}, [r4:256] @ encoding: [0x04,0xf9,0x3f,0x01]<br>
+<br>
+ vst4.8 {d0, d2, d4, d6}, [r4]!<br>
+ vst4.8 {d0, d2, d4, d6}, [r4:16]!<br>
+ vst4.8 {d0, d2, d4, d6}, [r4:32]!<br>
+ vst4.8 {d0, d2, d4, d6}, [r4:64]!<br>
+ vst4.8 {d0, d2, d4, d6}, [r4:128]!<br>
+ vst4.8 {d0, d2, d4, d6}, [r4:256]!<br>
+<br>
+@ CHECK: vst4.8 {d0, d2, d4, d6}, [r4]! @ encoding: [0x04,0xf9,0x0d,0x01]<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted<br>
+@ CHECK-ERRORS: vst4.8 {d0, d2, d4, d6}, [r4:16]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted<br>
+@ CHECK-ERRORS: vst4.8 {d0, d2, d4, d6}, [r4:32]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vst4.8 {d0, d2, d4, d6}, [r4:64]! @ encoding: [0x04,0xf9,0x1d,0x01]<br>
+@ CHECK: vst4.8 {d0, d2, d4, d6}, [r4:128]! @ encoding: [0x04,0xf9,0x2d,0x01]<br>
+@ CHECK: vst4.8 {d0, d2, d4, d6}, [r4:256]! @ encoding: [0x04,0xf9,0x3d,0x01]<br>
+<br>
+ vst4.8 {d0, d2, d4, d6}, [r4], r6<br>
+ vst4.8 {d0, d2, d4, d6}, [r4:16], r6<br>
+ vst4.8 {d0, d2, d4, d6}, [r4:32], r6<br>
+ vst4.8 {d0, d2, d4, d6}, [r4:64], r6<br>
+ vst4.8 {d0, d2, d4, d6}, [r4:128], r6<br>
+ vst4.8 {d0, d2, d4, d6}, [r4:256], r6<br>
+<br>
+@ CHECK: vst4.8 {d0, d2, d4, d6}, [r4], r6 @ encoding: [0x04,0xf9,0x06,0x01]<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted<br>
+@ CHECK-ERRORS: vst4.8 {d0, d2, d4, d6}, [r4:16], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted<br>
+@ CHECK-ERRORS: vst4.8 {d0, d2, d4, d6}, [r4:32], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vst4.8 {d0, d2, d4, d6}, [r4:64], r6 @ encoding: [0x04,0xf9,0x16,0x01]<br>
+@ CHECK: vst4.8 {d0, d2, d4, d6}, [r4:128], r6 @ encoding: [0x04,0xf9,0x26,0x01]<br>
+@ CHECK: vst4.8 {d0, d2, d4, d6}, [r4:256], r6 @ encoding: [0x04,0xf9,0x36,0x01]<br>
+<br>
+ vst4.8 {d0[1], d1[1], d2[1], d3[1]}, [r4]<br>
+ vst4.8 {d0[1], d1[1], d2[1], d3[1]}, [r4:16]<br>
+ vst4.8 {d0[1], d1[1], d2[1], d3[1]}, [r4:32]<br>
+ vst4.8 {d0[1], d1[1], d2[1], d3[1]}, [r4:64]<br>
+ vst4.8 {d0[1], d1[1], d2[1], d3[1]}, [r4:128]<br>
+ vst4.8 {d0[1], d1[1], d2[1], d3[1]}, [r4:256]<br>
+<br>
+@ CHECK: vst4.8 {d0[1], d1[1], d2[1], d3[1]}, [r4] @ encoding: [0x84,0xf9,0x2f,0x03]<br>
+@ CHECK-ERRORS: error: alignment must be 32 or omitted<br>
+@ CHECK-ERRORS: vst4.8 {d0[1], d1[1], d2[1], d3[1]}, [r4:16]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vst4.8 {d0[1], d1[1], d2[1], d3[1]}, [r4:32] @ encoding: [0x84,0xf9,0x3f,0x03]<br>
+@ CHECK-ERRORS: error: alignment must be 32 or omitted<br>
+@ CHECK-ERRORS: vst4.8 {d0[1], d1[1], d2[1], d3[1]}, [r4:64]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 32 or omitted<br>
+@ CHECK-ERRORS: vst4.8 {d0[1], d1[1], d2[1], d3[1]}, [r4:128]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 32 or omitted<br>
+@ CHECK-ERRORS: vst4.8 {d0[1], d1[1], d2[1], d3[1]}, [r4:256]<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vst4.8 {d0[1], d1[1], d2[1], d3[1]}, [r4]!<br>
+ vst4.8 {d0[1], d1[1], d2[1], d3[1]}, [r4:16]!<br>
+ vst4.8 {d0[1], d1[1], d2[1], d3[1]}, [r4:32]!<br>
+ vst4.8 {d0[1], d1[1], d2[1], d3[1]}, [r4:64]!<br>
+ vst4.8 {d0[1], d1[1], d2[1], d3[1]}, [r4:128]!<br>
+ vst4.8 {d0[1], d1[1], d2[1], d3[1]}, [r4:256]!<br>
+<br>
+@ CHECK: vst4.8 {d0[1], d1[1], d2[1], d3[1]}, [r4]! @ encoding: [0x84,0xf9,0x2d,0x03]<br>
+@ CHECK-ERRORS: error: alignment must be 32 or omitted<br>
+@ CHECK-ERRORS: vst4.8 {d0[1], d1[1], d2[1], d3[1]}, [r4:16]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vst4.8 {d0[1], d1[1], d2[1], d3[1]}, [r4:32]! @ encoding: [0x84,0xf9,0x3d,0x03]<br>
+@ CHECK-ERRORS: error: alignment must be 32 or omitted<br>
+@ CHECK-ERRORS: vst4.8 {d0[1], d1[1], d2[1], d3[1]}, [r4:64]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 32 or omitted<br>
+@ CHECK-ERRORS: vst4.8 {d0[1], d1[1], d2[1], d3[1]}, [r4:128]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 32 or omitted<br>
+@ CHECK-ERRORS: vst4.8 {d0[1], d1[1], d2[1], d3[1]}, [r4:256]!<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vst4.8 {d0[1], d1[1], d2[1], d3[1]}, [r4], r6<br>
+ vst4.8 {d0[1], d1[1], d2[1], d3[1]}, [r4:16], r6<br>
+ vst4.8 {d0[1], d1[1], d2[1], d3[1]}, [r4:32], r6<br>
+ vst4.8 {d0[1], d1[1], d2[1], d3[1]}, [r4:64], r6<br>
+ vst4.8 {d0[1], d1[1], d2[1], d3[1]}, [r4:128], r6<br>
+ vst4.8 {d0[1], d1[1], d2[1], d3[1]}, [r4:256], r6<br>
+<br>
+@ CHECK: vst4.8 {d0[1], d1[1], d2[1], d3[1]}, [r4], r6 @ encoding: [0x84,0xf9,0x26,0x03]<br>
+@ CHECK-ERRORS: error: alignment must be 32 or omitted<br>
+@ CHECK-ERRORS: vst4.8 {d0[1], d1[1], d2[1], d3[1]}, [r4:16], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vst4.8 {d0[1], d1[1], d2[1], d3[1]}, [r4:32], r6 @ encoding: [0x84,0xf9,0x36,0x03]<br>
+@ CHECK-ERRORS: error: alignment must be 32 or omitted<br>
+@ CHECK-ERRORS: vst4.8 {d0[1], d1[1], d2[1], d3[1]}, [r4:64], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 32 or omitted<br>
+@ CHECK-ERRORS: vst4.8 {d0[1], d1[1], d2[1], d3[1]}, [r4:128], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 32 or omitted<br>
+@ CHECK-ERRORS: vst4.8 {d0[1], d1[1], d2[1], d3[1]}, [r4:256], r6<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vst4.16 {d0, d1, d2, d3}, [r4]<br>
+ vst4.16 {d0, d1, d2, d3}, [r4:16]<br>
+ vst4.16 {d0, d1, d2, d3}, [r4:32]<br>
+ vst4.16 {d0, d1, d2, d3}, [r4:64]<br>
+ vst4.16 {d0, d1, d2, d3}, [r4:128]<br>
+ vst4.16 {d0, d1, d2, d3}, [r4:256]<br>
+<br>
+@ CHECK: vst4.16 {d0, d1, d2, d3}, [r4] @ encoding: [0x04,0xf9,0x4f,0x00]<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted<br>
+@ CHECK-ERRORS: vst4.16 {d0, d1, d2, d3}, [r4:16]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted<br>
+@ CHECK-ERRORS: vst4.16 {d0, d1, d2, d3}, [r4:32]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vst4.16 {d0, d1, d2, d3}, [r4:64] @ encoding: [0x04,0xf9,0x5f,0x00]<br>
+@ CHECK: vst4.16 {d0, d1, d2, d3}, [r4:128] @ encoding: [0x04,0xf9,0x6f,0x00]<br>
+@ CHECK: vst4.16 {d0, d1, d2, d3}, [r4:256] @ encoding: [0x04,0xf9,0x7f,0x00]<br>
+<br>
+ vst4.16 {d0, d1, d2, d3}, [r4]!<br>
+ vst4.16 {d0, d1, d2, d3}, [r4:16]!<br>
+ vst4.16 {d0, d1, d2, d3}, [r4:32]!<br>
+ vst4.16 {d0, d1, d2, d3}, [r4:64]!<br>
+ vst4.16 {d0, d1, d2, d3}, [r4:128]!<br>
+ vst4.16 {d0, d1, d2, d3}, [r4:256]!<br>
+<br>
+@ CHECK: vst4.16 {d0, d1, d2, d3}, [r4]! @ encoding: [0x04,0xf9,0x4d,0x00]<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted<br>
+@ CHECK-ERRORS: vst4.16 {d0, d1, d2, d3}, [r4:16]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted<br>
+@ CHECK-ERRORS: vst4.16 {d0, d1, d2, d3}, [r4:32]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vst4.16 {d0, d1, d2, d3}, [r4:64]! @ encoding: [0x04,0xf9,0x5d,0x00]<br>
+@ CHECK: vst4.16 {d0, d1, d2, d3}, [r4:128]! @ encoding: [0x04,0xf9,0x6d,0x00]<br>
+@ CHECK: vst4.16 {d0, d1, d2, d3}, [r4:256]! @ encoding: [0x04,0xf9,0x7d,0x00]<br>
+<br>
+ vst4.16 {d0, d1, d2, d3}, [r4], r6<br>
+ vst4.16 {d0, d1, d2, d3}, [r4:16], r6<br>
+ vst4.16 {d0, d1, d2, d3}, [r4:32], r6<br>
+ vst4.16 {d0, d1, d2, d3}, [r4:64], r6<br>
+ vst4.16 {d0, d1, d2, d3}, [r4:128], r6<br>
+ vst4.16 {d0, d1, d2, d3}, [r4:256], r6<br>
+<br>
+@ CHECK: vst4.16 {d0, d1, d2, d3}, [r4], r6 @ encoding: [0x04,0xf9,0x46,0x00]<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted<br>
+@ CHECK-ERRORS: vst4.16 {d0, d1, d2, d3}, [r4:16], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted<br>
+@ CHECK-ERRORS: vst4.16 {d0, d1, d2, d3}, [r4:32], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vst4.16 {d0, d1, d2, d3}, [r4:64], r6 @ encoding: [0x04,0xf9,0x56,0x00]<br>
+@ CHECK: vst4.16 {d0, d1, d2, d3}, [r4:128], r6 @ encoding: [0x04,0xf9,0x66,0x00]<br>
+@ CHECK: vst4.16 {d0, d1, d2, d3}, [r4:256], r6 @ encoding: [0x04,0xf9,0x76,0x00]<br>
+<br>
+ vst4.16 {d0, d2, d4, d6}, [r4]<br>
+ vst4.16 {d0, d2, d4, d6}, [r4:16]<br>
+ vst4.16 {d0, d2, d4, d6}, [r4:32]<br>
+ vst4.16 {d0, d2, d4, d6}, [r4:64]<br>
+ vst4.16 {d0, d2, d4, d6}, [r4:128]<br>
+ vst4.16 {d0, d2, d4, d6}, [r4:256]<br>
+<br>
+@ CHECK: vst4.16 {d0, d2, d4, d6}, [r4] @ encoding: [0x04,0xf9,0x4f,0x01]<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted<br>
+@ CHECK-ERRORS: vst4.16 {d0, d2, d4, d6}, [r4:16]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted<br>
+@ CHECK-ERRORS: vst4.16 {d0, d2, d4, d6}, [r4:32]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vst4.16 {d0, d2, d4, d6}, [r4:64] @ encoding: [0x04,0xf9,0x5f,0x01]<br>
+@ CHECK: vst4.16 {d0, d2, d4, d6}, [r4:128] @ encoding: [0x04,0xf9,0x6f,0x01]<br>
+@ CHECK: vst4.16 {d0, d2, d4, d6}, [r4:256] @ encoding: [0x04,0xf9,0x7f,0x01]<br>
+<br>
+ vst4.16 {d0, d2, d4, d6}, [r4]!<br>
+ vst4.16 {d0, d2, d4, d6}, [r4:16]!<br>
+ vst4.16 {d0, d2, d4, d6}, [r4:32]!<br>
+ vst4.16 {d0, d2, d4, d6}, [r4:64]!<br>
+ vst4.16 {d0, d2, d4, d6}, [r4:128]!<br>
+ vst4.16 {d0, d2, d4, d6}, [r4:256]!<br>
+<br>
+@ CHECK: vst4.16 {d0, d2, d4, d6}, [r4]! @ encoding: [0x04,0xf9,0x4d,0x01]<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted<br>
+@ CHECK-ERRORS: vst4.16 {d0, d2, d4, d6}, [r4:16]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted<br>
+@ CHECK-ERRORS: vst4.16 {d0, d2, d4, d6}, [r4:32]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vst4.16 {d0, d2, d4, d6}, [r4:64]! @ encoding: [0x04,0xf9,0x5d,0x01]<br>
+@ CHECK: vst4.16 {d0, d2, d4, d6}, [r4:128]! @ encoding: [0x04,0xf9,0x6d,0x01]<br>
+@ CHECK: vst4.16 {d0, d2, d4, d6}, [r4:256]! @ encoding: [0x04,0xf9,0x7d,0x01]<br>
+<br>
+ vst4.16 {d0, d2, d4, d6}, [r4], r6<br>
+ vst4.16 {d0, d2, d4, d6}, [r4:16], r6<br>
+ vst4.16 {d0, d2, d4, d6}, [r4:32], r6<br>
+ vst4.16 {d0, d2, d4, d6}, [r4:64], r6<br>
+ vst4.16 {d0, d2, d4, d6}, [r4:128], r6<br>
+ vst4.16 {d0, d2, d4, d6}, [r4:256], r6<br>
+<br>
+@ CHECK: vst4.16 {d0, d2, d4, d6}, [r4], r6 @ encoding: [0x04,0xf9,0x46,0x01]<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted<br>
+@ CHECK-ERRORS: vst4.16 {d0, d2, d4, d6}, [r4:16], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted<br>
+@ CHECK-ERRORS: vst4.16 {d0, d2, d4, d6}, [r4:32], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vst4.16 {d0, d2, d4, d6}, [r4:64], r6 @ encoding: [0x04,0xf9,0x56,0x01]<br>
+@ CHECK: vst4.16 {d0, d2, d4, d6}, [r4:128], r6 @ encoding: [0x04,0xf9,0x66,0x01]<br>
+@ CHECK: vst4.16 {d0, d2, d4, d6}, [r4:256], r6 @ encoding: [0x04,0xf9,0x76,0x01]<br>
+<br>
+ vst4.16 {d0[1], d1[1], d2[1], d3[1]}, [r4]<br>
+ vst4.16 {d0[1], d1[1], d2[1], d3[1]}, [r4:16]<br>
+ vst4.16 {d0[1], d1[1], d2[1], d3[1]}, [r4:32]<br>
+ vst4.16 {d0[1], d1[1], d2[1], d3[1]}, [r4:64]<br>
+ vst4.16 {d0[1], d1[1], d2[1], d3[1]}, [r4:128]<br>
+ vst4.16 {d0[1], d1[1], d2[1], d3[1]}, [r4:256]<br>
+<br>
+@ CHECK: vst4.16 {d0[1], d1[1], d2[1], d3[1]}, [r4] @ encoding: [0x84,0xf9,0x4f,0x07]<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vst4.16 {d0[1], d1[1], d2[1], d3[1]}, [r4:16]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vst4.16 {d0[1], d1[1], d2[1], d3[1]}, [r4:32]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vst4.16 {d0[1], d1[1], d2[1], d3[1]}, [r4:64] @ encoding: [0x84,0xf9,0x5f,0x07]<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vst4.16 {d0[1], d1[1], d2[1], d3[1]}, [r4:128]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vst4.16 {d0[1], d1[1], d2[1], d3[1]}, [r4:256]<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vst4.16 {d0[1], d1[1], d2[1], d3[1]}, [r4]!<br>
+ vst4.16 {d0[1], d1[1], d2[1], d3[1]}, [r4:16]!<br>
+ vst4.16 {d0[1], d1[1], d2[1], d3[1]}, [r4:32]!<br>
+ vst4.16 {d0[1], d1[1], d2[1], d3[1]}, [r4:64]!<br>
+ vst4.16 {d0[1], d1[1], d2[1], d3[1]}, [r4:128]!<br>
+ vst4.16 {d0[1], d1[1], d2[1], d3[1]}, [r4:256]!<br>
+<br>
+@ CHECK: vst4.16 {d0[1], d1[1], d2[1], d3[1]}, [r4]! @ encoding: [0x84,0xf9,0x4d,0x07]<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vst4.16 {d0[1], d1[1], d2[1], d3[1]}, [r4:16]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vst4.16 {d0[1], d1[1], d2[1], d3[1]}, [r4:32]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vst4.16 {d0[1], d1[1], d2[1], d3[1]}, [r4:64]! @ encoding: [0x84,0xf9,0x5d,0x07]<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vst4.16 {d0[1], d1[1], d2[1], d3[1]}, [r4:128]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vst4.16 {d0[1], d1[1], d2[1], d3[1]}, [r4:256]!<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vst4.16 {d0[1], d1[1], d2[1], d3[1]}, [r4], r6<br>
+ vst4.16 {d0[1], d1[1], d2[1], d3[1]}, [r4:16], r6<br>
+ vst4.16 {d0[1], d1[1], d2[1], d3[1]}, [r4:32], r6<br>
+ vst4.16 {d0[1], d1[1], d2[1], d3[1]}, [r4:64], r6<br>
+ vst4.16 {d0[1], d1[1], d2[1], d3[1]}, [r4:128], r6<br>
+ vst4.16 {d0[1], d1[1], d2[1], d3[1]}, [r4:256], r6<br>
+<br>
+@ CHECK: vst4.16 {d0[1], d1[1], d2[1], d3[1]}, [r4], r6 @ encoding: [0x84,0xf9,0x46,0x07]<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vst4.16 {d0[1], d1[1], d2[1], d3[1]}, [r4:16], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vst4.16 {d0[1], d1[1], d2[1], d3[1]}, [r4:32], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vst4.16 {d0[1], d1[1], d2[1], d3[1]}, [r4:64], r6 @ encoding: [0x84,0xf9,0x56,0x07]<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vst4.16 {d0[1], d1[1], d2[1], d3[1]}, [r4:128], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vst4.16 {d0[1], d1[1], d2[1], d3[1]}, [r4:256], r6<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vst4.16 {d0[1], d2[1], d4[1], d6[1]}, [r4]<br>
+ vst4.16 {d0[1], d2[1], d4[1], d6[1]}, [r4:16]<br>
+ vst4.16 {d0[1], d2[1], d4[1], d6[1]}, [r4:32]<br>
+ vst4.16 {d0[1], d2[1], d4[1], d6[1]}, [r4:64]<br>
+ vst4.16 {d0[1], d2[1], d4[1], d6[1]}, [r4:128]<br>
+ vst4.16 {d0[1], d2[1], d4[1], d6[1]}, [r4:256]<br>
+<br>
+@ CHECK: vst4.16 {d0[1], d2[1], d4[1], d6[1]}, [r4] @ encoding: [0x84,0xf9,0x6f,0x07]<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vst4.16 {d0[1], d2[1], d4[1], d6[1]}, [r4:16]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vst4.16 {d0[1], d2[1], d4[1], d6[1]}, [r4:32]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vst4.16 {d0[1], d2[1], d4[1], d6[1]}, [r4:64] @ encoding: [0x84,0xf9,0x7f,0x07]<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vst4.16 {d0[1], d2[1], d4[1], d6[1]}, [r4:128]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vst4.16 {d0[1], d2[1], d4[1], d6[1]}, [r4:256]<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vst4.16 {d0[1], d2[1], d4[1], d6[1]}, [r4]!<br>
+ vst4.16 {d0[1], d2[1], d4[1], d6[1]}, [r4:16]!<br>
+ vst4.16 {d0[1], d2[1], d4[1], d6[1]}, [r4:32]!<br>
+ vst4.16 {d0[1], d2[1], d4[1], d6[1]}, [r4:64]!<br>
+ vst4.16 {d0[1], d2[1], d4[1], d6[1]}, [r4:128]!<br>
+ vst4.16 {d0[1], d2[1], d4[1], d6[1]}, [r4:256]!<br>
+<br>
+@ CHECK: vst4.16 {d0[1], d1[1], d2[1], d3[1]}, [r4]! @ encoding: [0x84,0xf9,0x6d,0x07]<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vst4.16 {d0[1], d2[1], d4[1], d6[1]}, [r4:16]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vst4.16 {d0[1], d2[1], d4[1], d6[1]}, [r4:32]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vst4.16 {d0[1], d1[1], d2[1], d3[1]}, [r4:64]! @ encoding: [0x84,0xf9,0x7d,0x07]<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vst4.16 {d0[1], d2[1], d4[1], d6[1]}, [r4:128]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vst4.16 {d0[1], d2[1], d4[1], d6[1]}, [r4:256]!<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vst4.16 {d0[1], d2[1], d4[1], d6[1]}, [r4], r6<br>
+ vst4.16 {d0[1], d2[1], d4[1], d6[1]}, [r4:16], r6<br>
+ vst4.16 {d0[1], d2[1], d4[1], d6[1]}, [r4:32], r6<br>
+ vst4.16 {d0[1], d2[1], d4[1], d6[1]}, [r4:64], r6<br>
+ vst4.16 {d0[1], d2[1], d4[1], d6[1]}, [r4:128], r6<br>
+ vst4.16 {d0[1], d2[1], d4[1], d6[1]}, [r4:256], r6<br>
+<br>
+@ CHECK: vst4.16 {d0[1], d2[1], d4[1], d6[1]}, [r4], r6 @ encoding: [0x84,0xf9,0x66,0x07]<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vst4.16 {d0[1], d2[1], d4[1], d6[1]}, [r4:16], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vst4.16 {d0[1], d2[1], d4[1], d6[1]}, [r4:32], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vst4.16 {d0[1], d2[1], d4[1], d6[1]}, [r4:64], r6 @ encoding: [0x84,0xf9,0x76,0x07]<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vst4.16 {d0[1], d2[1], d4[1], d6[1]}, [r4:128], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64 or omitted<br>
+@ CHECK-ERRORS: vst4.16 {d0[1], d2[1], d4[1], d6[1]}, [r4:256], r6<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vst4.32 {d0, d1, d2, d3}, [r4]<br>
+ vst4.32 {d0, d1, d2, d3}, [r4:16]<br>
+ vst4.32 {d0, d1, d2, d3}, [r4:32]<br>
+ vst4.32 {d0, d1, d2, d3}, [r4:64]<br>
+ vst4.32 {d0, d1, d2, d3}, [r4:128]<br>
+ vst4.32 {d0, d1, d2, d3}, [r4:256]<br>
+<br>
+@ CHECK: vst4.32 {d0, d1, d2, d3}, [r4] @ encoding: [0x04,0xf9,0x8f,0x00]<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted<br>
+@ CHECK-ERRORS: vst4.32 {d0, d1, d2, d3}, [r4:16]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted<br>
+@ CHECK-ERRORS: vst4.32 {d0, d1, d2, d3}, [r4:32]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vst4.32 {d0, d1, d2, d3}, [r4:64] @ encoding: [0x04,0xf9,0x9f,0x00]<br>
+@ CHECK: vst4.32 {d0, d1, d2, d3}, [r4:128] @ encoding: [0x04,0xf9,0xaf,0x00]<br>
+@ CHECK: vst4.32 {d0, d1, d2, d3}, [r4:256] @ encoding: [0x04,0xf9,0xbf,0x00]<br>
+<br>
+ vst4.32 {d0, d1, d2, d3}, [r4]!<br>
+ vst4.32 {d0, d1, d2, d3}, [r4:16]!<br>
+ vst4.32 {d0, d1, d2, d3}, [r4:32]!<br>
+ vst4.32 {d0, d1, d2, d3}, [r4:64]!<br>
+ vst4.32 {d0, d1, d2, d3}, [r4:128]!<br>
+ vst4.32 {d0, d1, d2, d3}, [r4:256]!<br>
+<br>
+@ CHECK: vst4.32 {d0, d1, d2, d3}, [r4]! @ encoding: [0x04,0xf9,0x8d,0x00]<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted<br>
+@ CHECK-ERRORS: vst4.32 {d0, d1, d2, d3}, [r4:16]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted<br>
+@ CHECK-ERRORS: vst4.32 {d0, d1, d2, d3}, [r4:32]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vst4.32 {d0, d1, d2, d3}, [r4:64]! @ encoding: [0x04,0xf9,0x9d,0x00]<br>
+@ CHECK: vst4.32 {d0, d1, d2, d3}, [r4:128]! @ encoding: [0x04,0xf9,0xad,0x00]<br>
+@ CHECK: vst4.32 {d0, d1, d2, d3}, [r4:256]! @ encoding: [0x04,0xf9,0xbd,0x00]<br>
+<br>
+ vst4.32 {d0, d1, d2, d3}, [r4], r6<br>
+ vst4.32 {d0, d1, d2, d3}, [r4:16], r6<br>
+ vst4.32 {d0, d1, d2, d3}, [r4:32], r6<br>
+ vst4.32 {d0, d1, d2, d3}, [r4:64], r6<br>
+ vst4.32 {d0, d1, d2, d3}, [r4:128], r6<br>
+ vst4.32 {d0, d1, d2, d3}, [r4:256], r6<br>
+<br>
+@ CHECK: vst4.32 {d0, d1, d2, d3}, [r4], r6 @ encoding: [0x04,0xf9,0x86,0x00]<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted<br>
+@ CHECK-ERRORS: vst4.32 {d0, d1, d2, d3}, [r4:16], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted<br>
+@ CHECK-ERRORS: vst4.32 {d0, d1, d2, d3}, [r4:32], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vst4.32 {d0, d1, d2, d3}, [r4:64], r6 @ encoding: [0x04,0xf9,0x96,0x00]<br>
+@ CHECK: vst4.32 {d0, d1, d2, d3}, [r4:128], r6 @ encoding: [0x04,0xf9,0xa6,0x00]<br>
+@ CHECK: vst4.32 {d0, d1, d2, d3}, [r4:256], r6 @ encoding: [0x04,0xf9,0xb6,0x00]<br>
+<br>
+ vst4.32 {d0, d2, d4, d6}, [r4]<br>
+ vst4.32 {d0, d2, d4, d6}, [r4:16]<br>
+ vst4.32 {d0, d2, d4, d6}, [r4:32]<br>
+ vst4.32 {d0, d2, d4, d6}, [r4:64]<br>
+ vst4.32 {d0, d2, d4, d6}, [r4:128]<br>
+ vst4.32 {d0, d2, d4, d6}, [r4:256]<br>
+<br>
+@ CHECK: vst4.32 {d0, d2, d4, d6}, [r4] @ encoding: [0x04,0xf9,0x8f,0x01]<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted<br>
+@ CHECK-ERRORS: vst4.32 {d0, d2, d4, d6}, [r4:16]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted<br>
+@ CHECK-ERRORS: vst4.32 {d0, d2, d4, d6}, [r4:32]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vst4.32 {d0, d2, d4, d6}, [r4:64] @ encoding: [0x04,0xf9,0x9f,0x01]<br>
+@ CHECK: vst4.32 {d0, d2, d4, d6}, [r4:128] @ encoding: [0x04,0xf9,0xaf,0x01]<br>
+@ CHECK: vst4.32 {d0, d2, d4, d6}, [r4:256] @ encoding: [0x04,0xf9,0xbf,0x01]<br>
+<br>
+ vst4.32 {d0, d2, d4, d6}, [r4]!<br>
+ vst4.32 {d0, d2, d4, d6}, [r4:16]!<br>
+ vst4.32 {d0, d2, d4, d6}, [r4:32]!<br>
+ vst4.32 {d0, d2, d4, d6}, [r4:64]!<br>
+ vst4.32 {d0, d2, d4, d6}, [r4:128]!<br>
+ vst4.32 {d0, d2, d4, d6}, [r4:256]!<br>
+<br>
+@ CHECK: vst4.32 {d0, d2, d4, d6}, [r4]! @ encoding: [0x04,0xf9,0x8d,0x01]<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted<br>
+@ CHECK-ERRORS: vst4.32 {d0, d2, d4, d6}, [r4:16]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted<br>
+@ CHECK-ERRORS: vst4.32 {d0, d2, d4, d6}, [r4:32]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vst4.32 {d0, d2, d4, d6}, [r4:64]! @ encoding: [0x04,0xf9,0x9d,0x01]<br>
+@ CHECK: vst4.32 {d0, d2, d4, d6}, [r4:128]! @ encoding: [0x04,0xf9,0xad,0x01]<br>
+@ CHECK: vst4.32 {d0, d2, d4, d6}, [r4:256]! @ encoding: [0x04,0xf9,0xbd,0x01]<br>
+<br>
+ vst4.32 {d0, d2, d4, d6}, [r4], r6<br>
+ vst4.32 {d0, d2, d4, d6}, [r4:16], r6<br>
+ vst4.32 {d0, d2, d4, d6}, [r4:32], r6<br>
+ vst4.32 {d0, d2, d4, d6}, [r4:64], r6<br>
+ vst4.32 {d0, d2, d4, d6}, [r4:128], r6<br>
+ vst4.32 {d0, d2, d4, d6}, [r4:256], r6<br>
+<br>
+@ CHECK: vst4.32 {d0, d2, d4, d6}, [r4], r6 @ encoding: [0x04,0xf9,0x86,0x01]<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted<br>
+@ CHECK-ERRORS: vst4.32 {d0, d2, d4, d6}, [r4:16], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted<br>
+@ CHECK-ERRORS: vst4.32 {d0, d2, d4, d6}, [r4:32], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vst4.32 {d0, d2, d4, d6}, [r4:64], r6 @ encoding: [0x04,0xf9,0x96,0x01]<br>
+@ CHECK: vst4.32 {d0, d2, d4, d6}, [r4:128], r6 @ encoding: [0x04,0xf9,0xa6,0x01]<br>
+@ CHECK: vst4.32 {d0, d2, d4, d6}, [r4:256], r6 @ encoding: [0x04,0xf9,0xb6,0x01]<br>
+<br>
+ vst4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4]<br>
+ vst4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:16]<br>
+ vst4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:32]<br>
+ vst4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:64]<br>
+ vst4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:128]<br>
+ vst4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:256]<br>
+<br>
+@ CHECK: vst4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4] @ encoding: [0x84,0xf9,0x8f,0x0b]<br>
+@ CHECK-ERRORS: vst4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:16]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted<br>
+@ CHECK-ERRORS: vst4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:32]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vst4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:64] @ encoding: [0x84,0xf9,0x9f,0x0b]<br>
+@ CHECK: vst4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:128] @ encoding: [0x84,0xf9,0xaf,0x0b]<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted<br>
+@ CHECK-ERRORS: vst4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:256]<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vst4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4]!<br>
+ vst4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:16]!<br>
+ vst4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:32]!<br>
+ vst4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:64]!<br>
+ vst4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:128]!<br>
+ vst4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:256]!<br>
+<br>
+@ CHECK: vst4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4]! @ encoding: [0x84,0xf9,0x8d,0x0b]<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted<br>
+@ CHECK-ERRORS: vst4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:16]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted<br>
+@ CHECK-ERRORS: vst4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:32]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vst4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:64]! @ encoding: [0x84,0xf9,0x9d,0x0b]<br>
+@ CHECK: vst4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:128]! @ encoding: [0x84,0xf9,0xad,0x0b]<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted<br>
+@ CHECK-ERRORS: vst4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:256]!<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vst4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4], r6<br>
+ vst4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:16], r6<br>
+ vst4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:32], r6<br>
+ vst4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:64], r6<br>
+ vst4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:128], r6<br>
+ vst4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:256], r6<br>
+<br>
+@ CHECK: vst4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4], r6 @ encoding: [0x84,0xf9,0x86,0x0b]<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted<br>
+@ CHECK-ERRORS: vst4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:16], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted<br>
+@ CHECK-ERRORS: vst4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:32], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vst4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:64], r6 @ encoding: [0x84,0xf9,0x96,0x0b]<br>
+@ CHECK: vst4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:128], r6 @ encoding: [0x84,0xf9,0xa6,0x0b]<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted<br>
+@ CHECK-ERRORS: vst4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:256], r6<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4]<br>
+ vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:16]<br>
+ vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:32]<br>
+ vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:64]<br>
+ vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:128]<br>
+ vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:256]<br>
+<br>
+@ CHECK: vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4] @ encoding: [0x84,0xf9,0xcf,0x0b]<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted<br>
+@ CHECK-ERRORS: vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:16]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted<br>
+@ CHECK-ERRORS: vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:32]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:64] @ encoding: [0x84,0xf9,0xdf,0x0b]<br>
+@ CHECK: vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:128] @ encoding: [0x84,0xf9,0xef,0x0b]<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted<br>
+@ CHECK-ERRORS: vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:256]<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4]!<br>
+ vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:16]!<br>
+ vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:32]!<br>
+ vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:64]!<br>
+ vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:128]!<br>
+ vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:256]!<br>
+<br>
+@ CHECK: vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4]! @ encoding: [0x84,0xf9,0xcd,0x0b]<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted<br>
+@ CHECK-ERRORS: vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:16]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted<br>
+@ CHECK-ERRORS: vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:32]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:64]! @ encoding: [0x84,0xf9,0xdd,0x0b]<br>
+@ CHECK: vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:128]! @ encoding: [0x84,0xf9,0xed,0x0b]<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted<br>
+@ CHECK-ERRORS: vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:256]!<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4], r6<br>
+ vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:16], r6<br>
+ vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:32], r6<br>
+ vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:64], r6<br>
+ vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:128], r6<br>
+ vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:256], r6<br>
+<br>
+@ CHECK: vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4], r6 @ encoding: [0x84,0xf9,0xc6,0x0b]<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted<br>
+@ CHECK-ERRORS: vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:16], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted<br>
+@ CHECK-ERRORS: vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:32], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:64], r6 @ encoding: [0x84,0xf9,0xd6,0x0b]<br>
+@ CHECK: vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:128], r6 @ encoding: [0x84,0xf9,0xe6,0x0b]<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted<br>
+@ CHECK-ERRORS: vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:256], r6<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vst4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4]!<br>
+ vst4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:16]!<br>
+ vst4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:32]!<br>
+ vst4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:64]!<br>
+ vst4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:128]!<br>
+ vst4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:256]!<br>
+<br>
+@ CHECK: vst4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4]! @ encoding: [0x84,0xf9,0x8d,0x0b]<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted<br>
+@ CHECK-ERRORS: vst4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:16]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted<br>
+@ CHECK-ERRORS: vst4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:32]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vst4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:64]! @ encoding: [0x84,0xf9,0x9d,0x0b]<br>
+@ CHECK: vst4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:128]! @ encoding: [0x84,0xf9,0xad,0x0b]<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted<br>
+@ CHECK-ERRORS: vst4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:256]!<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vst4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4], r6<br>
+ vst4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:16], r6<br>
+ vst4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:32], r6<br>
+ vst4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:64], r6<br>
+ vst4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:128], r6<br>
+ vst4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:256], r6<br>
+<br>
+@ CHECK: vst4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4], r6 @ encoding: [0x84,0xf9,0x86,0x0b]<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted<br>
+@ CHECK-ERRORS: vst4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:16], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted<br>
+@ CHECK-ERRORS: vst4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:32], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vst4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:64], r6 @ encoding: [0x84,0xf9,0x96,0x0b]<br>
+@ CHECK: vst4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:128], r6 @ encoding: [0x84,0xf9,0xa6,0x0b]<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted<br>
+@ CHECK-ERRORS: vst4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:256], r6<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4]<br>
+ vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:16]<br>
+ vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:32]<br>
+ vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:64]<br>
+ vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:128]<br>
+ vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:256]<br>
+<br>
+@ CHECK: vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4] @ encoding: [0x84,0xf9,0xcf,0x0b]<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted<br>
+@ CHECK-ERRORS: vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:16]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted<br>
+@ CHECK-ERRORS: vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:32]<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:64] @ encoding: [0x84,0xf9,0xdf,0x0b]<br>
+@ CHECK: vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:128] @ encoding: [0x84,0xf9,0xef,0x0b]<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted<br>
+@ CHECK-ERRORS: vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:256]<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4]!<br>
+ vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:16]!<br>
+ vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:32]!<br>
+ vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:64]!<br>
+ vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:128]!<br>
+ vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:256]!<br>
+<br>
+@ CHECK: vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4]! @ encoding: [0x84,0xf9,0xcd,0x0b]<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted<br>
+@ CHECK-ERRORS: vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:16]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted<br>
+@ CHECK-ERRORS: vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:32]!<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:64]! @ encoding: [0x84,0xf9,0xdd,0x0b]<br>
+@ CHECK: vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:128]! @ encoding: [0x84,0xf9,0xed,0x0b]<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted<br>
+@ CHECK-ERRORS: vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:256]!<br>
+@ CHECK-ERRORS: ^<br>
+<br>
+ vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4], r6<br>
+ vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:16], r6<br>
+ vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:32], r6<br>
+ vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:64], r6<br>
+ vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:128], r6<br>
+ vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:256], r6<br>
+<br>
+@ CHECK: vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4], r6 @ encoding: [0x84,0xf9,0xc6,0x0b]<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted<br>
+@ CHECK-ERRORS: vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:16], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted<br>
+@ CHECK-ERRORS: vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:32], r6<br>
+@ CHECK-ERRORS: ^<br>
+@ CHECK: vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:64], r6 @ encoding: [0x84,0xf9,0xd6,0x0b]<br>
+@ CHECK: vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:128], r6 @ encoding: [0x84,0xf9,0xe6,0x0b]<br>
+@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted<br>
+@ CHECK-ERRORS: vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:256], r6<br>
+@ CHECK-ERRORS: ^<br>
<br>
<br>
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</blockquote></div><br></div>