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</o:shapelayout></xml><![endif]--></head><body lang=EN-US link=blue vlink=purple><div class=WordSection1><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'>Jiangning,<o:p></o:p></span></p><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'><o:p> </o:p></span></p><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'>I believe “ld1/st1 + rev” or “ldr” on big-endian should be controlled by pattern matching and addressed by a separate patch... Can you point me to the review thread you mentioned?<o:p></o:p></span></p><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'><o:p> </o:p></span></p><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'>I looked into ARM64 backend. All vector types are promoted to v2i64/v2i32 and the pattern matcher emits ldr/str instructions.<o:p></o:p></span></p><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'><o:p> </o:p></span></p><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'>My assumption is Linux by default is configured to support unaligned accesses. Do you mean I should add –aarch64-no-strict-align to the command line in my test? Can you elaborate a little bit about “the ld1/st1 CHECK should be guaranteed for both little-endian and big-endian”?<o:p></o:p></span></p><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'><o:p> </o:p></span></p><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'>Thanks,<o:p></o:p></span></p><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'>Zhaoshi<o:p></o:p></span></p><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'><o:p> </o:p></span></p><p class=MsoNormal><b><span style='font-size:10.0pt;font-family:"Tahoma","sans-serif"'>From:</span></b><span style='font-size:10.0pt;font-family:"Tahoma","sans-serif"'> Jiangning Liu [mailto:liujiangning1@gmail.com] <br><b>Sent:</b> Tuesday, April 08, 2014 23:36<br><b>To:</b> Zhaoshi<br><b>Cc:</b> llvm-commits@cs.uiuc.edu for LLVM<br><b>Subject:</b> Re: [Patch] [AArch64] Implement allowsUnalignedMemoryAccesses()<o:p></o:p></span></p><p class=MsoNormal><o:p> </o:p></p><div><div><p class=MsoNormal><span style='font-family:"Arial","sans-serif"'>Hi Zhaoshi,<o:p></o:p></span></p></div><div><p class=MsoNormal><span style='font-family:"Arial","sans-serif"'><o:p> </o:p></span></p></div><div><p class=MsoNormal><span style='font-family:"Arial","sans-serif"'>One more thing...<o:p></o:p></span></p></div><div><p class=MsoNormal><span style='font-family:"Arial","sans-serif"'><o:p> </o:p></span></p></div><div><p class=MsoNormal><span style='font-family:"Arial","sans-serif"'>Currently the pattern match only generates ld1/st1, which is inefficient for big-endian, and I think it is going to be changed soon to ldr/str by another big-endian support patch. You may have noticed there is another patch review thread relates to big-endian. I prefer your case stays with ld1/st1, and ask another patch to fix that all together, because that's all about big-endian.<o:p></o:p></span></p></div><div><p class=MsoNormal><span style='font-family:"Arial","sans-serif"'><o:p> </o:p></span></p></div><div><p class=MsoNormal><span style='font-family:"Arial","sans-serif"'>For performance wise, you can hack the followings in AArch64IntrNEON.td in advance to verify ldr/str.<o:p></o:p></span></p></div><div><p class=MsoNormal><span style='font-family:"Arial","sans-serif"'><o:p> </o:p></span></p></div><div><div><p class=MsoNormal><span style='font-family:"Arial","sans-serif"'>def : Pat<(v2f64 (load GPR64xsp:$addr)), (LD1_2D GPR64xsp:$addr)>;</span><o:p></o:p></p></div><div><p class=MsoNormal><span style='font-family:"Arial","sans-serif"'>def : Pat<(v2i64 (load GPR64xsp:$addr)), (LD1_2D GPR64xsp:$addr)>;</span><o:p></o:p></p></div><div><p class=MsoNormal><o:p> </o:p></p></div><div><p class=MsoNormal><span style='font-family:"Arial","sans-serif"'>def : Pat<(v4f32 (load GPR64xsp:$addr)), (LD1_4S GPR64xsp:$addr)>;</span><o:p></o:p></p></div><div><p class=MsoNormal><span style='font-family:"Arial","sans-serif"'>def : Pat<(v4i32 (load GPR64xsp:$addr)), (LD1_4S GPR64xsp:$addr)>;</span><o:p></o:p></p></div><div><p class=MsoNormal><o:p> </o:p></p></div><div><p class=MsoNormal><span style='font-family:"Arial","sans-serif"'>def : Pat<(v8i16 (load GPR64xsp:$addr)), (LD1_8H GPR64xsp:$addr)>;</span><o:p></o:p></p></div><div><p class=MsoNormal><span style='font-family:"Arial","sans-serif"'>def : Pat<(v16i8 (load GPR64xsp:$addr)), (LD1_16B GPR64xsp:$addr)>;</span><o:p></o:p></p></div><div><p class=MsoNormal><o:p> </o:p></p></div><div><p class=MsoNormal><span style='font-family:"Arial","sans-serif"'>def : Pat<(v1f64 (load GPR64xsp:$addr)), (LD1_1D GPR64xsp:$addr)>;</span><o:p></o:p></p></div><div><p class=MsoNormal><span style='font-family:"Arial","sans-serif"'>def : Pat<(v1i64 (load GPR64xsp:$addr)), (LD1_1D GPR64xsp:$addr)>;</span><o:p></o:p></p></div><div><p class=MsoNormal><o:p> </o:p></p></div><div><p class=MsoNormal><span style='font-family:"Arial","sans-serif"'>def : Pat<(v2f32 (load GPR64xsp:$addr)), (LD1_2S GPR64xsp:$addr)>;</span><o:p></o:p></p></div><div><p class=MsoNormal><span style='font-family:"Arial","sans-serif"'>def : Pat<(v2i32 (load GPR64xsp:$addr)), (LD1_2S GPR64xsp:$addr)>;</span><o:p></o:p></p></div><div><p class=MsoNormal><o:p> </o:p></p></div><div><p class=MsoNormal><span style='font-family:"Arial","sans-serif"'>def : Pat<(v4i16 (load GPR64xsp:$addr)), (LD1_4H GPR64xsp:$addr)>;</span><o:p></o:p></p></div><div><p class=MsoNormal><span style='font-family:"Arial","sans-serif"'>def : Pat<(v8i8 (load GPR64xsp:$addr)), (LD1_8B GPR64xsp:$addr)>;</span><o:p></o:p></p></div></div><div><p class=MsoNormal><span style='font-family:"Arial","sans-serif"'><o:p> </o:p></span></p></div><div><p class=MsoNormal><span style='font-family:"Arial","sans-serif"'>This is just in case the performance impact after fully enabling big-endian on AArch64.<o:p></o:p></span></p></div><div><p class=MsoNormal><span style='font-family:"Arial","sans-serif"'><o:p> </o:p></span></p></div><div><p class=MsoNormal><span style='font-family:"Arial","sans-serif"'>Thanks,<o:p></o:p></span></p></div><div><p class=MsoNormal><span style='font-family:"Arial","sans-serif"'>-Jiangning<o:p></o:p></span></p></div></div><div><p class=MsoNormal style='margin-bottom:12.0pt'><o:p> </o:p></p><div><p class=MsoNormal>2014-04-09 12:45 GMT+08:00 Jiangning Liu <<a href="mailto:liujiangning1@gmail.com" target="_blank">liujiangning1@gmail.com</a>>:<o:p></o:p></p><div><div><p class=MsoNormal><span style='font-family:"Arial","sans-serif"'>Hi Zhaoshi,<o:p></o:p></span></p></div><div><p class=MsoNormal><span style='font-family:"Arial","sans-serif"'><o:p> </o:p></span></p></div><div><p class=MsoNormal><span style='font-family:"Arial","sans-serif"'>For both little-endian and big-endian, we need to generate instructions as if ldr/str. For little-endian, ldr/str is the same as ld1/st1, while for big-endian they have different behaviours. So if we generate ld1/st1 for big-endian, we should have to generate "rev" following them to keep the reversed in-register layout.<o:p></o:p></span></p></div><div><p class=MsoNormal><span style='font-family:"Arial","sans-serif"'><o:p> </o:p></span></p></div><div><p class=MsoNormal><span style='font-family:"Arial","sans-serif"'>Your code shows you are saying Linux should be always configured as non-strict mode for hardware, so for big-endian the choice between "ldr/str" and "ld1/st1 + rev" will depend on cost estimate. Therefore, for your test case unaligned-vector-ld1-st1.ll,<o:p></o:p></span></p></div><div><p class=MsoNormal><span style='font-family:"Arial","sans-serif"'><o:p> </o:p></span></p></div><div><p class=MsoNormal style='margin-bottom:12.0pt'><span style='font-family:"Arial","sans-serif"'>+; RUN: llc < %s -mtriple=aarch64_be-none-linux-gnu -mattr=+neon -o - | FileCheck %s</span><o:p></o:p></p></div><div><p class=MsoNormal><span style='font-family:"Arial","sans-serif"'>It would be better if you can add -aarch64-strict-align in command line, and the ld1/st1 CHECK should be guaranteed for both little-endian and big-endian. Also, I don't see you have tests covering those three newly added opts you added.</span><o:p></o:p></p></div><div><p class=MsoNormal><o:p> </o:p></p></div><div><p class=MsoNormal><span style='font-family:"Arial","sans-serif"'>Thanks,</span><o:p></o:p></p></div><div><p class=MsoNormal><span style='font-family:"Arial","sans-serif"'>-Jiangning</span><o:p></o:p></p></div><div><p class=MsoNormal><span style='font-family:"Arial","sans-serif"'><o:p> </o:p></span></p></div></div><div><p class=MsoNormal style='margin-bottom:12.0pt'><o:p> </o:p></p><div><p class=MsoNormal>2014-04-08 9:24 GMT+08:00 <<a href="mailto:zhaoshiz@codeaurora.org" target="_blank">zhaoshiz@codeaurora.org</a>>:<o:p></o:p></p><div><div><p class=MsoNormal>Hi,<br><br>This patch should enable unaligned accesses of vector types on AArch64.<br>Please help review.<br><br>Thanks,<br>Zhaoshi<o:p></o:p></p></div></div><p class=MsoNormal style='margin-bottom:12.0pt'>_______________________________________________<br>llvm-commits mailing list<br><a href="mailto:llvm-commits@cs.uiuc.edu" target="_blank">llvm-commits@cs.uiuc.edu</a><br><a href="http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits" target="_blank">http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits</a><o:p></o:p></p></div><p class=MsoNormal><span style='color:#888888'><br><br clear=all><span class=hoenzb><o:p></o:p></span></span></p><div><p class=MsoNormal><o:p> </o:p></p></div><p class=MsoNormal><span class=hoenzb><span style='color:#888888'>-- </span><o:p></o:p></span></p><div><p class=MsoNormal><span style='font-family:"Courier New";color:#888888'>Thanks,</span><o:p></o:p></p><div><p class=MsoNormal><span style='font-family:"Courier New";color:#888888'>-Jiangning</span><span style='color:#888888'><o:p></o:p></span></p></div></div></div></div><p class=MsoNormal><br><br clear=all><o:p></o:p></p><div><p class=MsoNormal><o:p> </o:p></p></div><p class=MsoNormal>-- <o:p></o:p></p><div><p class=MsoNormal><span style='font-family:"Courier New"'>Thanks,</span><o:p></o:p></p><div><p class=MsoNormal><span style='font-family:"Courier New"'>-Jiangning</span><o:p></o:p></p></div></div></div></div></body></html>