<html><head><meta http-equiv="Content-Type" content="text/html charset=windows-1252"></head><body style="word-wrap: break-word; -webkit-nbsp-mode: space; -webkit-line-break: after-white-space;"><br><div><div>On Mar 25, 2014, at 10:50 AM, Dan Gohman <<a href="mailto:dan433584@gmail.com">dan433584@gmail.com</a>> wrote:</div><br class="Apple-interchange-newline"><blockquote type="cite"><div dir="ltr"><br><div class="gmail_extra"><br><br><div class="gmail_quote">On Tue, Mar 25, 2014 at 7:24 AM, Rafael Espíndola <span dir="ltr"><<a href="mailto:rafael.espindola@gmail.com" target="_blank">rafael.espindola@gmail.com</a>></span> wrote:<br>
<blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex"><div class="">On 25 March 2014 09:49, Dan Gohman <<a href="mailto:dan433584@gmail.com">dan433584@gmail.com</a>> wrote:<br>
> Hi Lang,<br>
><br>
> I can reproduce the performance regression on fourinarow, at least. With the<br>
> patch, the code size and static instruction count of the benchmark's one<br>
> embarassingly-hot function is lower, the dynamic instruction count is lower,<br>
> and the stack frame is smaller, but it still runs slower. Instruction<br>
> selection is basically the same, except that there are fewer cmovs. There<br>
> appears to be a minor difference in instruction scheduling in the hot<br>
> function. The regression disappeared when I experimented with non-default<br>
> values for -pre-RA-sched. However, I'm not prepared for the adventure of<br>
> changing the instruction scheduler's heuristics at this time, so I'll just<br>
> let this patch go for now.<br>
<br>
</div>Do you have a small .ll testcase?<br></blockquote><div><br></div><div>Not handy anymore, but it's just MultiSource/Benchmarks/<div>FreeBench/fourinarow/fourinarow with -O3 -flto on x86-64.<br></div></div></div></div></div></blockquote></div><br><div>fourinarow is jittery, sensitive to register pressure, and doesn’t like codegen changes. Were there several other significant regressions and no significant improvements? Were the results overall bad on non -flto builds too? Or did we just have bad luck with LTO? Are there regressions on any real benchmarks?</div><div><br></div><div>Is there any reason to believe this patch is chronically increasing register pressure?</div><div><br></div><div>The default SD scheduler should be simply preserving IR order. If the patch fundamentally makes sense, and the generated code before register coalescing looks better by simple metrics: dynamic instruction count and critical path, then the only way forward is to file a bug against the register coalescer and MI scheduler (which are often two sides of the same problem).</div><div><br></div><div>I don’t think it’s a good idea to retune these passes to enable unrelated checkins just to make the test-suite numbers look better. That only makes it more difficult to solve the codegen problems in robust ways.</div><div><br></div><div>-Andy</div></body></html>