<p dir="ltr">I can see it on a couple of the others as well. I'll take a look. I think the testcase may just need to be relaxed. </p>
<div class="gmail_quote">On Apr 3, 2014 7:03 AM, "Daniel Sanders" <<a href="mailto:Daniel.Sanders@imgtec.com">Daniel.Sanders@imgtec.com</a>> wrote:<br type="attribution"><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">
Hi Eric,<br>
<br>
I think this commit caused llvm-mips-linux buildbot to turn red and I don't think it has sent an email (I'm also on the blamelist and I haven't received one).<br>
The build is <a href="http://lab.llvm.org:8011/builders/llvm-mips-linux/builds/8028" target="_blank">http://lab.llvm.org:8011/builders/llvm-mips-linux/builds/8028</a><br>
<br>
I've re-run the test on an X86 with -march=mips added to the llc command and it seems that an extra entry appears in the line information between the CHECK and the CHECK-NEXT:<br>
Address Line Column File ISA Discriminator Flags<br>
------------------ ------ ------ ------ --- ------------- -------------<br>
0x0000000000000000 1 0 1 0 0 is_stmt<br>
0x0000000000000000 1 0 1 0 0 is_stmt prologue_end <--- extra line<br>
0x0000000000000010 2 0 1 0 0 is_stmt<br>
0x0000000000000018 4 0 1 0 0 is_stmt<br>
0x0000000000000020 6 0 1 0 0 is_stmt<br>
0x0000000000000034 6 0 1 0 0 is_stmt end_sequence<br>
<br>
> -----Original Message-----<br>
> From: <a href="mailto:llvm-commits-bounces@cs.uiuc.edu">llvm-commits-bounces@cs.uiuc.edu</a> [mailto:<a href="mailto:llvm-commits-">llvm-commits-</a><br>
> <a href="mailto:bounces@cs.uiuc.edu">bounces@cs.uiuc.edu</a>] On Behalf Of Eric Christopher<br>
> Sent: 03 April 2014 13:12<br>
> To: <a href="mailto:llvm-commits@cs.uiuc.edu">llvm-commits@cs.uiuc.edu</a><br>
> Subject: [llvm] r205529 - Fix for PR 19261:<br>
><br>
> Author: echristo<br>
> Date: Thu Apr 3 07:11:51 2014<br>
> New Revision: 205529<br>
><br>
> URL: <a href="http://llvm.org/viewvc/llvm-project?rev=205529&view=rev" target="_blank">http://llvm.org/viewvc/llvm-project?rev=205529&view=rev</a><br>
> Log:<br>
> Fix for PR 19261:<br>
><br>
> llc doesn't generate nodes for unconditional fall-through branches for targets<br>
> without FastISel implementation (X86 has it, but can be disabled by<br>
> "-fast-isel=false") in SelectionDAGBuilder::visitBr().<br>
><br>
> So for line 4 in the following testcase<br>
><br>
> 1: void foo(int i){<br>
> 2: switch(i){<br>
> 3: default:<br>
> 4: break;<br>
> 5: }<br>
> 6: return;<br>
> 7: }<br>
><br>
> there is no corresponding line in .debug_line section, and a debugger cannot<br>
> set a breakpoint at line 4.<br>
><br>
> Fix this by always emitting a branch when we're not optimizing and add a<br>
> testcase to ensure that there's code on every line we'd want to break.<br>
><br>
> Patch by Daniil Fukalov.<br>
><br>
> Added:<br>
> llvm/trunk/test/DebugInfo/unconditional-branch.ll<br>
> Modified:<br>
> llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp<br>
><br>
> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp<br>
> URL: <a href="http://llvm.org/viewvc/llvm-" target="_blank">http://llvm.org/viewvc/llvm-</a><br>
> project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp?re<br>
> v=205529&r1=205528&r2=205529&view=diff<br>
> ==========================================================<br>
> ====================<br>
> --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp<br>
> (original)<br>
> +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp Thu<br>
> Apr<br>
> +++ 3 07:11:51 2014<br>
> @@ -1571,8 +1571,9 @@ void SelectionDAGBuilder::visitBr(const<br>
> // Update machine-CFG edges.<br>
> BrMBB->addSuccessor(Succ0MBB);<br>
><br>
> - // If this is not a fall-through branch, emit the branch.<br>
> - if (Succ0MBB != NextBlock)<br>
> + // If this is not a fall-through branch or optimizations are switched off,<br>
> + // emit the branch.<br>
> + if (Succ0MBB != NextBlock || TM.getOptLevel() == CodeGenOpt::None)<br>
> DAG.setRoot(DAG.getNode(ISD::BR, getCurSDLoc(),<br>
> MVT::Other, getControlRoot(),<br>
> DAG.getBasicBlock(Succ0MBB)));<br>
><br>
> Added: llvm/trunk/test/DebugInfo/unconditional-branch.ll<br>
> URL: <a href="http://llvm.org/viewvc/llvm-" target="_blank">http://llvm.org/viewvc/llvm-</a><br>
> project/llvm/trunk/test/DebugInfo/unconditional-<br>
> branch.ll?rev=205529&view=auto<br>
> ==========================================================<br>
> ====================<br>
> --- llvm/trunk/test/DebugInfo/unconditional-branch.ll (added)<br>
> +++ llvm/trunk/test/DebugInfo/unconditional-branch.ll Thu Apr 3<br>
> +++ 07:11:51 2014<br>
> @@ -0,0 +1,64 @@<br>
> +; REQUIRES: object-emission<br>
> +; PR 19261<br>
> +<br>
> +; RUN: %llc_dwarf -fast-isel=false -O0 -filetype=obj < %s > %t ; RUN:<br>
> +llvm-dwarfdump %t | FileCheck %s<br>
> +<br>
> +; CHECK: {{0x[0-9a-f]+}} 1 0 1 0 0 is_stmt<br>
> +; CHECK-NEXT: {{0x[0-9a-f]+}} 2 0 1 0 0 is_stmt<br>
> +; CHECK-NEXT: {{0x[0-9a-f]+}} 4 0 1 0 0 is_stmt<br>
> +<br>
> +; IR generated from clang -O0 -g with the following source:<br>
> +;void foo(int i){<br>
> +; switch(i){<br>
> +; default:<br>
> +; break;<br>
> +; }<br>
> +; return;<br>
> +;}<br>
> +<br>
> +; Function Attrs: nounwind<br>
> +define void @foo(i32 %i) #0 {<br>
> +entry:<br>
> + %i.addr = alloca i32, align 4<br>
> + store i32 %i, i32* %i.addr, align 4<br>
> + call void @llvm.dbg.declare(metadata !{i32* %i.addr}, metadata !12),<br>
> +!dbg !13<br>
> + %0 = load i32* %i.addr, align 4, !dbg !14<br>
> + switch i32 %0, label %sw.default [<br>
> + ], !dbg !14<br>
> +<br>
> +sw.default: ; preds = %entry<br>
> + br label %sw.epilog, !dbg !15<br>
> +<br>
> +sw.epilog: ; preds = %sw.default<br>
> + ret void, !dbg !17<br>
> +}<br>
> +<br>
> +; Function Attrs: nounwind readnone<br>
> +declare void @llvm.dbg.declare(metadata, metadata) #1<br>
> +<br>
> +attributes #0 = { nounwind "less-precise-fpmad"="false"<br>
> +"no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf"<br>
> +"no-infs-fp-math"="false" "no-nans-fp-math"="false"<br>
> +"stack-protector-buffer-size"="8" "unsafe-fp-math"="false"<br>
> +"use-soft-float"="false" } attributes #1 = { nounwind readnone }<br>
> +<br>
> +!<a href="http://llvm.dbg.cu" target="_blank">llvm.dbg.cu</a> = !{!0}<br>
> +!llvm.module.flags = !{!9, !10}<br>
> +!llvm.ident = !{!11}<br>
> +<br>
> +!0 = metadata !{i32 786449, metadata !1, i32 12, metadata !"clang<br>
> +version 3.5.0 (204712)", i1 false, metadata !"", i32 0, metadata !2,<br>
> +metadata !2, metadata !3, metadata !2, metadata !2, metadata !"", i32<br>
> +1} ; [ DW_TAG_compile_unit ] [D:\work\EPRs\396363/test.c]<br>
> [DW_LANG_C99]<br>
> +!1 = metadata !{metadata !"test.c", metadata<br>
> +!"D:\5Cwork\5CEPRs\5C396363"}<br>
> +!2 = metadata !{}<br>
> +!3 = metadata !{metadata !4}<br>
> +!4 = metadata !{i32 786478, metadata !1, metadata !5, metadata !"foo",<br>
> metadata !"foo", metadata !"", i32 1, metadata !6, i1 false, i1 true, i32 0, i32 0,<br>
> null, i32 256, i1 false, void (i32)* @foo, null, null, metadata !2, i32 1} ; [<br>
> DW_TAG_subprogram ] [line 1] [def] [foo]<br>
> +!5 = metadata !{i32 786473, metadata !1} ; [ DW_TAG_file_type ]<br>
> [D:\work\EPRs\396363/test.c]<br>
> +!6 = metadata !{i32 786453, i32 0, null, metadata !"", i32 0, i64 0,<br>
> +i64 0, i64 0, i32 0, null, metadata !7, i32 0, null, null, null} ; [<br>
> +DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]<br>
> +!7 = metadata !{null, metadata !8}<br>
> +!8 = metadata !{i32 786468, null, null, metadata !"int", i32 0, i64 32,<br>
> +i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] [int] [line 0, size<br>
> +32, align 32, offset 0, enc DW_ATE_signed]<br>
> +!9 = metadata !{i32 2, metadata !"Dwarf Version", i32 4}<br>
> +!10 = metadata !{i32 1, metadata !"Debug Info Version", i32 1}<br>
> +!11 = metadata !{metadata !"clang version 3.5.0 (204712)"}<br>
> +!12 = metadata !{i32 786689, metadata !4, metadata !"i", metadata !5,<br>
> +i32 16777217, metadata !8, i32 0, i32 0} ; [ DW_TAG_arg_variable ] [i]<br>
> +[line 1]<br>
> +!13 = metadata !{i32 1, i32 0, metadata !4, null}<br>
> +!14 = metadata !{i32 2, i32 0, metadata !4, null}<br>
> +!15 = metadata !{i32 4, i32 0, metadata !16, null}<br>
> +!16 = metadata !{i32 786443, metadata !1, metadata !4, i32 2, i32 0,<br>
> +i32 0, i32 0} ; [ DW_TAG_lexical_block ] [D:\work\EPRs\396363/test.c]<br>
> +!17 = metadata !{i32 6, i32 0, metadata !4, null}<br>
><br>
><br>
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</blockquote></div>