<html><head><meta http-equiv="Content-Type" content="text/html charset=us-ascii"></head><body style="word-wrap: break-word; -webkit-nbsp-mode: space; -webkit-line-break: after-white-space;">Hi James,<br><div apple-content-edited="true">
</div>
<br><div><div>On Apr 2, 2014, at 3:17 AM, James Molloy <<a href="mailto:james@jamesmolloy.co.uk">james@jamesmolloy.co.uk</a>> wrote:</div><br class="Apple-interchange-newline"><blockquote type="cite"><div dir="ltr">Hi Quentin,<div><br></div><div>Thanks for adding those extra comments. However, I believe LLVM policy is to not have Apple <a href="rdar://">rdar://</a> links at all in the source code. Could you therefore remove these lines?</div></div></blockquote><div>Sure!</div><div><br></div><div>Here you go:</div><div><div style="margin: 0px; font-size: 11px; font-family: Menlo;">Committed revision 205435.</div></div><div><br></div>Thanks,</div><div>-Quentin<br><blockquote type="cite"><div dir="ltr">
<div><br></div><div><span style="font-family:arial,sans-serif;font-size:13px"> // More information are available in the design document attached to</span><br style="font-family:arial,sans-serif;font-size:13px"><span style="font-family:arial,sans-serif;font-size:13px"> // <a href="rdar://11956674">rdar://11956674</a></span><br>
</div><div><span style="font-family:arial,sans-serif;font-size:13px"><br></span></div><div><font face="arial, sans-serif">Thanks,</font></div><div><font face="arial, sans-serif"><br></font></div><div><font face="arial, sans-serif">James</font></div>
</div><div class="gmail_extra"><br><br><div class="gmail_quote">On 2 April 2014 02:02, Quentin Colombet <span dir="ltr"><<a href="mailto:qcolombet@apple.com" target="_blank">qcolombet@apple.com</a>></span> wrote:<br>
<blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">Author: qcolombet<br>
Date: Tue Apr 1 20:02:28 2014<br>
New Revision: 205379<br>
<br>
URL: <a href="http://llvm.org/viewvc/llvm-project?rev=205379&view=rev" target="_blank">http://llvm.org/viewvc/llvm-project?rev=205379&view=rev</a><br>
Log:<br>
[ARM64][CollectLOH] Add some comments to explain how the LOHs<br>
framework works (for the compiler part), since the design<br>
document is not available.<br>
<br>
Modified:<br>
llvm/trunk/lib/MC/MCLinkerOptimizationHint.cpp<br>
llvm/trunk/lib/Target/ARM64/ARM64CollectLOH.cpp<br>
<br>
Modified: llvm/trunk/lib/MC/MCLinkerOptimizationHint.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCLinkerOptimizationHint.cpp?rev=205379&r1=205378&r2=205379&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCLinkerOptimizationHint.cpp?rev=205379&r1=205378&r2=205379&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/MC/MCLinkerOptimizationHint.cpp (original)<br>
+++ llvm/trunk/lib/MC/MCLinkerOptimizationHint.cpp Tue Apr 1 20:02:28 2014<br>
@@ -14,6 +14,14 @@<br>
<br>
using namespace llvm;<br>
<br>
+// Each LOH is composed by, in this order (each field is encoded using ULEB128):<br>
+// - Its kind.<br>
+// - Its number of arguments (let say N).<br>
+// - Its arg1.<br>
+// - ...<br>
+// - Its argN.<br>
+// <arg1> to <argN> are absolute addresses in the object file, i.e.,<br>
+// relative addresses from the beginning of the object file.<br>
void MCLOHDirective::Emit_impl(raw_ostream &OutStream,<br>
const MachObjectWriter &ObjWriter,<br>
const MCAsmLayout &Layout) const {<br>
<br>
Modified: llvm/trunk/lib/Target/ARM64/ARM64CollectLOH.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM64/ARM64CollectLOH.cpp?rev=205379&r1=205378&r2=205379&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM64/ARM64CollectLOH.cpp?rev=205379&r1=205378&r2=205379&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/ARM64/ARM64CollectLOH.cpp (original)<br>
+++ llvm/trunk/lib/Target/ARM64/ARM64CollectLOH.cpp Tue Apr 1 20:02:28 2014<br>
@@ -11,7 +11,42 @@<br>
// This pass should be run at the very end of the compilation flow, just before<br>
// assembly printer.<br>
// To be useful for the linker, the LOH must be printed into the assembly file.<br>
-// Currently supported LOH are:<br>
+//<br>
+// A LOH describes a sequence of instructions that may be optimized by the<br>
+// linker.<br>
+// This same sequence cannot be optimized by the compiler because some of<br>
+// the information will be known at link time.<br>
+// For instance, consider the following sequence:<br>
+// L1: adrp xA, sym@PAGE<br>
+// L2: add xB, xA, sym@PAGEOFF<br>
+// L3: ldr xC, [xB, #imm]<br>
+// This sequence can be turned into:<br>
+// A literal load if sym@PAGE + sym@PAGEOFF + #imm - address(L3) is < 1MB:<br>
+// L3: ldr xC, sym+#imm<br>
+// It may also be turned into either the following more efficient<br>
+// code sequences:<br>
+// - If sym@PAGEOFF + #imm fits the encoding space of L3.<br>
+// L1: adrp xA, sym@PAGE<br>
+// L3: ldr xC, [xB, sym@PAGEOFF + #imm]<br>
+// - If sym@PAGE + sym@PAGEOFF - address(L1) < 1MB:<br>
+// L1: adr xA, sym<br>
+// L3: ldr xC, [xB, #imm]<br>
+//<br>
+// To be valid a LOH must meet all the requirements needed by all the related<br>
+// possible linker transformations.<br>
+// For instance, using the running example, the constraints to emit<br>
+// ".loh AdrpAddLdr" are:<br>
+// - L1, L2, and L3 instructions are of the expected type, i.e.,<br>
+// respectively ADRP, ADD (immediate), and LD.<br>
+// - The result of L1 is used only by L2.<br>
+// - The register argument (xA) used in the ADD instruction is defined<br>
+// only by L1.<br>
+// - The result of L2 is used only by L3.<br>
+// - The base address (xB) in L3 is defined only L2.<br>
+// - The ADRP in L1 and the ADD in L2 must reference the same symbol using<br>
+// @PAGE/@PAGEOFF with no additional constants<br>
+//<br>
+// Currently supported LOHs are:<br>
// * So called non-ADRP-related:<br>
// - .loh AdrpAddLdr L1, L2, L3:<br>
// L1: adrp xA, sym@PAGE<br>
@@ -39,12 +74,28 @@<br>
// L1 result is used only by L2 and L2 result by L3.<br>
// L3 LOH-related argument is defined only by L2 and L2 LOH-related argument<br>
// by L1.<br>
+// All these LOHs aim at using more efficient load/store patterns by folding<br>
+// some instructions used to compute the address directly into the load/store.<br>
//<br>
// * So called ADRP-related:<br>
// - .loh AdrpAdrp L2, L1:<br>
// L2: ADRP xA, sym1@PAGE<br>
// L1: ADRP xA, sym2@PAGE<br>
// L2 dominates L1 and xA is not redifined between L2 and L1<br>
+// This LOH aims at getting rid of redundant ADRP instructions.<br>
+//<br>
+// The overall design for emitting the LOHs is:<br>
+// 1. ARM64CollectLOH (this pass) records the LOHs in the ARM64FunctionInfo.<br>
+// 2. ARM64AsmPrinter reads the LOHs from ARM64FunctionInfo and it:<br>
+// 1. Associates them a label.<br>
+// 2. Emits them in a MCStreamer (EmitLOHDirective).<br>
+// - The MCMachOStreamer records them into the MCAssembler.<br>
+// - The MCAsmStreamer prints them.<br>
+// - Other MCStreamers ignore them.<br>
+// 3. Closes the MCStreamer:<br>
+// - The MachObjectWriter gets them from the MCAssembler and writes<br>
+// them in the object file.<br>
+// - Other ObjectWriters ignore them.<br>
//<br>
// More information are available in the design document attached to<br>
// <a href="rdar://11956674">rdar://11956674</a><br>
<br>
<br>
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</blockquote></div><br></div>
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