<div dir="ltr">From another thread on cfe-dev ("[cfe-dev] Debug info broken for ASan-instrumented binaries"), this is apparently <a href="https://code.google.com/p/address-sanitizer/issues/detail?id=235" target="_blank">https://code.google.com/p/address-sanitizer/issues/detail?id=235</a></div>
<div class="gmail_extra"><br><br><div class="gmail_quote">On Sat, Mar 29, 2014 at 4:07 PM, Nico Weber <span dir="ltr"><<a href="mailto:thakis@chromium.org" target="_blank">thakis@chromium.org</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">
<div dir="ltr">Hi Adrian,<div><br></div><div>r185966 lets clang optimize out the this pointer with asan even with -O0. Is that intentional?</div><div><br></div><div>(sorry about replying to the digest, I don't subscribe to llvm-commits.)</div>
<div><br></div><div>Thanks,</div><div>Nico</div><div><br></div><div><br></div><div>ps: Repro, at r185965 and r185966:</div><div><div><br></div><div>$ cat test.cc</div><div>class A {</div><div> public:</div><div> int f(int a) { </div>
<div> d = a;</div><div> int b = 4 * a;</div><div> return b;</div><div> }</div><div> int d;</div><div>};</div><div><br></div><div>int main() {</div><div> A a;</div><div> return a.f(53);</div><div>}</div><div>
<br>
</div><div>$ ~/src/llvm-build/bin/clang++ test.cc -g -fsanitize=address -O0</div><div>$ lldb a.out</div><div>Current executable set to 'a.out' (x86_64).</div><div>(lldb) b main</div><div>Breakpoint 1: where = a.out`main + 263 at test.cc:13, address = 0x0000000100000aa7</div>
<div>(lldb) run</div><div>Process 8465 launched: '/Users/thakis/src/chrome/src/a.out' (x86_64)</div><div>Process 8465 stopped</div><div>* thread #1: tid = 0x2cb858, 0x00007fff5fc01028 dyld`_dyld_start, stop reason = exec</div>
<div> frame #0: 0x00007fff5fc01028 dyld`_dyld_start</div><div>dyld`_dyld_start:</div><div>-> 0x7fff5fc01028: popq %rdi</div><div> 0x7fff5fc01029: pushq $0</div><div> 0x7fff5fc0102b: movq %rsp, %rbp</div>
<div> 0x7fff5fc0102e: andq $-16, %rsp</div><div>(lldb) c</div><div>Process 8465 resuming</div><div>Process 8465 stopped</div><div>* thread #1: tid = 0x2cb858, 0x0000000100000aa7 a.out`main + 263 at test.cc:13, queue = 'com.apple.main-thread, stop reason = breakpoint 1.1</div>
<div> frame #0: 0x0000000100000aa7 a.out`main + 263 at test.cc:13</div><div> 10 <span style="white-space:pre-wrap"> </span></div><div> 11 <span style="white-space:pre-wrap"> </span>int main() {</div><div>
12 <span style="white-space:pre-wrap"> </span> A a;</div><div>-> 13 <span style="white-space:pre-wrap"> </span> return a.f(53);</div><div> 14 <span style="white-space:pre-wrap"> </span>}</div><div>
(lldb) s</div><div>Process 8465 stopped</div><div>* thread #1: tid = 0x2cb858, 0x0000000100000ce2 a.out`A::f(this=0x00007fff5fbff980, a=53) + 402 at test.cc:4, queue = 'com.apple.main-thread, stop reason = step in</div>
<div> frame #0: 0x0000000100000ce2 a.out`A::f(this=0x00007fff5fbff980, a=53) + 402 at test.cc:4</div><div> 1 <span style="white-space:pre-wrap"> </span>class A {</div><div> 2 <span style="white-space:pre-wrap"> </span> public:</div>
<div> 3 <span style="white-space:pre-wrap"> </span> int f(int a) { </div><div>-> 4 <span style="white-space:pre-wrap"> </span> d = a;</div><div> 5 <span style="white-space:pre-wrap"> </span> int b = 4 * a;</div>
<div> 6 <span style="white-space:pre-wrap"> </span> return b;</div><div> 7 <span style="white-space:pre-wrap"> </span> }</div><div>(lldb) ^DQuitting LLDB will kill one or more processes. Do you really want to proceed: [Y/n] </div>
<div>Nicos-MacBook-Pro:src thakis$ ~/src/llvm-build/bin/clang++ --version</div><div>clang version 3.4 (185965)</div><div>Target: x86_64-apple-darwin13.1.0</div><div>Thread model: posix</div><div><br></div><div># Note how the this pointer is fine at r185965</div>
<div><br></div><div><br></div><div><br></div><div>$ ~/src/llvm-build/bin/clang++ test.cc -g -fsanitize=address -O0</div><div>$ lldb a.out</div><div>Current executable set to 'a.out' (x86_64).</div><div>(lldb) b main</div>
<div>Breakpoint 1: where = a.out`main + 263 at test.cc:13, address = 0x0000000100000aa7</div><div>(lldb) r</div><div>Process 8945 launched: '/Users/thakis/src/chrome/src/a.out' (x86_64)</div><div>Process 8945 stopped</div>
<div>* thread #1: tid = 0x2cbd36, 0x00007fff5fc01028 dyld`_dyld_start, stop reason = exec</div><div> frame #0: 0x00007fff5fc01028 dyld`_dyld_start</div><div>dyld`_dyld_start:</div><div>-> 0x7fff5fc01028: popq %rdi</div>
<div> 0x7fff5fc01029: pushq $0</div><div> 0x7fff5fc0102b: movq %rsp, %rbp</div><div> 0x7fff5fc0102e: andq $-16, %rsp</div><div>(lldb) c</div><div>Process 8945 resuming</div><div>Process 8945 stopped</div><div>
* thread #1: tid = 0x2cbd36, 0x0000000100000aa7 a.out`main + 263 at test.cc:13, queue = 'com.apple.main-thread, stop reason = breakpoint 1.1</div><div> frame #0: 0x0000000100000aa7 a.out`main + 263 at test.cc:13</div>
<div> 10 <span style="white-space:pre-wrap"> </span></div><div> 11 <span style="white-space:pre-wrap"> </span>int main() {</div><div> 12 <span style="white-space:pre-wrap"> </span> A a;</div><div>-> 13 <span style="white-space:pre-wrap"> </span> return a.f(53);</div>
<div> 14 <span style="white-space:pre-wrap"> </span>}</div><div>(lldb) s</div><div>Process 8945 stopped</div><div>* thread #1: tid = 0x2cbd36, 0x0000000100000ce2 a.out`A::f(this=<unavailable>, a=<unavailable>) + 402 at test.cc:4, queue = 'com.apple.main-thread, stop reason = step in</div>
<div> frame #0: 0x0000000100000ce2 a.out`A::f(this=<unavailable>, a=<unavailable>) + 402 at test.cc:4</div><div> 1 <span style="white-space:pre-wrap"> </span>class A {</div><div> 2 <span style="white-space:pre-wrap"> </span> public:</div>
<div> 3 <span style="white-space:pre-wrap"> </span> int f(int a) { </div><div>-> 4 <span style="white-space:pre-wrap"> </span> d = a;</div><div> 5 <span style="white-space:pre-wrap"> </span> int b = 4 * a;</div>
<div> 6 <span style="white-space:pre-wrap"> </span> return b;</div><div> 7 <span style="white-space:pre-wrap"> </span> }</div><div>(lldb) ^DQuitting LLDB will kill one or more processes. Do you really want to proceed: [Y/n] </div>
<div>Nicos-MacBook-Pro:src thakis$ ~/src/llvm-build/bin/clang++ --version</div><div>clang version 3.4 (185966)</div><div>Target: x86_64-apple-darwin13.1.0</div><div>Thread model: posix</div><div class="gmail_extra"><br></div>
<div class="gmail_extra"># Note that the this pointer is now optimized out</div><div class="gmail_extra"><br><br><div class="gmail_quote">On Tue, Jul 9, 2013 at 1:54 PM, <span dir="ltr"><<a href="mailto:llvm-commits-request@cs.uiuc.edu" target="_blank">llvm-commits-request@cs.uiuc.edu</a>></span> wrote:<br>
<blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left-width:1px;border-left-color:rgb(204,204,204);border-left-style:solid;padding-left:1ex">Send llvm-commits mailing list submissions to<br>
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<br>
Today's Topics:<br>
<br>
1. [llvm] r185960 - WidenVecRes_BUILD_VECTOR must use the first<br>
operand's type (Hal Finkel)<br>
2. [llvm] r185961 - Appease Atom buildbot after r185956<br>
(explicitly turn on AVX) (Stephen Lin)<br>
3. Re: [llvm] r185961 - Appease Atom buildbot after r185956<br>
(explicitly turn on AVX) (Stephen Lin)<br>
4. [llvm] r185962 - Appease buildbots after r185956: just set<br>
-mcpu explicitly, as it should have been from the beginning.<br>
(Stephen Lin)<br>
5. Re: [llvm] r185851 - [ADT/NullablePtr] Allow implicit<br>
conversion of NullablePtr<OtherT> -> NullablePtr<T> if OtherT is<br>
derived from T. (David Blaikie)<br>
6. [llvm] r185963 - Added "mode: c++" to FastISel.h header.<br>
(Michael Gottesman)<br>
7. Re: [llvm] r185851 - [ADT/NullablePtr] Allow implicit<br>
conversion of NullablePtr<OtherT> -> NullablePtr<T> if OtherT is<br>
derived from T. (Chandler Carruth)<br>
8. [llvm] r185964 - Fixed up the comments in FastISel.h so that<br>
they conform to the LLVM style guide. (Michael Gottesman)<br>
9. [llvm] r185966 - Reapply an improved version of<br>
r180816/180817. (Adrian Prantl)<br>
10. Re: [llvm-commits] [llvm] r159203 - in /llvm/trunk:<br>
lib/Target/ARM/ARMAsmPrinter.cpp<br>
lib/Target/CellSPU/SPUAsmPrinter.cpp<br>
lib/Target/Hexagon/HexagonAsmPrinter.cpp<br>
lib/Target/MBlaze/MBlazeAsmPrinter.cpp<br>
lib/Target/NVPTX/NVPTXAsmPrinter.cpp<br>
lib/Target/PowerPC/PPCAsmPrinter.cpp<br>
lib/Target/Sparc/SparcAsmPrinter.cpp<br>
lib/Target/X86/X86AsmPrinter.cpp<br>
lib/Target/XCore/XCoreAsmPrinter.cpp<br>
test/CodeGen/Generic/asm-large-immediate.ll (Aaron Ballman)<br>
11. [PATCH] Allow FMAs in safe math mode in some cases when one<br>
operand of the fmul is either exactly 0.0 or exactly 1.0.<br>
(Stephen Lin)<br>
12. Re: [PATCH] [Object] Split the ELF interface into 3 parts.<br>
(Michael Spencer)<br>
<br>
<br>
----------------------------------------------------------------------<br>
<br>
Message: 1<br>
Date: Tue, 09 Jul 2013 18:55:11 -0000<br>
From: Hal Finkel <<a href="mailto:hfinkel@anl.gov" target="_blank">hfinkel@anl.gov</a>><br>
To: <a href="mailto:llvm-commits@cs.uiuc.edu" target="_blank">llvm-commits@cs.uiuc.edu</a><br>
Subject: [llvm] r185960 - WidenVecRes_BUILD_VECTOR must use the first<br>
operand's type<br>
Message-ID: <<a href="mailto:20130709185511.504AE2A6C029@llvm.org" target="_blank">20130709185511.504AE2A6C029@llvm.org</a>><br>
Content-Type: text/plain; charset="utf-8"<br>
<br>
Author: hfinkel<br>
Date: Tue Jul 9 13:55:10 2013<br>
New Revision: 185960<br>
<br>
URL: <a href="http://llvm.org/viewvc/llvm-project?rev=185960&view=rev" target="_blank">http://llvm.org/viewvc/llvm-project?rev=185960&view=rev</a><br>
Log:<br>
WidenVecRes_BUILD_VECTOR must use the first operand's type<br>
<br>
Because integer BUILD_VECTOR operands may have a larger type than the result's<br>
vector element type, and all operands must have the same type, when widening a<br>
BUILD_VECTOR node by adding UNDEFs, we cannot use the vector element type, but<br>
rather must use the type of the existing operands.<br>
<br>
Another bug found by llvm-stress.<br>
<br>
Added:<br>
llvm/trunk/test/CodeGen/PowerPC/bv-widen-undef.ll<br>
Modified:<br>
llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp<br>
<br>
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp?rev=185960&r1=185959&r2=185960&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp?rev=185960&r1=185959&r2=185960&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp (original)<br>
+++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp Tue Jul 9 13:55:10 2013<br>
@@ -1872,7 +1872,10 @@ SDValue DAGTypeLegalizer::WidenVecRes_BU<br>
SDLoc dl(N);<br>
// Build a vector with undefined for the new nodes.<br>
EVT VT = N->getValueType(0);<br>
- EVT EltVT = VT.getVectorElementType();<br>
+<br>
+ // Integer BUILD_VECTOR operands may be larger than the node's vector element<br>
+ // type. The UNDEFs need to have the same type as the existing operands.<br>
+ EVT EltVT = N->getOperand(0).getValueType();<br>
unsigned NumElts = VT.getVectorNumElements();<br>
<br>
EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);<br>
<br>
Added: llvm/trunk/test/CodeGen/PowerPC/bv-widen-undef.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/bv-widen-undef.ll?rev=185960&view=auto" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/bv-widen-undef.ll?rev=185960&view=auto</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/PowerPC/bv-widen-undef.ll (added)<br>
+++ llvm/trunk/test/CodeGen/PowerPC/bv-widen-undef.ll Tue Jul 9 13:55:10 2013<br>
@@ -0,0 +1,23 @@<br>
+; RUN: llc -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 < %s<br>
+target triple = "powerpc64-unknown-linux-gnu"<br>
+<br>
+define void @autogen_SD4357(i8) {<br>
+BB:<br>
+ br label %CF<br>
+<br>
+CF: ; preds = %CF, %BB<br>
+ br i1 undef, label %CF, label %CF77<br>
+<br>
+CF77: ; preds = %CF81, %CF77, %CF<br>
+ %Shuff12 = shufflevector <2 x i8> <i8 -1, i8 -1>, <2 x i8> <i8 -1, i8 -1>, <2 x i32> <i32 0, i32 undef><br>
+ br i1 undef, label %CF77, label %CF80<br>
+<br>
+CF80: ; preds = %CF80, %CF77<br>
+ %B21 = mul <2 x i8> %Shuff12, <i8 -1, i8 -1><br>
+ %Cmp24 = fcmp une ppc_fp128 0xM00000000000000000000000000000000, 0xM00000000000000000000000000000000<br>
+ br i1 %Cmp24, label %CF80, label %CF81<br>
+<br>
+CF81: ; preds = %CF80<br>
+ %I36 = insertelement <2 x i8> %B21, i8 %0, i32 0<br>
+ br label %CF77<br>
+}<br>
<br>
<br>
<br>
<br>
------------------------------<br>
<br>
Message: 2<br>
Date: Tue, 09 Jul 2013 18:55:52 -0000<br>
From: Stephen Lin <<a href="mailto:stephenwlin@gmail.com" target="_blank">stephenwlin@gmail.com</a>><br>
To: <a href="mailto:llvm-commits@cs.uiuc.edu" target="_blank">llvm-commits@cs.uiuc.edu</a><br>
Subject: [llvm] r185961 - Appease Atom buildbot after r185956<br>
(explicitly turn on AVX)<br>
Message-ID: <<a href="mailto:20130709185552.EB1D62A6C029@llvm.org" target="_blank">20130709185552.EB1D62A6C029@llvm.org</a>><br>
Content-Type: text/plain; charset="utf-8"<br>
<br>
Author: stephenwlin<br>
Date: Tue Jul 9 13:55:52 2013<br>
New Revision: 185961<br>
<br>
URL: <a href="http://llvm.org/viewvc/llvm-project?rev=185961&view=rev" target="_blank">http://llvm.org/viewvc/llvm-project?rev=185961&view=rev</a><br>
Log:<br>
Appease Atom buildbot after r185956 (explicitly turn on AVX)<br>
<br>
Modified:<br>
llvm/trunk/test/CodeGen/X86/extended-fma-contraction.ll<br>
llvm/trunk/test/CodeGen/X86/wide-fma-contraction.ll<br>
<br>
Modified: llvm/trunk/test/CodeGen/X86/extended-fma-contraction.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/extended-fma-contraction.ll?rev=185961&r1=185960&r2=185961&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/extended-fma-contraction.ll?rev=185961&r1=185960&r2=185961&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/X86/extended-fma-contraction.ll (original)<br>
+++ llvm/trunk/test/CodeGen/X86/extended-fma-contraction.ll Tue Jul 9 13:55:52 2013<br>
@@ -1,5 +1,5 @@<br>
; RUN: llc -march=x86 -mattr=+fma4 -mtriple=x86_64-apple-darwin < %s | FileCheck %s<br>
-; RUN: llc -march=x86 -mattr=-fma,-fma4 -mtriple=x86_64-apple-darwin < %s | FileCheck %s --check-prefix=CHECK-NOFMA<br>
+; RUN: llc -march=x86 -mattr=+avx,-fma,-fma4 -mtriple=x86_64-apple-darwin < %s | FileCheck %s --check-prefix=CHECK-NOFMA<br>
<br>
; CHECK: fmafunc<br>
define <3 x float> @fmafunc(<3 x float> %a, <3 x float> %b, <3 x float> %c) {<br>
<br>
Modified: llvm/trunk/test/CodeGen/X86/wide-fma-contraction.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/wide-fma-contraction.ll?rev=185961&r1=185960&r2=185961&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/wide-fma-contraction.ll?rev=185961&r1=185960&r2=185961&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/X86/wide-fma-contraction.ll (original)<br>
+++ llvm/trunk/test/CodeGen/X86/wide-fma-contraction.ll Tue Jul 9 13:55:52 2013<br>
@@ -1,5 +1,5 @@<br>
; RUN: llc -march=x86 -mattr=+fma4 -mtriple=x86_64-apple-darwin < %s | FileCheck %s<br>
-; RUN: llc -march=x86 -mattr=-fma,-fma4 -mtriple=x86_64-apple-darwin < %s | FileCheck %s --check-prefix=CHECK-NOFMA<br>
+; RUN: llc -march=x86 -mattr=+avx,-fma,-fma4 -mtriple=x86_64-apple-darwin < %s | FileCheck %s --check-prefix=CHECK-NOFMA<br>
<br>
; CHECK: fmafunc<br>
define <16 x float> @fmafunc(<16 x float> %a, <16 x float> %b, <16 x float> %c) {<br>
<br>
<br>
<br>
<br>
------------------------------<br>
<br>
Message: 3<br>
Date: Tue, 9 Jul 2013 12:00:32 -0700<br>
From: Stephen Lin <<a href="mailto:stephenwlin@gmail.com" target="_blank">stephenwlin@gmail.com</a>><br>
To: <a href="mailto:llvm-commits@cs.uiuc.edu" target="_blank">llvm-commits@cs.uiuc.edu</a><br>
Subject: Re: [llvm] r185961 - Appease Atom buildbot after r185956<br>
(explicitly turn on AVX)<br>
Message-ID:<br>
<<a href="mailto:CAP2HvmDNKK8Euu%2Br19KPDOvH2oDg_%2Bi2-wdzvzMa1iMEvk3QHQ@mail.gmail.com" target="_blank">CAP2HvmDNKK8Euu+r19KPDOvH2oDg_+i2-wdzvzMa1iMEvk3QHQ@mail.gmail.com</a>><br>
Content-Type: text/plain; charset=UTF-8<br>
<br>
Sorry for all the broken bots, I copied and pasted a test line and<br>
didn't notice it wasn't setting the cpu explicitly (everything passed<br>
on my dev machine because it has +avx,-fma,-fma4)<br>
Stephen<br>
<br>
On Tue, Jul 9, 2013 at 11:55 AM, Stephen Lin <<a href="mailto:stephenwlin@gmail.com" target="_blank">stephenwlin@gmail.com</a>> wrote:<br>
> Author: stephenwlin<br>
> Date: Tue Jul 9 13:55:52 2013<br>
> New Revision: 185961<br>
><br>
> URL: <a href="http://llvm.org/viewvc/llvm-project?rev=185961&view=rev" target="_blank">http://llvm.org/viewvc/llvm-project?rev=185961&view=rev</a><br>
> Log:<br>
> Appease Atom buildbot after r185956 (explicitly turn on AVX)<br>
><br>
> Modified:<br>
> llvm/trunk/test/CodeGen/X86/extended-fma-contraction.ll<br>
> llvm/trunk/test/CodeGen/X86/wide-fma-contraction.ll<br>
><br>
> Modified: llvm/trunk/test/CodeGen/X86/extended-fma-contraction.ll<br>
> URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/extended-fma-contraction.ll?rev=185961&r1=185960&r2=185961&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/extended-fma-contraction.ll?rev=185961&r1=185960&r2=185961&view=diff</a><br>
> ==============================================================================<br>
> --- llvm/trunk/test/CodeGen/X86/extended-fma-contraction.ll (original)<br>
> +++ llvm/trunk/test/CodeGen/X86/extended-fma-contraction.ll Tue Jul 9 13:55:52 2013<br>
> @@ -1,5 +1,5 @@<br>
> ; RUN: llc -march=x86 -mattr=+fma4 -mtriple=x86_64-apple-darwin < %s | FileCheck %s<br>
> -; RUN: llc -march=x86 -mattr=-fma,-fma4 -mtriple=x86_64-apple-darwin < %s | FileCheck %s --check-prefix=CHECK-NOFMA<br>
> +; RUN: llc -march=x86 -mattr=+avx,-fma,-fma4 -mtriple=x86_64-apple-darwin < %s | FileCheck %s --check-prefix=CHECK-NOFMA<br>
><br>
> ; CHECK: fmafunc<br>
> define <3 x float> @fmafunc(<3 x float> %a, <3 x float> %b, <3 x float> %c) {<br>
><br>
> Modified: llvm/trunk/test/CodeGen/X86/wide-fma-contraction.ll<br>
> URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/wide-fma-contraction.ll?rev=185961&r1=185960&r2=185961&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/wide-fma-contraction.ll?rev=185961&r1=185960&r2=185961&view=diff</a><br>
> ==============================================================================<br>
> --- llvm/trunk/test/CodeGen/X86/wide-fma-contraction.ll (original)<br>
> +++ llvm/trunk/test/CodeGen/X86/wide-fma-contraction.ll Tue Jul 9 13:55:52 2013<br>
> @@ -1,5 +1,5 @@<br>
> ; RUN: llc -march=x86 -mattr=+fma4 -mtriple=x86_64-apple-darwin < %s | FileCheck %s<br>
> -; RUN: llc -march=x86 -mattr=-fma,-fma4 -mtriple=x86_64-apple-darwin < %s | FileCheck %s --check-prefix=CHECK-NOFMA<br>
> +; RUN: llc -march=x86 -mattr=+avx,-fma,-fma4 -mtriple=x86_64-apple-darwin < %s | FileCheck %s --check-prefix=CHECK-NOFMA<br>
><br>
> ; CHECK: fmafunc<br>
> define <16 x float> @fmafunc(<16 x float> %a, <16 x float> %b, <16 x float> %c) {<br>
><br>
><br>
> _______________________________________________<br>
> llvm-commits mailing list<br>
> <a href="mailto:llvm-commits@cs.uiuc.edu" target="_blank">llvm-commits@cs.uiuc.edu</a><br>
> <a href="http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits" target="_blank">http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits</a><br>
<br>
<br>
------------------------------<br>
<br>
Message: 4<br>
Date: Tue, 09 Jul 2013 19:27:10 -0000<br>
From: Stephen Lin <<a href="mailto:stephenwlin@gmail.com" target="_blank">stephenwlin@gmail.com</a>><br>
To: <a href="mailto:llvm-commits@cs.uiuc.edu" target="_blank">llvm-commits@cs.uiuc.edu</a><br>
Subject: [llvm] r185962 - Appease buildbots after r185956: just set<br>
-mcpu explicitly, as it should have been from the beginning.<br>
Message-ID: <<a href="mailto:20130709192710.83C4C2A6C029@llvm.org" target="_blank">20130709192710.83C4C2A6C029@llvm.org</a>><br>
Content-Type: text/plain; charset="utf-8"<br>
<br>
Author: stephenwlin<br>
Date: Tue Jul 9 14:27:10 2013<br>
New Revision: 185962<br>
<br>
URL: <a href="http://llvm.org/viewvc/llvm-project?rev=185962&view=rev" target="_blank">http://llvm.org/viewvc/llvm-project?rev=185962&view=rev</a><br>
Log:<br>
Appease buildbots after r185956: just set -mcpu explicitly, as it should have been from the beginning.<br>
<br>
Modified:<br>
llvm/trunk/test/CodeGen/X86/extended-fma-contraction.ll<br>
llvm/trunk/test/CodeGen/X86/wide-fma-contraction.ll<br>
<br>
Modified: llvm/trunk/test/CodeGen/X86/extended-fma-contraction.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/extended-fma-contraction.ll?rev=185962&r1=185961&r2=185962&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/extended-fma-contraction.ll?rev=185962&r1=185961&r2=185962&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/X86/extended-fma-contraction.ll (original)<br>
+++ llvm/trunk/test/CodeGen/X86/extended-fma-contraction.ll Tue Jul 9 14:27:10 2013<br>
@@ -1,5 +1,5 @@<br>
-; RUN: llc -march=x86 -mattr=+fma4 -mtriple=x86_64-apple-darwin < %s | FileCheck %s<br>
-; RUN: llc -march=x86 -mattr=+avx,-fma,-fma4 -mtriple=x86_64-apple-darwin < %s | FileCheck %s --check-prefix=CHECK-NOFMA<br>
+; RUN: llc -march=x86 -mcpu=bdver2 -mattr=-fma -mtriple=x86_64-apple-darwin < %s | FileCheck %s<br>
+; RUN: llc -march=x86 -mcpu=bdver2 -mattr=-fma,-fma4 -mtriple=x86_64-apple-darwin < %s | FileCheck %s --check-prefix=CHECK-NOFMA<br>
<br>
; CHECK: fmafunc<br>
define <3 x float> @fmafunc(<3 x float> %a, <3 x float> %b, <3 x float> %c) {<br>
<br>
Modified: llvm/trunk/test/CodeGen/X86/wide-fma-contraction.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/wide-fma-contraction.ll?rev=185962&r1=185961&r2=185962&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/wide-fma-contraction.ll?rev=185962&r1=185961&r2=185962&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/X86/wide-fma-contraction.ll (original)<br>
+++ llvm/trunk/test/CodeGen/X86/wide-fma-contraction.ll Tue Jul 9 14:27:10 2013<br>
@@ -1,5 +1,5 @@<br>
-; RUN: llc -march=x86 -mattr=+fma4 -mtriple=x86_64-apple-darwin < %s | FileCheck %s<br>
-; RUN: llc -march=x86 -mattr=+avx,-fma,-fma4 -mtriple=x86_64-apple-darwin < %s | FileCheck %s --check-prefix=CHECK-NOFMA<br>
+; RUN: llc -march=x86 -mcpu=bdver2 -mattr=-fma -mtriple=x86_64-apple-darwin < %s | FileCheck %s<br>
+; RUN: llc -march=x86 -mcpu=bdver2 -mattr=-fma,-fma4 -mtriple=x86_64-apple-darwin < %s | FileCheck %s --check-prefix=CHECK-NOFMA<br>
<br>
; CHECK: fmafunc<br>
define <16 x float> @fmafunc(<16 x float> %a, <16 x float> %b, <16 x float> %c) {<br>
<br>
<br>
<br>
<br>
------------------------------<br>
<br>
Message: 5<br>
Date: Tue, 9 Jul 2013 12:37:11 -0700<br>
From: David Blaikie <<a href="mailto:dblaikie@gmail.com" target="_blank">dblaikie@gmail.com</a>><br>
To: Argyrios Kyrtzidis <<a href="mailto:akyrtzi@gmail.com" target="_blank">akyrtzi@gmail.com</a>><br>
Cc: "<a href="mailto:llvm-commits@cs.uiuc.edu" target="_blank">llvm-commits@cs.uiuc.edu</a>" <<a href="mailto:llvm-commits@cs.uiuc.edu" target="_blank">llvm-commits@cs.uiuc.edu</a>><br>
Subject: Re: [llvm] r185851 - [ADT/NullablePtr] Allow implicit<br>
conversion of NullablePtr<OtherT> -> NullablePtr<T> if OtherT is<br>
derived from T.<br>
Message-ID:<br>
<<a href="mailto:CAENS6EuF7cSYBNfSJp03r89%2Booc_ypQjn7vB_7qcxqKsBgjrzQ@mail.gmail.com" target="_blank">CAENS6EuF7cSYBNfSJp03r89+ooc_ypQjn7vB_7qcxqKsBgjrzQ@mail.gmail.com</a>><br>
Content-Type: text/plain; charset=ISO-8859-1<br>
<br>
On Tue, Jul 9, 2013 at 11:48 AM, Argyrios Kyrtzidis <<a href="mailto:akyrtzi@gmail.com" target="_blank">akyrtzi@gmail.com</a>> wrote:<br>
> On Jul 8, 2013, at 7:37 PM, David Blaikie <<a href="mailto:dblaikie@gmail.com" target="_blank">dblaikie@gmail.com</a>> wrote:<br>
><br>
>> On Mon, Jul 8, 2013 at 7:31 PM, Argyrios Kyrtzidis <<a href="mailto:akyrtzi@gmail.com" target="_blank">akyrtzi@gmail.com</a>> wrote:<br>
>>> On Jul 8, 2013, at 5:31 PM, David Blaikie <<a href="mailto:dblaikie@gmail.com" target="_blank">dblaikie@gmail.com</a>> wrote:<br>
>>><br>
>>>> On Mon, Jul 8, 2013 at 5:08 PM, Argyrios Kyrtzidis <<a href="mailto:akyrtzi@gmail.com" target="_blank">akyrtzi@gmail.com</a>> wrote:<br>
>>>>> On Jul 8, 2013, at 4:05 PM, David Blaikie <<a href="mailto:dblaikie@gmail.com" target="_blank">dblaikie@gmail.com</a>> wrote:<br>
>>>>><br>
>>>>> On Mon, Jul 8, 2013 at 2:51 PM, Argyrios Kyrtzidis <<a href="mailto:akyrtzi@gmail.com" target="_blank">akyrtzi@gmail.com</a>><br>
>>>>> wrote:<br>
>>>>><br>
>>>>> On Jul 8, 2013, at 12:47 PM, David Blaikie <<a href="mailto:dblaikie@gmail.com" target="_blank">dblaikie@gmail.com</a>> wrote:<br>
>>>>><br>
>>>>> On Mon, Jul 8, 2013 at 12:12 PM, Argyrios Kyrtzidis <<a href="mailto:akyrtzi@gmail.com" target="_blank">akyrtzi@gmail.com</a>><br>
>>>>> wrote:<br>
>>>>><br>
>>>>> Author: akirtzidis<br>
>>>>> Date: Mon Jul 8 14:12:01 2013<br>
>>>>> New Revision: 185851<br>
>>>>><br>
>>>>> URL: <a href="http://llvm.org/viewvc/llvm-project?rev=185851&view=rev" target="_blank">http://llvm.org/viewvc/llvm-project?rev=185851&view=rev</a><br>
>>>>> Log:<br>
>>>>> [ADT/NullablePtr] Allow implicit conversion of NullablePtr<OtherT> -><br>
>>>>> NullablePtr<T> if OtherT is derived from T.<br>
>>>>><br>
>>>>><br>
>>>>> Might be nicer to do this for any case where SrcT* is implicitly<br>
>>>>> convertible DestT* (such as adding cv qualifiers or converting to<br>
>>>>> void*).<br>
>>>>><br>
>>>>><br>
>>>>> cv qualifiers look like are working, void* is not.<br>
>>>>> In general, we need to add the equivalent of C++11's is_convertible to<br>
>>>>> "llvm/Support/type_traits.h" and use it here.<br>
>>>>><br>
>>>>><br>
>>>>> Shall we do that then?<br>
>>>>><br>
>>>>> (your current implementation also disables this ctor for NullablePtr's<br>
>>>>> of non-class type (NullablePtr<int> for example), I think... that<br>
>>>>> seems unreasonable)<br>
>>>>><br>
>>>>><br>
>>>>> Feel free to enhance it :-)<br>
>>>><br>
>>>> Alternatively, this code doesn't seem to have any uses inside the llvm<br>
>>>> codebase (at least not clang, llvm, compiler-rt, libcxx - maybe in<br>
>>>> lldb?) nor any tests. Should we just remove it instead? (I assume you<br>
>>>> have a use-case, or you wouldn't've been motivated to update it - is<br>
>>>> that use case somewhere in the llvm project (broadly, across all<br>
>>>> subprojects) or out of tree?)<br>
>>><br>
>>> It is used out of tree.<br>
>><br>
>> It might be more suitable for it to live along with the code that's<br>
>> consuming it, I'd imagine. (that'd be my preference, at least - though<br>
>> if it's really necessary for it to be here, it should probably at<br>
>> least have unit tests)<br>
><br>
> Unit tests for this are overkill IMO,<br>
<br>
Even if it's just compile tests to check that some of the examples I<br>
gave work correctly/as expected, that doesn't seem unreasonable to me<br>
(if only to enshrine/document the intended semantics).<br>
<br>
> we could just start using it in new llvm/clang APIs.<br>
<br>
That it's been in the codebase for 2 years & still (?) has zero uses<br>
seems to indicate that that might not be desired & should probably<br>
just be removed.<br>
<br>
><br>
>><br>
>> - David<br>
>><br>
>>><br>
>>>><br>
>>>> - David<br>
>>>><br>
>>>>><br>
>>>>> -Argyrios<br>
>>>>><br>
>>>>><br>
>>>>><br>
>>>>><br>
>>>>><br>
>>>>> Modified:<br>
>>>>> llvm/trunk/include/llvm/ADT/NullablePtr.h<br>
>>>>><br>
>>>>> Modified: llvm/trunk/include/llvm/ADT/NullablePtr.h<br>
>>>>> URL:<br>
>>>>> <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/ADT/NullablePtr.h?rev=185851&r1=185850&r2=185851&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/ADT/NullablePtr.h?rev=185851&r1=185850&r2=185851&view=diff</a><br>
>>>>> ==============================================================================<br>
>>>>> --- llvm/trunk/include/llvm/ADT/NullablePtr.h (original)<br>
>>>>> +++ llvm/trunk/include/llvm/ADT/NullablePtr.h Mon Jul 8 14:12:01 2013<br>
>>>>> @@ -14,6 +14,7 @@<br>
>>>>> #ifndef LLVM_ADT_NULLABLEPTR_H<br>
>>>>> #define LLVM_ADT_NULLABLEPTR_H<br>
>>>>><br>
>>>>> +#include "llvm/Support/type_traits.h"<br>
>>>>> #include <cassert><br>
>>>>> #include <cstddef><br>
>>>>><br>
>>>>> @@ -25,8 +26,17 @@ namespace llvm {<br>
>>>>> template<class T><br>
>>>>> class NullablePtr {<br>
>>>>> T *Ptr;<br>
>>>>> + struct PlaceHolder {};<br>
>>>>> +<br>
>>>>> public:<br>
>>>>> NullablePtr(T *P = 0) : Ptr(P) {}<br>
>>>>> +<br>
>>>>> + template<typename OtherT><br>
>>>>> + NullablePtr(NullablePtr<OtherT> Other,<br>
>>>>> + typename enable_if<<br>
>>>>> + is_base_of<T, OtherT>,<br>
>>>>> + PlaceHolder<br>
>>>>> + >::type = PlaceHolder()) : Ptr(Other.getPtrOrNull()) {}<br>
>>>>><br>
>>>>> bool isNull() const { return Ptr == 0; }<br>
>>>>> bool isNonNull() const { return Ptr != 0; }<br>
>>>>><br>
>>>>><br>
>>>>> _______________________________________________<br>
>>>>> llvm-commits mailing list<br>
>>>>> <a href="mailto:llvm-commits@cs.uiuc.edu" target="_blank">llvm-commits@cs.uiuc.edu</a><br>
>>>>> <a href="http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits" target="_blank">http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits</a><br>
>>>>><br>
>>>>><br>
>>><br>
><br>
<br>
<br>
------------------------------<br>
<br>
Message: 6<br>
Date: Tue, 09 Jul 2013 20:00:25 -0000<br>
From: Michael Gottesman <<a href="mailto:mgottesman@apple.com" target="_blank">mgottesman@apple.com</a>><br>
To: <a href="mailto:llvm-commits@cs.uiuc.edu" target="_blank">llvm-commits@cs.uiuc.edu</a><br>
Subject: [llvm] r185963 - Added "mode: c++" to FastISel.h header.<br>
Message-ID: <<a href="mailto:20130709200025.826872A6C029@llvm.org" target="_blank">20130709200025.826872A6C029@llvm.org</a>><br>
Content-Type: text/plain; charset="utf-8"<br>
<br>
Author: mgottesman<br>
Date: Tue Jul 9 15:00:25 2013<br>
New Revision: 185963<br>
<br>
URL: <a href="http://llvm.org/viewvc/llvm-project?rev=185963&view=rev" target="_blank">http://llvm.org/viewvc/llvm-project?rev=185963&view=rev</a><br>
Log:<br>
Added "mode: c++" to FastISel.h header.<br>
<br>
Modified:<br>
llvm/trunk/include/llvm/CodeGen/FastISel.h<br>
<br>
Modified: llvm/trunk/include/llvm/CodeGen/FastISel.h<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/FastISel.h?rev=185963&r1=185962&r2=185963&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/FastISel.h?rev=185963&r1=185962&r2=185963&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/include/llvm/CodeGen/FastISel.h (original)<br>
+++ llvm/trunk/include/llvm/CodeGen/FastISel.h Tue Jul 9 15:00:25 2013<br>
@@ -1,4 +1,4 @@<br>
-//===-- FastISel.h - Definition of the FastISel class ---------------------===//<br>
+//===-- FastISel.h - Definition of the FastISel class ---*- mode: c++; -*--===//<br>
//<br>
// The LLVM Compiler Infrastructure<br>
//<br>
<br>
<br>
<br>
<br>
------------------------------<br>
<br>
Message: 7<br>
Date: Tue, 9 Jul 2013 13:02:34 -0700<br>
From: Chandler Carruth <<a href="mailto:chandlerc@google.com" target="_blank">chandlerc@google.com</a>><br>
To: Argyrios Kyrtzidis <<a href="mailto:akyrtzi@gmail.com" target="_blank">akyrtzi@gmail.com</a>><br>
Cc: "<a href="mailto:llvm-commits@cs.uiuc.edu" target="_blank">llvm-commits@cs.uiuc.edu</a>" <<a href="mailto:llvm-commits@cs.uiuc.edu" target="_blank">llvm-commits@cs.uiuc.edu</a>><br>
Subject: Re: [llvm] r185851 - [ADT/NullablePtr] Allow implicit<br>
conversion of NullablePtr<OtherT> -> NullablePtr<T> if OtherT is<br>
derived from T.<br>
Message-ID:<br>
<CAGCO0Kj+=8ODzR1EBFkgS+FEBgXW6030v=<a href="mailto:h_au25kWPELSjfpg@mail.gmail.com" target="_blank">h_au25kWPELSjfpg@mail.gmail.com</a>><br>
Content-Type: text/plain; charset="utf-8"<br>
<br>
On Tue, Jul 9, 2013 at 11:48 AM, Argyrios Kyrtzidis <<a href="mailto:akyrtzi@gmail.com" target="_blank">akyrtzi@gmail.com</a>>wrote:<br>
<br>
> >>> Alternatively, this code doesn't seem to have any uses inside the llvm<br>
> >>> codebase (at least not clang, llvm, compiler-rt, libcxx - maybe in<br>
> >>> lldb?) nor any tests. Should we just remove it instead? (I assume you<br>
> >>> have a use-case, or you wouldn't've been motivated to update it - is<br>
> >>> that use case somewhere in the llvm project (broadly, across all<br>
> >>> subprojects) or out of tree?)<br>
> >><br>
> >> It is used out of tree.<br>
> ><br>
> > It might be more suitable for it to live along with the code that's<br>
> > consuming it, I'd imagine. (that'd be my preference, at least - though<br>
> > if it's really necessary for it to be here, it should probably at<br>
> > least have unit tests)<br>
><br>
> Unit tests for this are overkill IMO, we could just start using it in new<br>
> llvm/clang APIs.<br>
<br>
<br>
I think one of two things need to happen here:<br>
<br>
1) We move this code to live with the out-of-tree consumers so that the<br>
open source project isn't maintaining and carrying forward untested and<br>
unused code paths, or<br>
2) We make a conscious decision to consistently recommend the use of this<br>
type as part of APIs in LLVM, Clang, and other projects.<br>
<br>
As to why I would prefer #1 over #2: I don't (yet) buy the utility of this.<br>
Instead, I prefer the simple rule: pointers are nullable, references are<br>
not, and to use them for those purposes.<br>
<br>
Yes, there is a challenge of re-binding a never-null pointer member of a<br>
class, but the fact that this utility for addressing that problem has<br>
gotten so little adoption makes me feel that this isn't a big problem, and<br>
we already have sufficient tools to address it (such as assert()s around<br>
mutation operations).<br>
<br>
My 2 cents.<br>
-Chandler<br>
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<br>
------------------------------<br>
<br>
Message: 8<br>
Date: Tue, 09 Jul 2013 20:08:46 -0000<br>
From: Michael Gottesman <<a href="mailto:mgottesman@apple.com" target="_blank">mgottesman@apple.com</a>><br>
To: <a href="mailto:llvm-commits@cs.uiuc.edu" target="_blank">llvm-commits@cs.uiuc.edu</a><br>
Subject: [llvm] r185964 - Fixed up the comments in FastISel.h so that<br>
they conform to the LLVM style guide.<br>
Message-ID: <<a href="mailto:20130709200846.8FF102A6C029@llvm.org" target="_blank">20130709200846.8FF102A6C029@llvm.org</a>><br>
Content-Type: text/plain; charset="utf-8"<br>
<br>
Author: mgottesman<br>
Date: Tue Jul 9 15:08:46 2013<br>
New Revision: 185964<br>
<br>
URL: <a href="http://llvm.org/viewvc/llvm-project?rev=185964&view=rev" target="_blank">http://llvm.org/viewvc/llvm-project?rev=185964&view=rev</a><br>
Log:<br>
Fixed up the comments in FastISel.h so that they conform to the LLVM style guide.<br>
<br>
Modified:<br>
llvm/trunk/include/llvm/CodeGen/FastISel.h<br>
<br>
Modified: llvm/trunk/include/llvm/CodeGen/FastISel.h<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/FastISel.h?rev=185964&r1=185963&r2=185964&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/FastISel.h?rev=185964&r1=185963&r2=185964&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/include/llvm/CodeGen/FastISel.h (original)<br>
+++ llvm/trunk/include/llvm/CodeGen/FastISel.h Tue Jul 9 15:08:46 2013<br>
@@ -6,9 +6,10 @@<br>
// License. See LICENSE.TXT for details.<br>
//<br>
//===----------------------------------------------------------------------===//<br>
-//<br>
-// This file defines the FastISel class.<br>
-//<br>
+///<br>
+/// \file<br>
+/// This file defines the FastISel class.<br>
+///<br>
//===----------------------------------------------------------------------===//<br>
<br>
#ifndef LLVM_CODEGEN_FASTISEL_H<br>
@@ -41,9 +42,8 @@ class TargetRegisterInfo;<br>
class User;<br>
class Value;<br>
<br>
-/// FastISel - This is a fast-path instruction selection class that<br>
-/// generates poor code and doesn't support illegal types or non-trivial<br>
-/// lowering, but runs quickly.<br>
+/// This is a fast-path instruction selection class that generates poor code and<br>
+/// doesn't support illegal types or non-trivial lowering, but runs quickly.<br>
class FastISel {<br>
protected:<br>
DenseMap<const Value *, unsigned> LocalValueMap;<br>
@@ -59,99 +59,92 @@ protected:<br>
const TargetRegisterInfo &TRI;<br>
const TargetLibraryInfo *LibInfo;<br>
<br>
- /// The position of the last instruction for materializing constants<br>
- /// for use in the current block. It resets to EmitStartPt when it<br>
- /// makes sense (for example, it's usually profitable to avoid function<br>
- /// calls between the definition and the use)<br>
+ /// The position of the last instruction for materializing constants for use<br>
+ /// in the current block. It resets to EmitStartPt when it makes sense (for<br>
+ /// example, it's usually profitable to avoid function calls between the<br>
+ /// definition and the use)<br>
MachineInstr *LastLocalValue;<br>
<br>
- /// The top most instruction in the current block that is allowed for<br>
- /// emitting local variables. LastLocalValue resets to EmitStartPt when<br>
- /// it makes sense (for example, on function calls)<br>
+ /// The top most instruction in the current block that is allowed for emitting<br>
+ /// local variables. LastLocalValue resets to EmitStartPt when it makes sense<br>
+ /// (for example, on function calls)<br>
MachineInstr *EmitStartPt;<br>
<br>
public:<br>
- /// getLastLocalValue - Return the position of the last instruction<br>
- /// emitted for materializing constants for use in the current block.<br>
+ /// Return the position of the last instruction emitted for materializing<br>
+ /// constants for use in the current block.<br>
MachineInstr *getLastLocalValue() { return LastLocalValue; }<br>
<br>
- /// setLastLocalValue - Update the position of the last instruction<br>
- /// emitted for materializing constants for use in the current block.<br>
+ /// Update the position of the last instruction emitted for materializing<br>
+ /// constants for use in the current block.<br>
void setLastLocalValue(MachineInstr *I) {<br>
EmitStartPt = I;<br>
LastLocalValue = I;<br>
}<br>
<br>
- /// startNewBlock - Set the current block to which generated machine<br>
- /// instructions will be appended, and clear the local CSE map.<br>
- ///<br>
+ /// Set the current block to which generated machine instructions will be<br>
+ /// appended, and clear the local CSE map.<br>
void startNewBlock();<br>
<br>
- /// getCurDebugLoc() - Return current debug location information.<br>
+ /// Return current debug location information.<br>
DebugLoc getCurDebugLoc() const { return DL; }<br>
<br>
- /// LowerArguments - Do "fast" instruction selection for function arguments<br>
- /// and append machine instructions to the current block. Return true if<br>
- /// it is successful.<br>
+ /// Do "fast" instruction selection for function arguments and append machine<br>
+ /// instructions to the current block. Return true if it is successful.<br>
bool LowerArguments();<br>
<br>
- /// SelectInstruction - Do "fast" instruction selection for the given<br>
- /// LLVM IR instruction, and append generated machine instructions to<br>
- /// the current block. Return true if selection was successful.<br>
- ///<br>
+ /// Do "fast" instruction selection for the given LLVM IR instruction, and<br>
+ /// append generated machine instructions to the current block. Return true if<br>
+ /// selection was successful.<br>
bool SelectInstruction(const Instruction *I);<br>
<br>
- /// SelectOperator - Do "fast" instruction selection for the given<br>
- /// LLVM IR operator (Instruction or ConstantExpr), and append<br>
- /// generated machine instructions to the current block. Return true<br>
- /// if selection was successful.<br>
- ///<br>
+ /// Do "fast" instruction selection for the given LLVM IR operator<br>
+ /// (Instruction or ConstantExpr), and append generated machine instructions<br>
+ /// to the current block. Return true if selection was successful.<br>
bool SelectOperator(const User *I, unsigned Opcode);<br>
<br>
- /// getRegForValue - Create a virtual register and arrange for it to<br>
- /// be assigned the value for the given LLVM value.<br>
+ /// Create a virtual register and arrange for it to be assigned the value for<br>
+ /// the given LLVM value.<br>
unsigned getRegForValue(const Value *V);<br>
<br>
- /// lookUpRegForValue - Look up the value to see if its value is already<br>
- /// cached in a register. It may be defined by instructions across blocks or<br>
- /// defined locally.<br>
+ /// Look up the value to see if its value is already cached in a register. It<br>
+ /// may be defined by instructions across blocks or defined locally.<br>
unsigned lookUpRegForValue(const Value *V);<br>
<br>
- /// getRegForGEPIndex - This is a wrapper around getRegForValue that also<br>
- /// takes care of truncating or sign-extending the given getelementptr<br>
- /// index value.<br>
+ /// This is a wrapper around getRegForValue that also takes care of truncating<br>
+ /// or sign-extending the given getelementptr index value.<br>
std::pair<unsigned, bool> getRegForGEPIndex(const Value *V);<br>
<br>
- /// \brief We're checking to see if we can fold \p LI into \p FoldInst.<br>
- /// Note that we could have a sequence where multiple LLVM IR instructions<br>
- /// are folded into the same machineinstr. For example we could have:<br>
+ /// \brief We're checking to see if we can fold \p LI into \p FoldInst. Note<br>
+ /// that we could have a sequence where multiple LLVM IR instructions are<br>
+ /// folded into the same machineinstr. For example we could have:<br>
+ ///<br>
/// A: x = load i32 *P<br>
/// B: y = icmp A, 42<br>
/// C: br y, ...<br>
///<br>
- /// In this scenario, \p LI is "A", and \p FoldInst is "C". We know<br>
- /// about "B" (and any other folded instructions) because it is between<br>
- /// A and C.<br>
+ /// In this scenario, \p LI is "A", and \p FoldInst is "C". We know about "B"<br>
+ /// (and any other folded instructions) because it is between A and C.<br>
///<br>
/// If we succeed folding, return true.<br>
- ///<br>
bool tryToFoldLoad(const LoadInst *LI, const Instruction *FoldInst);<br>
<br>
- /// \brief The specified machine instr operand is a vreg, and that<br>
- /// vreg is being provided by the specified load instruction. If possible,<br>
- /// try to fold the load as an operand to the instruction, returning true if<br>
+ /// \brief The specified machine instr operand is a vreg, and that vreg is<br>
+ /// being provided by the specified load instruction. If possible, try to<br>
+ /// fold the load as an operand to the instruction, returning true if<br>
/// possible.<br>
+ ///<br>
/// This method should be implemented by targets.<br>
virtual bool tryToFoldLoadIntoMI(MachineInstr * /*MI*/, unsigned /*OpNo*/,<br>
const LoadInst * /*LI*/) {<br>
return false;<br>
}<br>
<br>
- /// recomputeInsertPt - Reset InsertPt to prepare for inserting instructions<br>
- /// into the current block.<br>
+ /// Reset InsertPt to prepare for inserting instructions into the current<br>
+ /// block.<br>
void recomputeInsertPt();<br>
<br>
- /// removeDeadCode - Remove all dead instructions between the I and E.<br>
+ /// Remove all dead instructions between the I and E.<br>
void removeDeadCode(MachineBasicBlock::iterator I,<br>
MachineBasicBlock::iterator E);<br>
<br>
@@ -160,11 +153,11 @@ public:<br>
DebugLoc DL;<br>
};<br>
<br>
- /// enterLocalValueArea - Prepare InsertPt to begin inserting instructions<br>
- /// into the local value area and return the old insert position.<br>
+ /// Prepare InsertPt to begin inserting instructions into the local value area<br>
+ /// and return the old insert position.<br>
SavePoint enterLocalValueArea();<br>
<br>
- /// leaveLocalValueArea - Reset InsertPt to the given old insert position.<br>
+ /// Reset InsertPt to the given old insert position.<br>
void leaveLocalValueArea(SavePoint Old);<br>
<br>
virtual ~FastISel();<br>
@@ -173,69 +166,59 @@ protected:<br>
explicit FastISel(FunctionLoweringInfo &funcInfo,<br>
const TargetLibraryInfo *libInfo);<br>
<br>
- /// TargetSelectInstruction - This method is called by target-independent<br>
- /// code when the normal FastISel process fails to select an instruction.<br>
- /// This gives targets a chance to emit code for anything that doesn't<br>
- /// fit into FastISel's framework. It returns true if it was successful.<br>
- ///<br>
+ /// This method is called by target-independent code when the normal FastISel<br>
+ /// process fails to select an instruction. This gives targets a chance to<br>
+ /// emit code for anything that doesn't fit into FastISel's framework. It<br>
+ /// returns true if it was successful.<br>
virtual bool<br>
TargetSelectInstruction(const Instruction *I) = 0;<br>
<br>
- /// FastLowerArguments - This method is called by target-independent code to<br>
- /// do target specific argument lowering. It returns true if it was<br>
- /// successful.<br>
+ /// This method is called by target-independent code to do target specific<br>
+ /// argument lowering. It returns true if it was successful.<br>
virtual bool FastLowerArguments();<br>
<br>
- /// FastEmit_r - This method is called by target-independent code<br>
- /// to request that an instruction with the given type and opcode<br>
- /// be emitted.<br>
+ /// This method is called by target-independent code to request that an<br>
+ /// instruction with the given type and opcode be emitted.<br>
virtual unsigned FastEmit_(MVT VT,<br>
MVT RetVT,<br>
unsigned Opcode);<br>
<br>
- /// FastEmit_r - This method is called by target-independent code<br>
- /// to request that an instruction with the given type, opcode, and<br>
- /// register operand be emitted.<br>
- ///<br>
+ /// This method is called by target-independent code to request that an<br>
+ /// instruction with the given type, opcode, and register operand be emitted.<br>
virtual unsigned FastEmit_r(MVT VT,<br>
MVT RetVT,<br>
unsigned Opcode,<br>
unsigned Op0, bool Op0IsKill);<br>
<br>
- /// FastEmit_rr - This method is called by target-independent code<br>
- /// to request that an instruction with the given type, opcode, and<br>
- /// register operands be emitted.<br>
- ///<br>
+ /// This method is called by target-independent code to request that an<br>
+ /// instruction with the given type, opcode, and register operands be emitted.<br>
virtual unsigned FastEmit_rr(MVT VT,<br>
MVT RetVT,<br>
unsigned Opcode,<br>
unsigned Op0, bool Op0IsKill,<br>
unsigned Op1, bool Op1IsKill);<br>
<br>
- /// FastEmit_ri - This method is called by target-independent code<br>
- /// to request that an instruction with the given type, opcode, and<br>
- /// register and immediate operands be emitted.<br>
- ///<br>
+ /// This method is called by target-independent code to request that an<br>
+ /// instruction with the given type, opcode, and register and immediate<br>
+ /// operands be emitted.<br>
virtual unsigned FastEmit_ri(MVT VT,<br>
MVT RetVT,<br>
unsigned Opcode,<br>
unsigned Op0, bool Op0IsKill,<br>
uint64_t Imm);<br>
<br>
- /// FastEmit_rf - This method is called by target-independent code<br>
- /// to request that an instruction with the given type, opcode, and<br>
- /// register and floating-point immediate operands be emitted.<br>
- ///<br>
+ /// This method is called by target-independent code to request that an<br>
+ /// instruction with the given type, opcode, and register and floating-point<br>
+ /// immediate operands be emitted.<br>
virtual unsigned FastEmit_rf(MVT VT,<br>
MVT RetVT,<br>
unsigned Opcode,<br>
unsigned Op0, bool Op0IsKill,<br>
const ConstantFP *FPImm);<br>
<br>
- /// FastEmit_rri - This method is called by target-independent code<br>
- /// to request that an instruction with the given type, opcode, and<br>
- /// register and immediate operands be emitted.<br>
- ///<br>
+ /// This method is called by target-independent code to request that an<br>
+ /// instruction with the given type, opcode, and register and immediate<br>
+ /// operands be emitted.<br>
virtual unsigned FastEmit_rri(MVT VT,<br>
MVT RetVT,<br>
unsigned Opcode,<br>
@@ -243,142 +226,130 @@ protected:<br>
unsigned Op1, bool Op1IsKill,<br>
uint64_t Imm);<br>
<br>
- /// FastEmit_ri_ - This method is a wrapper of FastEmit_ri. It first tries<br>
- /// to emit an instruction with an immediate operand using FastEmit_ri.<br>
- /// If that fails, it materializes the immediate into a register and try<br>
- /// FastEmit_rr instead.<br>
+ /// \brief This method is a wrapper of FastEmit_ri.<br>
+ ///<br>
+ /// It first tries to emit an instruction with an immediate operand using<br>
+ /// FastEmit_ri. If that fails, it materializes the immediate into a register<br>
+ /// and try FastEmit_rr instead.<br>
unsigned FastEmit_ri_(MVT VT,<br>
unsigned Opcode,<br>
unsigned Op0, bool Op0IsKill,<br>
uint64_t Imm, MVT ImmType);<br>
<br>
- /// FastEmit_i - This method is called by target-independent code<br>
- /// to request that an instruction with the given type, opcode, and<br>
- /// immediate operand be emitted.<br>
+ /// This method is called by target-independent code to request that an<br>
+ /// instruction with the given type, opcode, and immediate operand be emitted.<br>
virtual unsigned FastEmit_i(MVT VT,<br>
MVT RetVT,<br>
unsigned Opcode,<br>
uint64_t Imm);<br>
<br>
- /// FastEmit_f - This method is called by target-independent code<br>
- /// to request that an instruction with the given type, opcode, and<br>
- /// floating-point immediate operand be emitted.<br>
+ /// This method is called by target-independent code to request that an<br>
+ /// instruction with the given type, opcode, and floating-point immediate<br>
+ /// operand be emitted.<br>
virtual unsigned FastEmit_f(MVT VT,<br>
MVT RetVT,<br>
unsigned Opcode,<br>
const ConstantFP *FPImm);<br>
<br>
- /// FastEmitInst_ - Emit a MachineInstr with no operands and a<br>
- /// result register in the given register class.<br>
- ///<br>
+ /// Emit a MachineInstr with no operands and a result register in the given<br>
+ /// register class.<br>
unsigned FastEmitInst_(unsigned MachineInstOpcode,<br>
const TargetRegisterClass *RC);<br>
<br>
- /// FastEmitInst_r - Emit a MachineInstr with one register operand<br>
- /// and a result register in the given register class.<br>
- ///<br>
+ /// Emit a MachineInstr with one register operand and a result register in the<br>
+ /// given register class.<br>
unsigned FastEmitInst_r(unsigned MachineInstOpcode,<br>
const TargetRegisterClass *RC,<br>
unsigned Op0, bool Op0IsKill);<br>
<br>
- /// FastEmitInst_rr - Emit a MachineInstr with two register operands<br>
- /// and a result register in the given register class.<br>
- ///<br>
+ /// Emit a MachineInstr with two register operands and a result register in<br>
+ /// the given register class.<br>
unsigned FastEmitInst_rr(unsigned MachineInstOpcode,<br>
const TargetRegisterClass *RC,<br>
unsigned Op0, bool Op0IsKill,<br>
unsigned Op1, bool Op1IsKill);<br>
<br>
- /// FastEmitInst_rrr - Emit a MachineInstr with three register operands<br>
- /// and a result register in the given register class.<br>
- ///<br>
+ /// Emit a MachineInstr with three register operands and a result register in<br>
+ /// the given register class.<br>
unsigned FastEmitInst_rrr(unsigned MachineInstOpcode,<br>
const TargetRegisterClass *RC,<br>
unsigned Op0, bool Op0IsKill,<br>
unsigned Op1, bool Op1IsKill,<br>
unsigned Op2, bool Op2IsKill);<br>
<br>
- /// FastEmitInst_ri - Emit a MachineInstr with a register operand,<br>
- /// an immediate, and a result register in the given register class.<br>
- ///<br>
+ /// Emit a MachineInstr with a register operand, an immediate, and a result<br>
+ /// register in the given register class.<br>
unsigned FastEmitInst_ri(unsigned MachineInstOpcode,<br>
const TargetRegisterClass *RC,<br>
unsigned Op0, bool Op0IsKill,<br>
uint64_t Imm);<br>
<br>
- /// FastEmitInst_rii - Emit a MachineInstr with one register operand<br>
- /// and two immediate operands.<br>
- ///<br>
+ /// Emit a MachineInstr with one register operand and two immediate operands.<br>
unsigned FastEmitInst_rii(unsigned MachineInstOpcode,<br>
const TargetRegisterClass *RC,<br>
unsigned Op0, bool Op0IsKill,<br>
uint64_t Imm1, uint64_t Imm2);<br>
<br>
- /// FastEmitInst_rf - Emit a MachineInstr with two register operands<br>
- /// and a result register in the given register class.<br>
- ///<br>
+ /// Emit a MachineInstr with two register operands and a result register in<br>
+ /// the given register class.<br>
unsigned FastEmitInst_rf(unsigned MachineInstOpcode,<br>
const TargetRegisterClass *RC,<br>
unsigned Op0, bool Op0IsKill,<br>
const ConstantFP *FPImm);<br>
<br>
- /// FastEmitInst_rri - Emit a MachineInstr with two register operands,<br>
- /// an immediate, and a result register in the given register class.<br>
- ///<br>
+ /// Emit a MachineInstr with two register operands, an immediate, and a result<br>
+ /// register in the given register class.<br>
unsigned FastEmitInst_rri(unsigned MachineInstOpcode,<br>
const TargetRegisterClass *RC,<br>
unsigned Op0, bool Op0IsKill,<br>
unsigned Op1, bool Op1IsKill,<br>
uint64_t Imm);<br>
<br>
- /// FastEmitInst_rrii - Emit a MachineInstr with two register operands,<br>
- /// two immediates operands, and a result register in the given register<br>
- /// class.<br>
+ /// Emit a MachineInstr with two register operands, two immediates operands,<br>
+ /// and a result register in the given register class.<br>
unsigned FastEmitInst_rrii(unsigned MachineInstOpcode,<br>
const TargetRegisterClass *RC,<br>
unsigned Op0, bool Op0IsKill,<br>
unsigned Op1, bool Op1IsKill,<br>
uint64_t Imm1, uint64_t Imm2);<br>
<br>
- /// FastEmitInst_i - Emit a MachineInstr with a single immediate<br>
- /// operand, and a result register in the given register class.<br>
+ /// Emit a MachineInstr with a single immediate operand, and a result register<br>
+ /// in the given register class.<br>
unsigned FastEmitInst_i(unsigned MachineInstrOpcode,<br>
const TargetRegisterClass *RC,<br>
uint64_t Imm);<br>
<br>
- /// FastEmitInst_ii - Emit a MachineInstr with a two immediate operands.<br>
+ /// Emit a MachineInstr with a two immediate operands.<br>
unsigned FastEmitInst_ii(unsigned MachineInstrOpcode,<br>
const TargetRegisterClass *RC,<br>
uint64_t Imm1, uint64_t Imm2);<br>
<br>
- /// FastEmitInst_extractsubreg - Emit a MachineInstr for an extract_subreg<br>
- /// from a specified index of a superregister to a specified type.<br>
+ /// Emit a MachineInstr for an extract_subreg from a specified index of a<br>
+ /// superregister to a specified type.<br>
unsigned FastEmitInst_extractsubreg(MVT RetVT,<br>
unsigned Op0, bool Op0IsKill,<br>
uint32_t Idx);<br>
<br>
- /// FastEmitZExtFromI1 - Emit MachineInstrs to compute the value of Op<br>
- /// with all but the least significant bit set to zero.<br>
+ /// Emit MachineInstrs to compute the value of Op with all but the least<br>
+ /// significant bit set to zero.<br>
unsigned FastEmitZExtFromI1(MVT VT,<br>
unsigned Op0, bool Op0IsKill);<br>
<br>
- /// FastEmitBranch - Emit an unconditional branch to the given block,<br>
- /// unless it is the immediate (fall-through) successor, and update<br>
- /// the CFG.<br>
+ /// Emit an unconditional branch to the given block, unless it is the<br>
+ /// immediate (fall-through) successor, and update the CFG.<br>
void FastEmitBranch(MachineBasicBlock *MBB, DebugLoc DL);<br>
<br>
void UpdateValueMap(const Value* I, unsigned Reg, unsigned NumRegs = 1);<br>
<br>
unsigned createResultReg(const TargetRegisterClass *RC);<br>
<br>
- /// TargetMaterializeConstant - Emit a constant in a register using<br>
- /// target-specific logic, such as constant pool loads.<br>
+ /// Emit a constant in a register using target-specific logic, such as<br>
+ /// constant pool loads.<br>
virtual unsigned TargetMaterializeConstant(const Constant* C) {<br>
return 0;<br>
}<br>
<br>
- /// TargetMaterializeAlloca - Emit an alloca address in a register using<br>
- /// target-specific logic.<br>
+ /// Emit an alloca address in a register using target-specific logic.<br>
virtual unsigned TargetMaterializeAlloca(const AllocaInst* C) {<br>
return 0;<br>
}<br>
@@ -404,25 +375,26 @@ private:<br>
<br>
bool SelectInsertValue(const User *I);<br>
<br>
- /// HandlePHINodesInSuccessorBlocks - Handle PHI nodes in successor blocks.<br>
+ /// \brief Handle PHI nodes in successor blocks.<br>
+ ///<br>
/// Emit code to ensure constants are copied into registers when needed.<br>
/// Remember the virtual registers that need to be added to the Machine PHI<br>
- /// nodes as input. We cannot just directly add them, because expansion<br>
- /// might result in multiple MBB's for one BB. As such, the start of the<br>
- /// BB might correspond to a different MBB than the end.<br>
+ /// nodes as input. We cannot just directly add them, because expansion might<br>
+ /// result in multiple MBB's for one BB. As such, the start of the BB might<br>
+ /// correspond to a different MBB than the end.<br>
bool HandlePHINodesInSuccessorBlocks(const BasicBlock *LLVMBB);<br>
<br>
- /// materializeRegForValue - Helper for getRegForVale. This function is<br>
- /// called when the value isn't already available in a register and must<br>
- /// be materialized with new instructions.<br>
+ /// Helper for getRegForVale. This function is called when the value isn't<br>
+ /// already available in a register and must be materialized with new<br>
+ /// instructions.<br>
unsigned materializeRegForValue(const Value *V, MVT VT);<br>
<br>
- /// flushLocalValueMap - clears LocalValueMap and moves the area for the<br>
- /// new local variables to the beginning of the block. It helps to avoid<br>
- /// spilling cached variables across heavy instructions like calls.<br>
+ /// Clears LocalValueMap and moves the area for the new local variables to the<br>
+ /// beginning of the block. It helps to avoid spilling cached variables across<br>
+ /// heavy instructions like calls.<br>
void flushLocalValueMap();<br>
<br>
- /// hasTrivialKill - Test whether the given value has exactly one use.<br>
+ /// Test whether the given value has exactly one use.<br>
bool hasTrivialKill(const Value *V) const;<br>
};<br>
<br>
<br>
<br>
<br>
<br>
------------------------------<br>
<br>
Message: 9<br>
Date: Tue, 09 Jul 2013 20:28:37 -0000<br>
From: Adrian Prantl <<a href="mailto:aprantl@apple.com" target="_blank">aprantl@apple.com</a>><br>
To: <a href="mailto:llvm-commits@cs.uiuc.edu" target="_blank">llvm-commits@cs.uiuc.edu</a><br>
Subject: [llvm] r185966 - Reapply an improved version of<br>
r180816/180817.<br>
Message-ID: <<a href="mailto:20130709202838.5B2422A6C029@llvm.org" target="_blank">20130709202838.5B2422A6C029@llvm.org</a>><br>
Content-Type: text/plain; charset="utf-8"<br>
<br>
Author: adrian<br>
Date: Tue Jul 9 15:28:37 2013<br>
New Revision: 185966<br>
<br>
URL: <a href="http://llvm.org/viewvc/llvm-project?rev=185966&view=rev" target="_blank">http://llvm.org/viewvc/llvm-project?rev=185966&view=rev</a><br>
Log:<br>
Reapply an improved version of r180816/180817.<br>
<br>
Change the informal convention of DBG_VALUE machine instructions so that<br>
we can express a register-indirect address with an offset of 0.<br>
The old convention was that a DBG_VALUE is a register-indirect value if<br>
the offset (operand 1) is nonzero. The new convention is that a DBG_VALUE<br>
is register-indirect if the first operand is a register and the second<br>
operand is an immediate. For plain register values the combination reg,<br>
reg is used. MachineInstrBuilder::BuildMI knows how to build the new<br>
DBG_VALUES.<br>
<br>
rdar://problem/13658587<br>
<br>
Added:<br>
llvm/trunk/test/DebugInfo/X86/vla.ll<br>
Modified:<br>
llvm/trunk/include/llvm/CodeGen/MachineInstrBuilder.h<br>
llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp<br>
llvm/trunk/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp<br>
llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp<br>
llvm/trunk/lib/CodeGen/LiveDebugVariables.cpp<br>
llvm/trunk/lib/CodeGen/RegAllocFast.cpp<br>
llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp<br>
llvm/trunk/lib/CodeGen/SelectionDAG/InstrEmitter.cpp<br>
llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp<br>
llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp<br>
llvm/trunk/test/CodeGen/X86/dbg-value-range.ll<br>
llvm/trunk/test/DebugInfo/X86/op_deref.ll<br>
llvm/trunk/test/DebugInfo/X86/parameters.ll<br>
<br>
Modified: llvm/trunk/include/llvm/CodeGen/MachineInstrBuilder.h<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/MachineInstrBuilder.h?rev=185966&r1=185965&r2=185966&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/MachineInstrBuilder.h?rev=185966&r1=185965&r2=185966&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/include/llvm/CodeGen/MachineInstrBuilder.h (original)<br>
+++ llvm/trunk/include/llvm/CodeGen/MachineInstrBuilder.h Tue Jul 9 15:28:37 2013<br>
@@ -335,6 +335,51 @@ inline MachineInstrBuilder BuildMI(Machi<br>
return BuildMI(*BB, BB->end(), DL, MCID, DestReg);<br>
}<br>
<br>
+/// BuildMI - This version of the builder builds a DBG_VALUE intrinsic<br>
+/// for either a value in a register or a register-indirect+offset<br>
+/// address. The convention is that a DBG_VALUE is indirect iff the<br>
+/// second operand is an immediate.<br>
+///<br>
+inline MachineInstrBuilder BuildMI(MachineFunction &MF,<br>
+ DebugLoc DL,<br>
+ const MCInstrDesc &MCID,<br>
+ bool IsIndirect,<br>
+ unsigned Reg,<br>
+ unsigned Offset,<br>
+ const MDNode *MD) {<br>
+ if (IsIndirect)<br>
+ return BuildMI(MF, DL, MCID)<br>
+ .addReg(Reg, RegState::Debug)<br>
+ .addImm(Offset)<br>
+ .addMetadata(MD);<br>
+ else {<br>
+ assert(Offset == 0 && "A direct address cannot have an offset.");<br>
+ return BuildMI(MF, DL, MCID)<br>
+ .addReg(Reg, RegState::Debug)<br>
+ .addReg(0U, RegState::Debug)<br>
+ .addMetadata(MD);<br>
+ }<br>
+}<br>
+<br>
+/// BuildMI - This version of the builder builds a DBG_VALUE intrinsic<br>
+/// for either a value in a register or a register-indirect+offset<br>
+/// address and inserts it at position I.<br>
+///<br>
+inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB,<br>
+ MachineBasicBlock::iterator I,<br>
+ DebugLoc DL,<br>
+ const MCInstrDesc &MCID,<br>
+ bool IsIndirect,<br>
+ unsigned Reg,<br>
+ unsigned Offset,<br>
+ const MDNode *MD) {<br>
+ MachineFunction &MF = *BB.getParent();<br>
+ MachineInstr *MI = BuildMI(MF, DL, MCID, IsIndirect, Reg, Offset, MD);<br>
+ BB.insert(I, MI);<br>
+ return MachineInstrBuilder(MF, MI);<br>
+}<br>
+<br>
+<br>
inline unsigned getDefRegState(bool B) {<br>
return B ? RegState::Define : 0;<br>
}<br>
<br>
Modified: llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp?rev=185966&r1=185965&r2=185966&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp?rev=185966&r1=185965&r2=185966&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp (original)<br>
+++ llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp Tue Jul 9 15:28:37 2013<br>
@@ -570,8 +570,10 @@ static bool emitDebugValueComment(const<br>
}<br>
OS << V.getName() << " <- ";<br>
<br>
- int64_t Offset = MI->getOperand(1).getImm();<br>
- bool Deref = false;<br>
+ // The second operand is only an offset if it's an immediate.<br>
+ bool Deref = MI->getOperand(0).isReg() && MI->getOperand(1).isImm();<br>
+ int64_t Offset = Deref ? MI->getOperand(1).getImm() : 0;<br>
+<br>
// Register or immediate value. Register 0 means undef.<br>
if (MI->getOperand(0).isFPImm()) {<br>
APFloat APF = APFloat(MI->getOperand(0).getFPImm()->getValueAPF());<br>
@@ -595,8 +597,6 @@ static bool emitDebugValueComment(const<br>
unsigned Reg;<br>
if (MI->getOperand(0).isReg()) {<br>
Reg = MI->getOperand(0).getReg();<br>
- Deref = Offset != 0; // FIXME: use a better sentinel value so that deref<br>
- // of a reg with a zero offset is valid<br>
} else {<br>
assert(MI->getOperand(0).isFI() && "Unknown operand type");<br>
const TargetFrameLowering *TFI = AP.TM.getFrameLowering();<br>
@@ -616,10 +616,9 @@ static bool emitDebugValueComment(const<br>
OS << AP.TM.getRegisterInfo()->getName(Reg);<br>
}<br>
<br>
- if (Offset)<br>
- OS << '+' << Offset;<br>
if (Deref)<br>
- OS << ']';<br>
+ OS << '+' << Offset << ']';<br>
+<br>
// NOTE: Want this comment at start of line, don't emit with AddComment.<br>
AP.OutStreamer.EmitRawText(OS.str());<br>
return true;<br>
<br>
Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp?rev=185966&r1=185965&r2=185966&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp?rev=185966&r1=185965&r2=185966&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp (original)<br>
+++ llvm/trunk/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp Tue Jul 9 15:28:37 2013<br>
@@ -1563,8 +1563,9 @@ DIE *CompileUnit::constructVariableDIE(D<br>
assert(DVInsn->getNumOperands() == 3);<br>
if (DVInsn->getOperand(0).isReg()) {<br>
const MachineOperand RegOp = DVInsn->getOperand(0);<br>
- if (int64_t Offset = DVInsn->getOperand(1).getImm()) {<br>
- MachineLocation Location(RegOp.getReg(), Offset);<br>
+ // If the second operand is an immedieate, this is an indirect value.<br>
+ if (DVInsn->getOperand(1).isImm()) {<br>
+ MachineLocation Location(RegOp.getReg(), DVInsn->getOperand(1).getImm());<br>
addVariableAddress(*DV, VariableDie, Location);<br>
} else if (RegOp.getReg())<br>
addVariableAddress(*DV, VariableDie, MachineLocation(RegOp.getReg()));<br>
<br>
Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp?rev=185966&r1=185965&r2=185966&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp?rev=185966&r1=185965&r2=185966&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp (original)<br>
+++ llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp Tue Jul 9 15:28:37 2013<br>
@@ -1184,7 +1184,8 @@ static bool isDbgValueInDefinedReg(const<br>
assert(MI->isDebugValue() && "Invalid DBG_VALUE machine instruction!");<br>
return MI->getNumOperands() == 3 &&<br>
MI->getOperand(0).isReg() && MI->getOperand(0).getReg() &&<br>
- MI->getOperand(1).isImm() && MI->getOperand(1).getImm() == 0;<br>
+ (MI->getOperand(1).isImm() ||<br>
+ (MI->getOperand(1).isReg() && MI->getOperand(1).getReg() == 0U));<br>
}<br>
<br>
// Get .debug_loc entry for the instruction range starting at MI.<br>
@@ -1195,12 +1196,11 @@ static DotDebugLocEntry getDebugLocEntry<br>
const MDNode *Var = MI->getOperand(MI->getNumOperands() - 1).getMetadata();<br>
<br>
assert(MI->getNumOperands() == 3);<br>
- if (MI->getOperand(0).isReg() && MI->getOperand(1).isImm()) {<br>
+ if (MI->getOperand(0).isReg()) {<br>
MachineLocation MLoc;<br>
- // TODO: Currently an offset of 0 in a DBG_VALUE means<br>
- // we need to generate a direct register value.<br>
- // There is no way to specify an indirect value with offset 0.<br>
- if (MI->getOperand(1).getImm() == 0)<br>
+ // If the second operand is an immediate, this is a<br>
+ // register-indirect address.<br>
+ if (!MI->getOperand(1).isImm())<br>
MLoc.set(MI->getOperand(0).getReg());<br>
else<br>
MLoc.set(MI->getOperand(0).getReg(), MI->getOperand(1).getImm());<br>
<br>
Modified: llvm/trunk/lib/CodeGen/LiveDebugVariables.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LiveDebugVariables.cpp?rev=185966&r1=185965&r2=185966&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LiveDebugVariables.cpp?rev=185966&r1=185965&r2=185966&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/CodeGen/LiveDebugVariables.cpp (original)<br>
+++ llvm/trunk/lib/CodeGen/LiveDebugVariables.cpp Tue Jul 9 15:28:37 2013<br>
@@ -108,6 +108,7 @@ class LDVImpl;<br>
class UserValue {<br>
const MDNode *variable; ///< The debug info variable we are part of.<br>
unsigned offset; ///< Byte offset into variable.<br>
+ bool IsIndirect; ///< true if this is a register-indirect+offset value.<br>
DebugLoc dl; ///< The debug location for the variable. This is<br>
///< used by dwarf writer to find lexical scope.<br>
UserValue *leader; ///< Equivalence class leader.<br>
@@ -134,9 +135,10 @@ class UserValue {<br>
<br>
public:<br>
/// UserValue - Create a new UserValue.<br>
- UserValue(const MDNode *var, unsigned o, DebugLoc L,<br>
+ UserValue(const MDNode *var, unsigned o, bool i, DebugLoc L,<br>
LocMap::Allocator &alloc)<br>
- : variable(var), offset(o), dl(L), leader(this), next(0), locInts(alloc)<br>
+ : variable(var), offset(o), IsIndirect(i), dl(L), leader(this),<br>
+ next(0), locInts(alloc)<br>
{}<br>
<br>
/// getLeader - Get the leader of this value's equivalence class.<br>
@@ -299,7 +301,8 @@ class LDVImpl {<br>
UVMap userVarMap;<br>
<br>
/// getUserValue - Find or create a UserValue.<br>
- UserValue *getUserValue(const MDNode *Var, unsigned Offset, DebugLoc DL);<br>
+ UserValue *getUserValue(const MDNode *Var, unsigned Offset,<br>
+ bool IsIndirect, DebugLoc DL);<br>
<br>
/// lookupVirtReg - Find the EC leader for VirtReg or null.<br>
UserValue *lookupVirtReg(unsigned VirtReg);<br>
@@ -414,7 +417,7 @@ void UserValue::mapVirtRegs(LDVImpl *LDV<br>
}<br>
<br>
UserValue *LDVImpl::getUserValue(const MDNode *Var, unsigned Offset,<br>
- DebugLoc DL) {<br>
+ bool IsIndirect, DebugLoc DL) {<br>
UserValue *&Leader = userVarMap[Var];<br>
if (Leader) {<br>
UserValue *UV = Leader->getLeader();<br>
@@ -424,7 +427,7 @@ UserValue *LDVImpl::getUserValue(const M<br>
return UV;<br>
}<br>
<br>
- UserValue *UV = new UserValue(Var, Offset, DL, allocator);<br>
+ UserValue *UV = new UserValue(Var, Offset, IsIndirect, DL, allocator);<br>
userValues.push_back(UV);<br>
Leader = UserValue::merge(Leader, UV);<br>
return UV;<br>
@@ -445,15 +448,17 @@ UserValue *LDVImpl::lookupVirtReg(unsign<br>
bool LDVImpl::handleDebugValue(MachineInstr *MI, SlotIndex Idx) {<br>
// DBG_VALUE loc, offset, variable<br>
if (MI->getNumOperands() != 3 ||<br>
- !MI->getOperand(1).isImm() || !MI->getOperand(2).isMetadata()) {<br>
+ !(MI->getOperand(1).isReg() || MI->getOperand(1).isImm()) ||<br>
+ !MI->getOperand(2).isMetadata()) {<br>
DEBUG(dbgs() << "Can't handle " << *MI);<br>
return false;<br>
}<br>
<br>
// Get or create the UserValue for (variable,offset).<br>
- unsigned Offset = MI->getOperand(1).getImm();<br>
+ bool IsIndirect = MI->getOperand(1).isImm();<br>
+ unsigned Offset = IsIndirect ? MI->getOperand(1).getImm() : 0;<br>
const MDNode *Var = MI->getOperand(2).getMetadata();<br>
- UserValue *UV = getUserValue(Var, Offset, MI->getDebugLoc());<br>
+ UserValue *UV = getUserValue(Var, Offset, IsIndirect, MI->getDebugLoc());<br>
UV->addDef(Idx, MI->getOperand(0));<br>
return true;<br>
}<br>
@@ -921,8 +926,12 @@ void UserValue::insertDebugValue(Machine<br>
MachineOperand &Loc = locations[LocNo];<br>
++NumInsertedDebugValues;<br>
<br>
- BuildMI(*MBB, I, findDebugLoc(), TII.get(TargetOpcode::DBG_VALUE))<br>
- .addOperand(Loc).addImm(offset).addMetadata(variable);<br>
+ if (Loc.isReg())<br>
+ BuildMI(*MBB, I, findDebugLoc(), TII.get(TargetOpcode::DBG_VALUE),<br>
+ IsIndirect, Loc.getReg(), offset, variable);<br>
+ else<br>
+ BuildMI(*MBB, I, findDebugLoc(), TII.get(TargetOpcode::DBG_VALUE))<br>
+ .addOperand(Loc).addImm(offset).addMetadata(variable);<br>
}<br>
<br>
void UserValue::emitDebugValues(VirtRegMap *VRM, LiveIntervals &LIS,<br>
<br>
Modified: llvm/trunk/lib/CodeGen/RegAllocFast.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegAllocFast.cpp?rev=185966&r1=185965&r2=185966&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegAllocFast.cpp?rev=185966&r1=185965&r2=185966&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/CodeGen/RegAllocFast.cpp (original)<br>
+++ llvm/trunk/lib/CodeGen/RegAllocFast.cpp Tue Jul 9 15:28:37 2013<br>
@@ -298,7 +298,8 @@ void RAFast::spillVirtReg(MachineBasicBl<br>
for (unsigned li = 0, le = LRIDbgValues.size(); li != le; ++li) {<br>
MachineInstr *DBG = LRIDbgValues[li];<br>
const MDNode *MDPtr = DBG->getOperand(2).getMetadata();<br>
- int64_t Offset = DBG->getOperand(1).getImm();<br>
+ bool IsIndirect = DBG->getOperand(1).isImm(); // Register-indirect value?<br>
+ int64_t Offset = IsIndirect ? DBG->getOperand(1).getImm() : 0;<br>
DebugLoc DL;<br>
if (MI == MBB->end()) {<br>
// If MI is at basic block end then use last instruction's location.<br>
<br>
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp?rev=185966&r1=185965&r2=185966&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp?rev=185966&r1=185965&r2=185966&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp (original)<br>
+++ llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp Tue Jul 9 15:28:37 2013<br>
@@ -612,11 +612,13 @@ bool FastISel::SelectCall(const User *I)<br>
return true;<br>
}<br>
<br>
+ unsigned Offset = 0;<br>
Optional<MachineOperand> Op;<br>
if (const Argument *Arg = dyn_cast<Argument>(Address))<br>
// Some arguments' frame index is recorded during argument lowering.<br>
- if (int FI = FuncInfo.getArgumentFrameIndex(Arg))<br>
- Op = MachineOperand::CreateFI(FI);<br>
+ Offset = FuncInfo.getArgumentFrameIndex(Arg);<br>
+ if (Offset)<br>
+ Op = MachineOperand::CreateFI(Offset);<br>
if (!Op)<br>
if (unsigned Reg = lookUpRegForValue(Address))<br>
Op = MachineOperand::CreateReg(Reg, false);<br>
@@ -638,12 +640,16 @@ bool FastISel::SelectCall(const User *I)<br>
Op = MachineOperand::CreateReg(FuncInfo.InitializeRegForValue(Address),<br>
false);<br>
<br>
- if (Op && Op->isReg())<br>
- Op->setIsDebug(true);<br>
-<br>
if (Op)<br>
- BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,<br>
- TII.get(TargetOpcode::DBG_VALUE)).addOperand(*Op).addImm(0)<br>
+ if (Op->isReg()) {<br>
+ Op->setIsDebug(true);<br>
+ BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,<br>
+ TII.get(TargetOpcode::DBG_VALUE),<br>
+ /* IsIndirect */ DI->getAddress()->getType()->isPointerTy(),<br>
+ Op->getReg(), Offset, DI->getVariable());<br>
+ } else<br>
+ BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,<br>
+ TII.get(TargetOpcode::DBG_VALUE)).addOperand(*Op).addImm(0)<br>
.addMetadata(DI->getVariable());<br>
else<br>
// We can't yet handle anything else here because it would require<br>
@@ -676,9 +682,9 @@ bool FastISel::SelectCall(const User *I)<br>
.addFPImm(CF).addImm(DI->getOffset())<br>
.addMetadata(DI->getVariable());<br>
} else if (unsigned Reg = lookUpRegForValue(V)) {<br>
- BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)<br>
- .addReg(Reg, RegState::Debug).addImm(DI->getOffset())<br>
- .addMetadata(DI->getVariable());<br>
+ bool IsIndirect = DI->getOffset() != 0;<br>
+ BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, IsIndirect,<br>
+ Reg, DI->getOffset(), DI->getVariable());<br>
} else {<br>
// We can't yet handle anything else here because it would require<br>
// generating code, thus altering codegen because of debug info.<br>
<br>
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/InstrEmitter.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/InstrEmitter.cpp?rev=185966&r1=185965&r2=185966&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/InstrEmitter.cpp?rev=185966&r1=185965&r2=185966&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/CodeGen/SelectionDAG/InstrEmitter.cpp (original)<br>
+++ llvm/trunk/lib/CodeGen/SelectionDAG/InstrEmitter.cpp Tue Jul 9 15:28:37 2013<br>
@@ -678,7 +678,13 @@ InstrEmitter::EmitDbgValue(SDDbgValue *S<br>
MIB.addReg(0U);<br>
}<br>
<br>
- MIB.addImm(Offset).addMetadata(MDPtr);<br>
+ if (Offset != 0) // Indirect addressing.<br>
+ MIB.addImm(Offset);<br>
+ else<br>
+ MIB.addReg(0U, RegState::Debug);<br>
+<br>
+ MIB.addMetadata(MDPtr);<br>
+<br>
return &*MIB;<br>
}<br>
<br>
<br>
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp?rev=185966&r1=185965&r2=185966&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp?rev=185966&r1=185965&r2=185966&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp (original)<br>
+++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp Tue Jul 9 15:28:37 2013<br>
@@ -4422,11 +4422,15 @@ SelectionDAGBuilder::EmitFuncArgumentDbg<br>
return false;<br>
<br>
if (Op->isReg())<br>
- Op->setIsDebug();<br>
-<br>
- FuncInfo.ArgDbgValues.push_back(<br>
+ FuncInfo.ArgDbgValues.push_back(BuildMI(MF, getCurDebugLoc(),<br>
+ TII->get(TargetOpcode::DBG_VALUE),<br>
+ /* IsIndirect */ Offset != 0,<br>
+ Op->getReg(), Offset, Variable));<br>
+ else<br>
+ FuncInfo.ArgDbgValues.push_back(<br>
BuildMI(MF, getCurDebugLoc(), TII->get(TargetOpcode::DBG_VALUE))<br>
.addOperand(*Op).addImm(Offset).addMetadata(Variable));<br>
+<br>
return true;<br>
}<br>
<br>
<br>
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp?rev=185966&r1=185965&r2=185966&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp?rev=185966&r1=185965&r2=185966&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp (original)<br>
+++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Tue Jul 9 15:28:37 2013<br>
@@ -421,12 +421,13 @@ bool SelectionDAGISel::runOnMachineFunct<br>
MachineBasicBlock::iterator InsertPos = Def;<br>
const MDNode *Variable =<br>
MI->getOperand(MI->getNumOperands()-1).getMetadata();<br>
- unsigned Offset = MI->getOperand(1).getImm();<br>
+ bool IsIndirect = MI->getOperand(1).isImm();<br>
+ unsigned Offset = IsIndirect ? MI->getOperand(1).getImm() : 0;<br>
// Def is never a terminator here, so it is ok to increment InsertPos.<br>
BuildMI(*EntryMBB, ++InsertPos, MI->getDebugLoc(),<br>
- TII.get(TargetOpcode::DBG_VALUE))<br>
- .addReg(LDI->second, RegState::Debug)<br>
- .addImm(Offset).addMetadata(Variable);<br>
+ TII.get(TargetOpcode::DBG_VALUE),<br>
+ IsIndirect,<br>
+ LDI->second, Offset, Variable);<br>
<br>
// If this vreg is directly copied into an exported register then<br>
// that COPY instructions also need DBG_VALUE, if it is the only<br>
@@ -445,9 +446,10 @@ bool SelectionDAGISel::runOnMachineFunct<br>
if (CopyUseMI) {<br>
MachineInstr *NewMI =<br>
BuildMI(*MF, CopyUseMI->getDebugLoc(),<br>
- TII.get(TargetOpcode::DBG_VALUE))<br>
- .addReg(CopyUseMI->getOperand(0).getReg(), RegState::Debug)<br>
- .addImm(Offset).addMetadata(Variable);<br>
+ TII.get(TargetOpcode::DBG_VALUE),<br>
+ IsIndirect,<br>
+ CopyUseMI->getOperand(0).getReg(),<br>
+ Offset, Variable);<br>
MachineBasicBlock::iterator Pos = CopyUseMI;<br>
EntryMBB->insertAfter(Pos, NewMI);<br>
}<br>
<br>
Modified: llvm/trunk/test/CodeGen/X86/dbg-value-range.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/dbg-value-range.ll?rev=185966&r1=185965&r2=185966&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/dbg-value-range.ll?rev=185966&r1=185965&r2=185966&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/X86/dbg-value-range.ll (original)<br>
+++ llvm/trunk/test/CodeGen/X86/dbg-value-range.ll Tue Jul 9 15:28:37 2013<br>
@@ -40,7 +40,7 @@ declare void @llvm.dbg.value(metadata, i<br>
!21 = metadata !{metadata !6, metadata !11}<br>
!22 = metadata !{metadata !"bar.c", metadata !"/private/tmp"}<br>
<br>
-; Check that variable bar:b value range is appropriately trucated in debug info.<br>
+; Check that variable bar:b value range is appropriately truncated in debug info.<br>
; The variable is in %rdi which is clobbered by 'movl %ebx, %edi'<br>
; Here Ltmp7 is the end of the location range.<br>
<br>
@@ -54,7 +54,7 @@ declare void @llvm.dbg.value(metadata, i<br>
;CHECK-NEXT: Lset{{.*}} = Ltmp{{.*}}-Ltmp{{.*}}<br>
;CHECK-NEXT: .short Lset<br>
;CHECK-NEXT: Ltmp<br>
-;CHECK-NEXT: .byte 85<br>
+;CHECK-NEXT: .byte 85 ## DW_OP_reg<br>
;CHECK-NEXT: Ltmp<br>
;CHECK-NEXT: .quad 0<br>
;CHECK-NEXT: .quad 0<br>
<br>
Modified: llvm/trunk/test/DebugInfo/X86/op_deref.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/DebugInfo/X86/op_deref.ll?rev=185966&r1=185965&r2=185966&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/DebugInfo/X86/op_deref.ll?rev=185966&r1=185965&r2=185966&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/DebugInfo/X86/op_deref.ll (original)<br>
+++ llvm/trunk/test/DebugInfo/X86/op_deref.ll Tue Jul 9 15:28:37 2013<br>
@@ -1,10 +1,16 @@<br>
; RUN: llc -O0 -mtriple=x86_64-apple-darwin %s -o %t -filetype=obj<br>
-; RUN: llvm-dwarfdump -debug-dump=info %t | FileCheck %s<br>
+; RUN: llvm-dwarfdump -debug-dump=info %t | FileCheck %s -check-prefix=DW-CHECK<br>
<br>
-; CHECK: DW_AT_name [DW_FORM_strp] ( .debug_str[0x00000067] = "vla")<br>
+; DW-CHECK: DW_AT_name [DW_FORM_strp] ( .debug_str[0x00000067] = "vla")<br>
; FIXME: The location here needs to be fixed, but llvm-dwarfdump doesn't handle<br>
; DW_AT_location lists yet.<br>
-; CHECK: DW_AT_location [DW_FORM_data4] (0x00000000)<br>
+; DW-CHECK: DW_AT_location [DW_FORM_data4] (0x00000000)<br>
+<br>
+; Unfortunately llvm-dwarfdump can't unparse a list of DW_AT_locations<br>
+; right now, so we check the asm output:<br>
+; RUN: llc -O0 -mtriple=x86_64-apple-darwin %s -o - -filetype=asm | FileCheck %s -check-prefix=ASM-CHECK<br>
+; vla should have a register-indirect address at one point.<br>
+; ASM-CHECK: DEBUG_VALUE: vla <- [RCX+0]<br>
<br>
define void @testVLAwithSize(i32 %s) nounwind uwtable ssp {<br>
entry:<br>
<br>
Modified: llvm/trunk/test/DebugInfo/X86/parameters.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/DebugInfo/X86/parameters.ll?rev=185966&r1=185965&r2=185966&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/DebugInfo/X86/parameters.ll?rev=185966&r1=185965&r2=185966&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/DebugInfo/X86/parameters.ll (original)<br>
+++ llvm/trunk/test/DebugInfo/X86/parameters.ll Tue Jul 9 15:28:37 2013<br>
@@ -24,9 +24,9 @@<br>
<br>
; CHECK: debug_info contents<br>
; CHECK: DW_AT_name{{.*}} = "f"<br>
-; 0x74 is DW_OP_breg0 + 4, showing that the parameter is accessed indirectly<br>
+; 0x74 is DW_OP_breg4, showing that the parameter is accessed indirectly<br>
; (with a zero offset) from the register parameter<br>
-; CHECK: DW_AT_location{{.*}}(<0x02> 74 00 )<br>
+; CHECK: DW_AT_location{{.*}}(<0x0{{.}}> 74 00<br>
<br>
; CHECK: DW_AT_name{{.*}} = "g"<br>
; CHECK: DW_AT_location{{.*}}([[G_LOC:0x[0-9]*]])<br>
<br>
Added: llvm/trunk/test/DebugInfo/X86/vla.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/DebugInfo/X86/vla.ll?rev=185966&view=auto" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/DebugInfo/X86/vla.ll?rev=185966&view=auto</a><br>
==============================================================================<br>
--- llvm/trunk/test/DebugInfo/X86/vla.ll (added)<br>
+++ llvm/trunk/test/DebugInfo/X86/vla.ll Tue Jul 9 15:28:37 2013<br>
@@ -0,0 +1,104 @@<br>
+; RUN: llc -O0 -mtriple=x86_64-apple-darwin -filetype=asm %s -o - | FileCheck %s<br>
+; Ensure that we generate a breg+0 location for the variable length array a.<br>
+; CHECK: ##DEBUG_VALUE: vla:a <- [RDX+0]<br>
+; rdar://problem/13658587<br>
+;<br>
+; generated from:<br>
+;<br>
+; int vla(int n) {<br>
+; int a[n];<br>
+; a[0] = 42;<br>
+; return a[n-1];<br>
+; }<br>
+;<br>
+; int main(int argc, char** argv) {<br>
+; return vla(argc);<br>
+; }<br>
+<br>
+; ModuleID = 'vla.c'<br>
+target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"<br>
+target triple = "x86_64-apple-macosx10.8.0"<br>
+<br>
+; Function Attrs: nounwind ssp uwtable<br>
+define i32 @vla(i32 %n) nounwind ssp uwtable {<br>
+entry:<br>
+ %n.addr = alloca i32, align 4<br>
+ %saved_stack = alloca i8*<br>
+ %cleanup.dest.slot = alloca i32<br>
+ store i32 %n, i32* %n.addr, align 4<br>
+ call void @llvm.dbg.declare(metadata !{i32* %n.addr}, metadata !15), !dbg !16<br>
+ %0 = load i32* %n.addr, align 4, !dbg !17<br>
+ %1 = zext i32 %0 to i64, !dbg !17<br>
+ %2 = call i8* @llvm.stacksave(), !dbg !17<br>
+ store i8* %2, i8** %saved_stack, !dbg !17<br>
+ %vla = alloca i32, i64 %1, align 16, !dbg !17<br>
+ call void @llvm.dbg.declare(metadata !{i32* %vla}, metadata !18), !dbg !17<br>
+ %arrayidx = getelementptr inbounds i32* %vla, i64 0, !dbg !22<br>
+ store i32 42, i32* %arrayidx, align 4, !dbg !22<br>
+ %3 = load i32* %n.addr, align 4, !dbg !23<br>
+ %sub = sub nsw i32 %3, 1, !dbg !23<br>
+ %idxprom = sext i32 %sub to i64, !dbg !23<br>
+ %arrayidx1 = getelementptr inbounds i32* %vla, i64 %idxprom, !dbg !23<br>
+ %4 = load i32* %arrayidx1, align 4, !dbg !23<br>
+ store i32 1, i32* %cleanup.dest.slot<br>
+ %5 = load i8** %saved_stack, !dbg !24<br>
+ call void @llvm.stackrestore(i8* %5), !dbg !24<br>
+ ret i32 %4, !dbg !23<br>
+}<br>
+<br>
+; Function Attrs: nounwind readnone<br>
+declare void @llvm.dbg.declare(metadata, metadata) nounwind readnone<br>
+<br>
+; Function Attrs: nounwind<br>
+declare i8* @llvm.stacksave() nounwind<br>
+<br>
+; Function Attrs: nounwind<br>
+declare void @llvm.stackrestore(i8*) nounwind<br>
+<br>
+; Function Attrs: nounwind ssp uwtable<br>
+define i32 @main(i32 %argc, i8** %argv) nounwind ssp uwtable {<br>
+entry:<br>
+ %retval = alloca i32, align 4<br>
+ %argc.addr = alloca i32, align 4<br>
+ %argv.addr = alloca i8**, align 8<br>
+ store i32 0, i32* %retval<br>
+ store i32 %argc, i32* %argc.addr, align 4<br>
+ call void @llvm.dbg.declare(metadata !{i32* %argc.addr}, metadata !25), !dbg !26<br>
+ store i8** %argv, i8*** %argv.addr, align 8<br>
+ call void @llvm.d</blockquote></div></div></div></div>...<br><br>[Message clipped] </blockquote></div><br></div>