<div dir="ltr">I think it helped -- thanks!</div><div class="gmail_extra"><br><br><div class="gmail_quote">2014-03-24 20:19 GMT+04:00 Tom Stellard <span dir="ltr"><<a href="mailto:tom@stellard.net" target="_blank">tom@stellard.net</a>></span>:<br>
<blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"><div class="">On Mon, Mar 24, 2014 at 03:17:11PM +0400, Timur Iskhodzhanov wrote:<br>
> FYI gcc-4.8.2 doesn't like this:<br>
> ../lib/Target/R600/SIInstrInfo.cpp: In static member function ‘static<br>
> unsigned int llvm::SIInstrInfo::getVALUOp(const llvm::MachineInstr&)’:<br>
> ../lib/Target/R600/SIInstrInfo.cpp:501:41: warning: enumeral mismatch in<br>
> conditional expression: ‘llvm::TargetOpcode::<anonymous enum>’ vs<br>
> ‘llvm::AMDGPU::<anonymous enum>’ [-Wenum-compare]<br>
> TargetOpcode::COPY : AMDGPU::V_MOV_B32_e32;<br>
><br>
<br>
</div>Should be fixed in r204618.<br>
<span class="HOEnZb"><font color="#888888"><br>
-Tom<br>
</font></span><div class="HOEnZb"><div class="h5"><br>
><br>
><br>
> 2014-03-21 19:51 GMT+04:00 Tom Stellard <<a href="mailto:thomas.stellard@amd.com">thomas.stellard@amd.com</a>>:<br>
><br>
> > Author: tstellar<br>
> > Date: Fri Mar 21 10:51:54 2014<br>
> > New Revision: 204475<br>
> ><br>
> > URL: <a href="http://llvm.org/viewvc/llvm-project?rev=204475&view=rev" target="_blank">http://llvm.org/viewvc/llvm-project?rev=204475&view=rev</a><br>
> > Log:<br>
> > R600/SI: Handle S_MOV_B64 in SIInstrInfo::moveToVALU()<br>
> ><br>
> > Added:<br>
> > llvm/trunk/test/CodeGen/R600/salu-to-valu.ll<br>
> > Modified:<br>
> > llvm/trunk/lib/Target/R600/SIInstrInfo.cpp<br>
> ><br>
> > Modified: llvm/trunk/lib/Target/R600/SIInstrInfo.cpp<br>
> > URL:<br>
> > <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/R600/SIInstrInfo.cpp?rev=204475&r1=204474&r2=204475&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/R600/SIInstrInfo.cpp?rev=204475&r1=204474&r2=204475&view=diff</a><br>
> ><br>
> > ==============================================================================<br>
> > --- llvm/trunk/lib/Target/R600/SIInstrInfo.cpp (original)<br>
> > +++ llvm/trunk/lib/Target/R600/SIInstrInfo.cpp Fri Mar 21 10:51:54 2014<br>
> > @@ -496,6 +496,9 @@ unsigned SIInstrInfo::getVALUOp(const Ma<br>
> > case AMDGPU::REG_SEQUENCE: return AMDGPU::REG_SEQUENCE;<br>
> > case AMDGPU::COPY: return AMDGPU::COPY;<br>
> > case AMDGPU::PHI: return AMDGPU::PHI;<br>
> > + case AMDGPU::S_MOV_B32:<br>
> > + return MI.getOperand(1).isReg() ?<br>
> > + TargetOpcode::COPY : AMDGPU::V_MOV_B32_e32;<br>
> > case AMDGPU::S_ADD_I32: return AMDGPU::V_ADD_I32_e32;<br>
> > case AMDGPU::S_ADDC_U32: return AMDGPU::V_ADDC_U32_e32;<br>
> > case AMDGPU::S_SUB_I32: return AMDGPU::V_SUB_I32_e32;<br>
> > @@ -680,12 +683,57 @@ void SIInstrInfo::moveToVALU(MachineInst<br>
> ><br>
> > while (!Worklist.empty()) {<br>
> > MachineInstr *Inst = Worklist.pop_back_val();<br>
> > + MachineBasicBlock *MBB = Inst->getParent();<br>
> > + MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();<br>
> > +<br>
> > + // Handle some special cases<br>
> > + switch(Inst->getOpcode()) {<br>
> > + case AMDGPU::S_MOV_B64: {<br>
> > + DebugLoc DL = Inst->getDebugLoc();<br>
> > +<br>
> > + // If the source operand is a register we can replace this with a<br>
> > + // copy<br>
> > + if (Inst->getOperand(1).isReg()) {<br>
> > + MachineInstr *Copy = BuildMI(*MBB, Inst, DL,<br>
> > + get(TargetOpcode::COPY))<br>
> > + .addOperand(Inst->getOperand(0))<br>
> > + .addOperand(Inst->getOperand(1));<br>
> > + Worklist.push_back(Copy);<br>
> > + } else {<br>
> > + // Otherwise, we need to split this into two movs, because<br>
> > there is<br>
> > + // no 64-bit VALU move instruction.<br>
> > + unsigned LoDst, HiDst, Dst;<br>
> > + LoDst = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);<br>
> > + HiDst = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);<br>
> > + Dst = MRI.createVirtualRegister(<br>
> > + MRI.getRegClass(Inst->getOperand(0).getReg()));<br>
> > +<br>
> > + MachineInstr *Lo = BuildMI(*MBB, Inst, DL,<br>
> > get(AMDGPU::S_MOV_B32),<br>
> > + LoDst)<br>
> > + .addImm(Inst->getOperand(1).getImm() &<br>
> > 0xFFFFFFFF);<br>
> > + MachineInstr *Hi = BuildMI(*MBB, Inst, DL,<br>
> > get(AMDGPU::S_MOV_B32),<br>
> > + HiDst)<br>
> > + .addImm(Inst->getOperand(1).getImm()<br>
> > >> 32);<br>
> > +<br>
> > + BuildMI(*MBB, Inst, DL, get(TargetOpcode::REG_SEQUENCE), Dst)<br>
> > + .addReg(LoDst)<br>
> > + .addImm(AMDGPU::sub0)<br>
> > + .addReg(HiDst)<br>
> > + .addImm(AMDGPU::sub1);<br>
> > +<br>
> > + MRI.replaceRegWith(Inst->getOperand(0).getReg(), Dst);<br>
> > + Worklist.push_back(Lo);<br>
> > + Worklist.push_back(Hi);<br>
> > + }<br>
> > + Inst->eraseFromParent();<br>
> > + continue;<br>
> > + }<br>
> > + }<br>
> > +<br>
> > unsigned NewOpcode = getVALUOp(*Inst);<br>
> > if (NewOpcode == AMDGPU::INSTRUCTION_LIST_END)<br>
> > continue;<br>
> ><br>
> > - MachineRegisterInfo &MRI =<br>
> > Inst->getParent()->getParent()->getRegInfo();<br>
> > -<br>
> > // Use the new VALU Opcode.<br>
> > const MCInstrDesc &NewDesc = get(NewOpcode);<br>
> > Inst->setDesc(NewDesc);<br>
> ><br>
> > Added: llvm/trunk/test/CodeGen/R600/salu-to-valu.ll<br>
> > URL:<br>
> > <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/salu-to-valu.ll?rev=204475&view=auto" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/salu-to-valu.ll?rev=204475&view=auto</a><br>
> ><br>
> > ==============================================================================<br>
> > --- llvm/trunk/test/CodeGen/R600/salu-to-valu.ll (added)<br>
> > +++ llvm/trunk/test/CodeGen/R600/salu-to-valu.ll Fri Mar 21 10:51:54 2014<br>
> > @@ -0,0 +1,42 @@<br>
> > +; RUN: llc < %s -march=r600 -mcpu=SI | FileCheck %s<br>
> > +<br>
> > +; In this test both the pointer and the offset operands to the<br>
> > +; BUFFER_LOAD instructions end up being stored in vgprs. This<br>
> > +; requires us to add the pointer and offset together, store the<br>
> > +; result in the offset operand (vaddr), and then store 0 in an<br>
> > +; sgpr register pair and use that for the pointer operand<br>
> > +; (low 64-bits of srsrc).<br>
> > +<br>
> > +; CHECK-LABEL: @mubuf<br>
> > +; Make sure we aren't using VGPRs for the source operand of S_MOV_B64<br>
> > +; CHECK-NOT: S_MOV_B64 s[{{[0-9]+:[0-9]+}}], v<br>
> > +define void @mubuf(i32 addrspace(1)* %out, i8 addrspace(1)* %in) {<br>
> > +entry:<br>
> > + %0 = call i32 @llvm.r600.read.tidig.x() #1<br>
> > + %1 = call i32 @llvm.r600.read.tidig.y() #1<br>
> > + %2 = sext i32 %0 to i64<br>
> > + %3 = sext i32 %1 to i64<br>
> > + br label %loop<br>
> > +<br>
> > +loop:<br>
> > + %4 = phi i64 [0, %entry], [%5, %loop]<br>
> > + %5 = add i64 %2, %4<br>
> > + %6 = getelementptr i8 addrspace(1)* %in, i64 %5<br>
> > + %7 = load i8 addrspace(1)* %6, align 1<br>
> > + %8 = or i64 %5, 1<br>
> > + %9 = getelementptr i8 addrspace(1)* %in, i64 %8<br>
> > + %10 = load i8 addrspace(1)* %9, align 1<br>
> > + %11 = add i8 %7, %10<br>
> > + %12 = sext i8 %11 to i32<br>
> > + store i32 %12, i32 addrspace(1)* %out<br>
> > + %13 = icmp slt i64 %5, 10<br>
> > + br i1 %13, label %loop, label %done<br>
> > +<br>
> > +done:<br>
> > + ret void<br>
> > +}<br>
> > +<br>
> > +declare i32 @llvm.r600.read.tidig.x() #1<br>
> > +declare i32 @llvm.r600.read.tidig.y() #1<br>
> > +<br>
> > +attributes #1 = { nounwind readnone }<br>
> ><br>
> ><br>
> > _______________________________________________<br>
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> > <a href="mailto:llvm-commits@cs.uiuc.edu">llvm-commits@cs.uiuc.edu</a><br>
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> ><br>
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</div></div></blockquote></div><br></div>