<p dir="ltr">A little disturbing that some of these weren't used but thanks Nuno!</p>
<div class="gmail_quote">On Mar 23, 2014 10:18 AM, "Nuno Lopes" <<a href="mailto:nunoplopes@sapo.pt">nunoplopes@sapo.pt</a>> wrote:<br type="attribution"><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">
Author: nlopes<br>
Date: Sun Mar 23 12:09:26 2014<br>
New Revision: 204560<br>
<br>
URL: <a href="http://llvm.org/viewvc/llvm-project?rev=204560&view=rev" target="_blank">http://llvm.org/viewvc/llvm-project?rev=204560&view=rev</a><br>
Log:<br>
remove a bunch of unused private methods<br>
found with a smarter version of -Wunused-member-function that I'm playwing with.<br>
Appologies in advance if I removed someone's WIP code.<br>
<br>
include/llvm/CodeGen/MachineSSAUpdater.h | 1<br>
include/llvm/IR/DebugInfo.h | 3<br>
lib/CodeGen/MachineSSAUpdater.cpp | 10 --<br>
lib/CodeGen/PostRASchedulerList.cpp | 1<br>
lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp | 10 --<br>
lib/IR/DebugInfo.cpp | 12 --<br>
lib/MC/MCAsmStreamer.cpp | 2<br>
lib/Support/YAMLParser.cpp | 39 ---------<br>
lib/TableGen/TGParser.cpp | 16 ---<br>
lib/TableGen/TGParser.h | 1<br>
lib/Target/AArch64/AArch64TargetTransformInfo.cpp | 9 --<br>
lib/Target/ARM/ARMCodeEmitter.cpp | 12 --<br>
lib/Target/ARM/ARMFastISel.cpp | 84 --------------------<br>
lib/Target/Mips/MipsCodeEmitter.cpp | 11 --<br>
lib/Target/Mips/MipsConstantIslandPass.cpp | 12 --<br>
lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp | 21 -----<br>
lib/Target/NVPTX/NVPTXISelDAGToDAG.h | 2<br>
lib/Target/PowerPC/PPCFastISel.cpp | 1<br>
lib/Transforms/Instrumentation/AddressSanitizer.cpp | 2<br>
lib/Transforms/Instrumentation/BoundsChecking.cpp | 2<br>
lib/Transforms/Instrumentation/MemorySanitizer.cpp | 1<br>
lib/Transforms/Scalar/LoopIdiomRecognize.cpp | 8 -<br>
lib/Transforms/Scalar/SCCP.cpp | 1<br>
utils/TableGen/CodeEmitterGen.cpp | 2<br>
24 files changed, 2 insertions(+), 261 deletions(-)<br>
<br>
Modified:<br>
llvm/trunk/include/llvm/CodeGen/MachineSSAUpdater.h<br>
llvm/trunk/include/llvm/IR/DebugInfo.h<br>
llvm/trunk/lib/CodeGen/MachineSSAUpdater.cpp<br>
llvm/trunk/lib/CodeGen/PostRASchedulerList.cpp<br>
llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp<br>
llvm/trunk/lib/IR/DebugInfo.cpp<br>
llvm/trunk/lib/MC/MCAsmStreamer.cpp<br>
llvm/trunk/lib/Support/YAMLParser.cpp<br>
llvm/trunk/lib/TableGen/TGParser.cpp<br>
llvm/trunk/lib/TableGen/TGParser.h<br>
llvm/trunk/lib/Target/AArch64/AArch64TargetTransformInfo.cpp<br>
llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp<br>
llvm/trunk/lib/Target/ARM/ARMFastISel.cpp<br>
llvm/trunk/lib/Target/Mips/MipsCodeEmitter.cpp<br>
llvm/trunk/lib/Target/Mips/MipsConstantIslandPass.cpp<br>
llvm/trunk/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp<br>
llvm/trunk/lib/Target/NVPTX/NVPTXISelDAGToDAG.h<br>
llvm/trunk/lib/Target/PowerPC/PPCFastISel.cpp<br>
llvm/trunk/lib/Transforms/Instrumentation/AddressSanitizer.cpp<br>
llvm/trunk/lib/Transforms/Instrumentation/BoundsChecking.cpp<br>
llvm/trunk/lib/Transforms/Instrumentation/MemorySanitizer.cpp<br>
llvm/trunk/lib/Transforms/Scalar/LoopIdiomRecognize.cpp<br>
llvm/trunk/lib/Transforms/Scalar/SCCP.cpp<br>
llvm/trunk/utils/TableGen/CodeEmitterGen.cpp<br>
<br>
Modified: llvm/trunk/include/llvm/CodeGen/MachineSSAUpdater.h<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/MachineSSAUpdater.h?rev=204560&r1=204559&r2=204560&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/MachineSSAUpdater.h?rev=204560&r1=204559&r2=204560&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/include/llvm/CodeGen/MachineSSAUpdater.h (original)<br>
+++ llvm/trunk/include/llvm/CodeGen/MachineSSAUpdater.h Sun Mar 23 12:09:26 2014<br>
@@ -105,7 +105,6 @@ public:<br>
void RewriteUse(MachineOperand &U);<br>
<br>
private:<br>
- void ReplaceRegWith(unsigned OldReg, unsigned NewReg);<br>
unsigned GetValueAtEndOfBlockInternal(MachineBasicBlock *BB);<br>
<br>
void operator=(const MachineSSAUpdater&) LLVM_DELETED_FUNCTION;<br>
<br>
Modified: llvm/trunk/include/llvm/IR/DebugInfo.h<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/IR/DebugInfo.h?rev=204560&r1=204559&r2=204560&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/IR/DebugInfo.h?rev=204560&r1=204559&r2=204560&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/include/llvm/IR/DebugInfo.h (original)<br>
+++ llvm/trunk/include/llvm/IR/DebugInfo.h Sun Mar 23 12:09:26 2014<br>
@@ -854,9 +854,6 @@ private:<br>
/// processType - Process DIType.<br>
void processType(DIType DT);<br>
<br>
- /// processLexicalBlock - Process DILexicalBlock.<br>
- void processLexicalBlock(DILexicalBlock LB);<br>
-<br>
/// processSubprogram - Process DISubprogram.<br>
void processSubprogram(DISubprogram SP);<br>
<br>
<br>
Modified: llvm/trunk/lib/CodeGen/MachineSSAUpdater.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineSSAUpdater.cpp?rev=204560&r1=204559&r2=204560&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineSSAUpdater.cpp?rev=204560&r1=204559&r2=204560&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/CodeGen/MachineSSAUpdater.cpp (original)<br>
+++ llvm/trunk/lib/CodeGen/MachineSSAUpdater.cpp Sun Mar 23 12:09:26 2014<br>
@@ -230,16 +230,6 @@ void MachineSSAUpdater::RewriteUse(Machi<br>
U.setReg(NewVR);<br>
}<br>
<br>
-void MachineSSAUpdater::ReplaceRegWith(unsigned OldReg, unsigned NewReg) {<br>
- MRI->replaceRegWith(OldReg, NewReg);<br>
-<br>
- AvailableValsTy &AvailableVals = getAvailableVals(AV);<br>
- for (DenseMap<MachineBasicBlock*, unsigned>::iterator<br>
- I = AvailableVals.begin(), E = AvailableVals.end(); I != E; ++I)<br>
- if (I->second == OldReg)<br>
- I->second = NewReg;<br>
-}<br>
-<br>
/// SSAUpdaterTraits<MachineSSAUpdater> - Traits for the SSAUpdaterImpl<br>
/// template, specialized for MachineSSAUpdater.<br>
namespace llvm {<br>
<br>
Modified: llvm/trunk/lib/CodeGen/PostRASchedulerList.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/PostRASchedulerList.cpp?rev=204560&r1=204559&r2=204560&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/PostRASchedulerList.cpp?rev=204560&r1=204559&r2=204560&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/CodeGen/PostRASchedulerList.cpp (original)<br>
+++ llvm/trunk/lib/CodeGen/PostRASchedulerList.cpp Sun Mar 23 12:09:26 2014<br>
@@ -175,7 +175,6 @@ namespace {<br>
void ReleaseSuccessors(SUnit *SU);<br>
void ScheduleNodeTopDown(SUnit *SU, unsigned CurCycle);<br>
void ListScheduleTopDown();<br>
- void StartBlockForKills(MachineBasicBlock *BB);<br>
<br>
void dumpSchedule() const;<br>
void emitNoop(unsigned CurCycle);<br>
<br>
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp?rev=204560&r1=204559&r2=204560&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp?rev=204560&r1=204559&r2=204560&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp (original)<br>
+++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp Sun Mar 23 12:09:26 2014<br>
@@ -627,16 +627,6 @@ namespace {<br>
}<br>
}<br>
<br>
- /// areValueTypesLegal - Return true if types of all the values are legal.<br>
- bool areValueTypesLegal(const TargetLowering &TLI) {<br>
- for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) {<br>
- MVT RegisterVT = RegVTs[Value];<br>
- if (!TLI.isTypeLegal(RegisterVT))<br>
- return false;<br>
- }<br>
- return true;<br>
- }<br>
-<br>
/// append - Add the specified values to this one.<br>
void append(const RegsForValue &RHS) {<br>
ValueVTs.append(RHS.ValueVTs.begin(), RHS.ValueVTs.end());<br>
<br>
Modified: llvm/trunk/lib/IR/DebugInfo.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/IR/DebugInfo.cpp?rev=204560&r1=204559&r2=204560&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/IR/DebugInfo.cpp?rev=204560&r1=204559&r2=204560&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/IR/DebugInfo.cpp (original)<br>
+++ llvm/trunk/lib/IR/DebugInfo.cpp Sun Mar 23 12:09:26 2014<br>
@@ -1087,18 +1087,6 @@ void DebugInfoFinder::processScope(DISco<br>
}<br>
}<br>
<br>
-/// processLexicalBlock<br>
-void DebugInfoFinder::processLexicalBlock(DILexicalBlock LB) {<br>
- DIScope Context = LB.getContext();<br>
- if (Context.isLexicalBlock())<br>
- return processLexicalBlock(DILexicalBlock(Context));<br>
- else if (Context.isLexicalBlockFile()) {<br>
- DILexicalBlockFile DBF = DILexicalBlockFile(Context);<br>
- return processLexicalBlock(DILexicalBlock(DBF.getScope()));<br>
- } else<br>
- return processSubprogram(DISubprogram(Context));<br>
-}<br>
-<br>
/// processSubprogram - Process DISubprogram.<br>
void DebugInfoFinder::processSubprogram(DISubprogram SP) {<br>
if (!addSubprogram(SP))<br>
<br>
Modified: llvm/trunk/lib/MC/MCAsmStreamer.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCAsmStreamer.cpp?rev=204560&r1=204559&r2=204560&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCAsmStreamer.cpp?rev=204560&r1=204559&r2=204560&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/MC/MCAsmStreamer.cpp (original)<br>
+++ llvm/trunk/lib/MC/MCAsmStreamer.cpp Sun Mar 23 12:09:26 2014<br>
@@ -59,8 +59,6 @@ private:<br>
<br>
DenseMap<const MCSymbol*, MCSymbolData*> SymbolMap;<br>
<br>
- bool needsSet(const MCExpr *Value);<br>
-<br>
void EmitRegisterName(int64_t Register);<br>
void EmitCFIStartProcImpl(MCDwarfFrameInfo &Frame) override;<br>
void EmitCFIEndProcImpl(MCDwarfFrameInfo &Frame) override;<br>
<br>
Modified: llvm/trunk/lib/Support/YAMLParser.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Support/YAMLParser.cpp?rev=204560&r1=204559&r2=204560&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Support/YAMLParser.cpp?rev=204560&r1=204559&r2=204560&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Support/YAMLParser.cpp (original)<br>
+++ llvm/trunk/lib/Support/YAMLParser.cpp Sun Mar 23 12:09:26 2014<br>
@@ -378,9 +378,6 @@ private:<br>
/// sequence of ns-uri-char.<br>
StringRef scan_ns_uri_char();<br>
<br>
- /// @brief Scan ns-plain-one-line[133] starting at \a Cur.<br>
- StringRef scan_ns_plain_one_line();<br>
-<br>
/// @brief Consume a minimal well-formed code unit subsequence starting at<br>
/// \a Cur. Return false if it is not the same Unicode scalar value as<br>
/// \a Expected. This updates \a Column.<br>
@@ -873,42 +870,6 @@ StringRef Scanner::scan_ns_uri_char() {<br>
return StringRef(Start, Current - Start);<br>
}<br>
<br>
-StringRef Scanner::scan_ns_plain_one_line() {<br>
- StringRef::iterator start = Current;<br>
- // The first character must already be verified.<br>
- ++Current;<br>
- while (true) {<br>
- if (Current == End) {<br>
- break;<br>
- } else if (*Current == ':') {<br>
- // Check if the next character is a ns-char.<br>
- if (Current + 1 == End)<br>
- break;<br>
- StringRef::iterator i = skip_ns_char(Current + 1);<br>
- if (Current + 1 != i) {<br>
- Current = i;<br>
- Column += 2; // Consume both the ':' and ns-char.<br>
- } else<br>
- break;<br>
- } else if (*Current == '#') {<br>
- // Check if the previous character was a ns-char.<br>
- // The & 0x80 check is to check for the trailing byte of a utf-8<br>
- if (*(Current - 1) & 0x80 || skip_ns_char(Current - 1) == Current) {<br>
- ++Current;<br>
- ++Column;<br>
- } else<br>
- break;<br>
- } else {<br>
- StringRef::iterator i = skip_nb_char(Current);<br>
- if (i == Current)<br>
- break;<br>
- Current = i;<br>
- ++Column;<br>
- }<br>
- }<br>
- return StringRef(start, Current - start);<br>
-}<br>
-<br>
bool Scanner::consume(uint32_t Expected) {<br>
if (Expected >= 0x80)<br>
report_fatal_error("Not dealing with this yet");<br>
<br>
Modified: llvm/trunk/lib/TableGen/TGParser.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/TableGen/TGParser.cpp?rev=204560&r1=204559&r2=204560&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/TableGen/TGParser.cpp?rev=204560&r1=204559&r2=204560&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/TableGen/TGParser.cpp (original)<br>
+++ llvm/trunk/lib/TableGen/TGParser.cpp Sun Mar 23 12:09:26 2014<br>
@@ -722,22 +722,6 @@ RecTy *TGParser::ParseType() {<br>
}<br>
}<br>
<br>
-/// ParseIDValue - Parse an ID as a value and decode what it means.<br>
-///<br>
-/// IDValue ::= ID [def local value]<br>
-/// IDValue ::= ID [def template arg]<br>
-/// IDValue ::= ID [multiclass local value]<br>
-/// IDValue ::= ID [multiclass template argument]<br>
-/// IDValue ::= ID [def name]<br>
-///<br>
-Init *TGParser::ParseIDValue(Record *CurRec, IDParseMode Mode) {<br>
- assert(Lex.getCode() == tgtok::Id && "Expected ID in ParseIDValue");<br>
- std::string Name = Lex.getCurStrVal();<br>
- SMLoc Loc = Lex.getLoc();<br>
- Lex.Lex();<br>
- return ParseIDValue(CurRec, Name, Loc);<br>
-}<br>
-<br>
/// ParseIDValue - This is just like ParseIDValue above, but it assumes the ID<br>
/// has already been read.<br>
Init *TGParser::ParseIDValue(Record *CurRec,<br>
<br>
Modified: llvm/trunk/lib/TableGen/TGParser.h<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/TableGen/TGParser.h?rev=204560&r1=204559&r2=204560&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/TableGen/TGParser.h?rev=204560&r1=204559&r2=204560&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/TableGen/TGParser.h (original)<br>
+++ llvm/trunk/lib/TableGen/TGParser.h Sun Mar 23 12:09:26 2014<br>
@@ -167,7 +167,6 @@ private: // Parser methods.<br>
SubClassReference ParseSubClassReference(Record *CurRec, bool isDefm);<br>
SubMultiClassReference ParseSubMultiClassReference(MultiClass *CurMC);<br>
<br>
- Init *ParseIDValue(Record *CurRec, IDParseMode Mode = ParseValueMode);<br>
Init *ParseIDValue(Record *CurRec, const std::string &Name, SMLoc NameLoc,<br>
IDParseMode Mode = ParseValueMode);<br>
Init *ParseSimpleValue(Record *CurRec, RecTy *ItemType = 0,<br>
<br>
Modified: llvm/trunk/lib/Target/AArch64/AArch64TargetTransformInfo.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64TargetTransformInfo.cpp?rev=204560&r1=204559&r2=204560&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64TargetTransformInfo.cpp?rev=204560&r1=204559&r2=204560&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/AArch64/AArch64TargetTransformInfo.cpp (original)<br>
+++ llvm/trunk/lib/Target/AArch64/AArch64TargetTransformInfo.cpp Sun Mar 23 12:09:26 2014<br>
@@ -33,21 +33,16 @@ void initializeAArch64TTIPass(PassRegist<br>
namespace {<br>
<br>
class AArch64TTI final : public ImmutablePass, public TargetTransformInfo {<br>
- const AArch64TargetMachine *TM;<br>
const AArch64Subtarget *ST;<br>
const AArch64TargetLowering *TLI;<br>
<br>
- /// Estimate the overhead of scalarizing an instruction. Insert and Extract<br>
- /// are set if the result needs to be inserted and/or extracted from vectors.<br>
- unsigned getScalarizationOverhead(Type *Ty, bool Insert, bool Extract) const;<br>
-<br>
public:<br>
- AArch64TTI() : ImmutablePass(ID), TM(0), ST(0), TLI(0) {<br>
+ AArch64TTI() : ImmutablePass(ID), ST(0), TLI(0) {<br>
llvm_unreachable("This pass cannot be directly constructed");<br>
}<br>
<br>
AArch64TTI(const AArch64TargetMachine *TM)<br>
- : ImmutablePass(ID), TM(TM), ST(TM->getSubtargetImpl()),<br>
+ : ImmutablePass(ID), ST(TM->getSubtargetImpl()),<br>
TLI(TM->getTargetLowering()) {<br>
initializeAArch64TTIPass(*PassRegistry::getPassRegistry());<br>
}<br>
<br>
Modified: llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp?rev=204560&r1=204559&r2=204560&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp?rev=204560&r1=204559&r2=204560&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp (original)<br>
+++ llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp Sun Mar 23 12:09:26 2014<br>
@@ -207,8 +207,6 @@ namespace {<br>
const { return 0; }<br>
unsigned getThumbAddrModeRegRegOpValue(const MachineInstr &MI, unsigned Op)<br>
const { return 0; }<br>
- unsigned getT2AddrModeImm12OpValue(const MachineInstr &MI, unsigned Op)<br>
- const { return 0; }<br>
unsigned getT2AddrModeImm8OpValue(const MachineInstr &MI, unsigned Op)<br>
const { return 0; }<br>
unsigned getT2Imm8s4OpValue(const MachineInstr &MI, unsigned Op)<br>
@@ -219,8 +217,6 @@ namespace {<br>
const { return 0; }<br>
unsigned getT2AddrModeImm8OffsetOpValue(const MachineInstr &MI, unsigned Op)<br>
const { return 0; }<br>
- unsigned getT2AddrModeImm12OffsetOpValue(const MachineInstr &MI,unsigned Op)<br>
- const { return 0; }<br>
unsigned getT2AddrModeSORegOpValue(const MachineInstr &MI, unsigned Op)<br>
const { return 0; }<br>
unsigned getT2SORegOpValue(const MachineInstr &MI, unsigned Op)<br>
@@ -238,10 +234,6 @@ namespace {<br>
const { return 0; }<br>
unsigned getBitfieldInvertedMaskOpValue(const MachineInstr &MI,<br>
unsigned Op) const { return 0; }<br>
- unsigned getSsatBitPosValue(const MachineInstr &MI,<br>
- unsigned Op) const { return 0; }<br>
- uint32_t getLdStmModeOpValue(const MachineInstr &MI, unsigned OpIdx)<br>
- const {return 0; }<br>
uint32_t getLdStSORegOpValue(const MachineInstr &MI, unsigned OpIdx)<br>
const { return 0; }<br>
<br>
@@ -270,8 +262,6 @@ namespace {<br>
return 0;<br>
}<br>
<br>
- uint32_t getAddrMode2OpValue(const MachineInstr &MI, unsigned OpIdx)<br>
- const { return 0;}<br>
uint32_t getAddrMode2OffsetOpValue(const MachineInstr &MI, unsigned OpIdx)<br>
const { return 0;}<br>
uint32_t getPostIdxRegOpValue(const MachineInstr &MI, unsigned OpIdx)<br>
@@ -282,8 +272,6 @@ namespace {<br>
const { return 0; }<br>
uint32_t getAddrModeThumbSPOpValue(const MachineInstr &MI, unsigned Op)<br>
const { return 0; }<br>
- uint32_t getAddrModeSOpValue(const MachineInstr &MI, unsigned Op)<br>
- const { return 0; }<br>
uint32_t getAddrModeISOpValue(const MachineInstr &MI, unsigned Op)<br>
const { return 0; }<br>
uint32_t getAddrModePCOpValue(const MachineInstr &MI, unsigned Op)<br>
<br>
Modified: llvm/trunk/lib/Target/ARM/ARMFastISel.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMFastISel.cpp?rev=204560&r1=204559&r2=204560&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMFastISel.cpp?rev=204560&r1=204559&r2=204560&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/ARM/ARMFastISel.cpp (original)<br>
+++ llvm/trunk/lib/Target/ARM/ARMFastISel.cpp Sun Mar 23 12:09:26 2014<br>
@@ -105,8 +105,6 @@ class ARMFastISel final : public FastISe<br>
<br>
// Code from FastISel.cpp.<br>
private:<br>
- unsigned FastEmitInst_(unsigned MachineInstOpcode,<br>
- const TargetRegisterClass *RC);<br>
unsigned FastEmitInst_r(unsigned MachineInstOpcode,<br>
const TargetRegisterClass *RC,<br>
unsigned Op0, bool Op0IsKill);<br>
@@ -123,10 +121,6 @@ class ARMFastISel final : public FastISe<br>
const TargetRegisterClass *RC,<br>
unsigned Op0, bool Op0IsKill,<br>
uint64_t Imm);<br>
- unsigned FastEmitInst_rf(unsigned MachineInstOpcode,<br>
- const TargetRegisterClass *RC,<br>
- unsigned Op0, bool Op0IsKill,<br>
- const ConstantFP *FPImm);<br>
unsigned FastEmitInst_rri(unsigned MachineInstOpcode,<br>
const TargetRegisterClass *RC,<br>
unsigned Op0, bool Op0IsKill,<br>
@@ -135,13 +129,6 @@ class ARMFastISel final : public FastISe<br>
unsigned FastEmitInst_i(unsigned MachineInstOpcode,<br>
const TargetRegisterClass *RC,<br>
uint64_t Imm);<br>
- unsigned FastEmitInst_ii(unsigned MachineInstOpcode,<br>
- const TargetRegisterClass *RC,<br>
- uint64_t Imm1, uint64_t Imm2);<br>
-<br>
- unsigned FastEmitInst_extractsubreg(MVT RetVT,<br>
- unsigned Op0, bool Op0IsKill,<br>
- uint32_t Idx);<br>
<br>
// Backend specific FastISel code.<br>
private:<br>
@@ -313,16 +300,6 @@ unsigned ARMFastISel::constrainOperandRe<br>
return Op;<br>
}<br>
<br>
-unsigned ARMFastISel::FastEmitInst_(unsigned MachineInstOpcode,<br>
- const TargetRegisterClass* RC) {<br>
- unsigned ResultReg = createResultReg(RC);<br>
- const MCInstrDesc &II = TII.get(MachineInstOpcode);<br>
-<br>
- AddOptionalDefs(<br>
- BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg));<br>
- return ResultReg;<br>
-}<br>
-<br>
unsigned ARMFastISel::FastEmitInst_r(unsigned MachineInstOpcode,<br>
const TargetRegisterClass *RC,<br>
unsigned Op0, bool Op0IsKill) {<br>
@@ -431,32 +408,6 @@ unsigned ARMFastISel::FastEmitInst_ri(un<br>
return ResultReg;<br>
}<br>
<br>
-unsigned ARMFastISel::FastEmitInst_rf(unsigned MachineInstOpcode,<br>
- const TargetRegisterClass *RC,<br>
- unsigned Op0, bool Op0IsKill,<br>
- const ConstantFP *FPImm) {<br>
- unsigned ResultReg = createResultReg(RC);<br>
- const MCInstrDesc &II = TII.get(MachineInstOpcode);<br>
-<br>
- // Make sure the input operand is sufficiently constrained to be legal<br>
- // for this instruction.<br>
- Op0 = constrainOperandRegClass(II, Op0, 1);<br>
- if (II.getNumDefs() >= 1) {<br>
- AddOptionalDefs(<br>
- BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)<br>
- .addReg(Op0, Op0IsKill * RegState::Kill)<br>
- .addFPImm(FPImm));<br>
- } else {<br>
- AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II)<br>
- .addReg(Op0, Op0IsKill * RegState::Kill)<br>
- .addFPImm(FPImm));<br>
- AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,<br>
- TII.get(TargetOpcode::COPY), ResultReg)<br>
- .addReg(II.ImplicitDefs[0]));<br>
- }<br>
- return ResultReg;<br>
-}<br>
-<br>
unsigned ARMFastISel::FastEmitInst_rri(unsigned MachineInstOpcode,<br>
const TargetRegisterClass *RC,<br>
unsigned Op0, bool Op0IsKill,<br>
@@ -506,41 +457,6 @@ unsigned ARMFastISel::FastEmitInst_i(uns<br>
return ResultReg;<br>
}<br>
<br>
-unsigned ARMFastISel::FastEmitInst_ii(unsigned MachineInstOpcode,<br>
- const TargetRegisterClass *RC,<br>
- uint64_t Imm1, uint64_t Imm2) {<br>
- unsigned ResultReg = createResultReg(RC);<br>
- const MCInstrDesc &II = TII.get(MachineInstOpcode);<br>
-<br>
- if (II.getNumDefs() >= 1) {<br>
- AddOptionalDefs(<br>
- BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)<br>
- .addImm(Imm1)<br>
- .addImm(Imm2));<br>
- } else {<br>
- AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II)<br>
- .addImm(Imm1).addImm(Imm2));<br>
- AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,<br>
- TII.get(TargetOpcode::COPY),<br>
- ResultReg)<br>
- .addReg(II.ImplicitDefs[0]));<br>
- }<br>
- return ResultReg;<br>
-}<br>
-<br>
-unsigned ARMFastISel::FastEmitInst_extractsubreg(MVT RetVT,<br>
- unsigned Op0, bool Op0IsKill,<br>
- uint32_t Idx) {<br>
- unsigned ResultReg = createResultReg(TLI.getRegClassFor(RetVT));<br>
- assert(TargetRegisterInfo::isVirtualRegister(Op0) &&<br>
- "Cannot yet extract from physregs");<br>
-<br>
- AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt,<br>
- DbgLoc, TII.get(TargetOpcode::COPY), ResultReg)<br>
- .addReg(Op0, getKillRegState(Op0IsKill), Idx));<br>
- return ResultReg;<br>
-}<br>
-<br>
// TODO: Don't worry about 64-bit now, but when this is fixed remove the<br>
// checks from the various callers.<br>
unsigned ARMFastISel::ARMMoveToFPReg(MVT VT, unsigned SrcReg) {<br>
<br>
Modified: llvm/trunk/lib/Target/Mips/MipsCodeEmitter.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsCodeEmitter.cpp?rev=204560&r1=204559&r2=204560&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsCodeEmitter.cpp?rev=204560&r1=204559&r2=204560&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/Mips/MipsCodeEmitter.cpp (original)<br>
+++ llvm/trunk/lib/Target/Mips/MipsCodeEmitter.cpp Sun Mar 23 12:09:26 2014<br>
@@ -117,9 +117,6 @@ private:<br>
unsigned getSizeInsEncoding(const MachineInstr &MI, unsigned OpNo) const;<br>
unsigned getLSAImmEncoding(const MachineInstr &MI, unsigned OpNo) const;<br>
<br>
- void emitGlobalAddressUnaligned(const GlobalValue *GV, unsigned Reloc,<br>
- int Offset) const;<br>
-<br>
/// Expand pseudo instructions with accumulator register operands.<br>
void expandACCInstr(MachineBasicBlock::instr_iterator MI,<br>
MachineBasicBlock &MBB, unsigned Opc) const;<br>
@@ -280,14 +277,6 @@ void MipsCodeEmitter::emitGlobalAddress(<br>
MayNeedFarStub));<br>
}<br>
<br>
-void MipsCodeEmitter::emitGlobalAddressUnaligned(const GlobalValue *GV,<br>
- unsigned Reloc, int Offset) const {<br>
- MCE.addRelocation(MachineRelocation::getGV(MCE.getCurrentPCOffset(), Reloc,<br>
- const_cast<GlobalValue *>(GV), 0, false));<br>
- MCE.addRelocation(MachineRelocation::getGV(MCE.getCurrentPCOffset() + Offset,<br>
- Reloc, const_cast<GlobalValue *>(GV), 0, false));<br>
-}<br>
-<br>
void MipsCodeEmitter::<br>
emitExternalSymbolAddress(const char *ES, unsigned Reloc) const {<br>
MCE.addRelocation(MachineRelocation::getExtSym(MCE.getCurrentPCOffset(),<br>
<br>
Modified: llvm/trunk/lib/Target/Mips/MipsConstantIslandPass.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsConstantIslandPass.cpp?rev=204560&r1=204559&r2=204560&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsConstantIslandPass.cpp?rev=204560&r1=204559&r2=204560&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/Mips/MipsConstantIslandPass.cpp (original)<br>
+++ llvm/trunk/lib/Target/Mips/MipsConstantIslandPass.cpp Sun Mar 23 12:09:26 2014<br>
@@ -384,16 +384,12 @@ namespace {<br>
unsigned getOffsetOf(MachineInstr *MI) const;<br>
unsigned getUserOffset(CPUser&) const;<br>
void dumpBBs();<br>
- void verify();<br>
<br>
bool isOffsetInRange(unsigned UserOffset, unsigned TrialOffset,<br>
unsigned Disp, bool NegativeOK);<br>
bool isOffsetInRange(unsigned UserOffset, unsigned TrialOffset,<br>
const CPUser &U);<br>
<br>
- bool isLongFormOffsetInRange(unsigned UserOffset, unsigned TrialOffset,<br>
- const CPUser &U);<br>
-<br>
void computeBlockSize(MachineBasicBlock *MBB);<br>
MachineBasicBlock *splitBlockBeforeInstr(MachineInstr *MI);<br>
void updateForInsertedWaterBlock(MachineBasicBlock *NewBB);<br>
@@ -427,14 +423,6 @@ namespace {<br>
char MipsConstantIslands::ID = 0;<br>
} // end of anonymous namespace<br>
<br>
-<br>
-bool MipsConstantIslands::isLongFormOffsetInRange<br>
- (unsigned UserOffset, unsigned TrialOffset,<br>
- const CPUser &U) {<br>
- return isOffsetInRange(UserOffset, TrialOffset,<br>
- U.getLongFormMaxDisp(), U.NegOk);<br>
-}<br>
-<br>
bool MipsConstantIslands::isOffsetInRange<br>
(unsigned UserOffset, unsigned TrialOffset,<br>
const CPUser &U) {<br>
<br>
Modified: llvm/trunk/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp?rev=204560&r1=204559&r2=204560&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp?rev=204560&r1=204559&r2=204560&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp (original)<br>
+++ llvm/trunk/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp Sun Mar 23 12:09:26 2014<br>
@@ -2440,24 +2440,3 @@ bool NVPTXDAGToDAGISel::SelectInlineAsmM<br>
}<br>
return true;<br>
}<br>
-<br>
-// Return true if N is a undef or a constant.<br>
-// If N was undef, return a (i8imm 0) in Retval<br>
-// If N was imm, convert it to i8imm and return in Retval<br>
-// Note: The convert to i8imm is required, otherwise the<br>
-// pattern matcher inserts a bunch of IMOVi8rr to convert<br>
-// the imm to i8imm, and this causes instruction selection<br>
-// to fail.<br>
-bool NVPTXDAGToDAGISel::UndefOrImm(SDValue Op, SDValue N, SDValue &Retval) {<br>
- if (!(N.getOpcode() == ISD::UNDEF) && !(N.getOpcode() == ISD::Constant))<br>
- return false;<br>
-<br>
- if (N.getOpcode() == ISD::UNDEF)<br>
- Retval = CurDAG->getTargetConstant(0, MVT::i8);<br>
- else {<br>
- ConstantSDNode *cn = cast<ConstantSDNode>(N.getNode());<br>
- unsigned retval = cn->getZExtValue();<br>
- Retval = CurDAG->getTargetConstant(retval, MVT::i8);<br>
- }<br>
- return true;<br>
-}<br>
<br>
Modified: llvm/trunk/lib/Target/NVPTX/NVPTXISelDAGToDAG.h<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/NVPTX/NVPTXISelDAGToDAG.h?rev=204560&r1=204559&r2=204560&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/NVPTX/NVPTXISelDAGToDAG.h?rev=204560&r1=204559&r2=204560&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/NVPTX/NVPTXISelDAGToDAG.h (original)<br>
+++ llvm/trunk/lib/Target/NVPTX/NVPTXISelDAGToDAG.h Sun Mar 23 12:09:26 2014<br>
@@ -91,7 +91,5 @@ private:<br>
<br>
bool ChkMemSDNodeAddressSpace(SDNode *N, unsigned int spN) const;<br>
<br>
- bool UndefOrImm(SDValue Op, SDValue N, SDValue &Retval);<br>
-<br>
};<br>
}<br>
<br>
Modified: llvm/trunk/lib/Target/PowerPC/PPCFastISel.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCFastISel.cpp?rev=204560&r1=204559&r2=204560&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCFastISel.cpp?rev=204560&r1=204559&r2=204560&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/PowerPC/PPCFastISel.cpp (original)<br>
+++ llvm/trunk/lib/Target/PowerPC/PPCFastISel.cpp Sun Mar 23 12:09:26 2014<br>
@@ -127,7 +127,6 @@ class PPCFastISel final : public FastISe<br>
bool SelectStore(const Instruction *I);<br>
bool SelectBranch(const Instruction *I);<br>
bool SelectIndirectBr(const Instruction *I);<br>
- bool SelectCmp(const Instruction *I);<br>
bool SelectFPExt(const Instruction *I);<br>
bool SelectFPTrunc(const Instruction *I);<br>
bool SelectIToFP(const Instruction *I, bool IsSigned);<br>
<br>
Modified: llvm/trunk/lib/Transforms/Instrumentation/AddressSanitizer.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Instrumentation/AddressSanitizer.cpp?rev=204560&r1=204559&r2=204560&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Instrumentation/AddressSanitizer.cpp?rev=204560&r1=204559&r2=204560&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Transforms/Instrumentation/AddressSanitizer.cpp (original)<br>
+++ llvm/trunk/lib/Transforms/Instrumentation/AddressSanitizer.cpp Sun Mar 23 12:09:26 2014<br>
@@ -326,9 +326,7 @@ struct AddressSanitizer : public Functio<br>
private:<br>
void initializeCallbacks(Module &M);<br>
<br>
- bool ShouldInstrumentGlobal(GlobalVariable *G);<br>
bool LooksLikeCodeInBug11395(Instruction *I);<br>
- void FindDynamicInitializers(Module &M);<br>
bool GlobalIsLinkerInitialized(GlobalVariable *G);<br>
bool InjectCoverage(Function &F, const ArrayRef<BasicBlock*> AllBlocks);<br>
void InjectCoverageAtBlock(Function &F, BasicBlock &BB);<br>
<br>
Modified: llvm/trunk/lib/Transforms/Instrumentation/BoundsChecking.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Instrumentation/BoundsChecking.cpp?rev=204560&r1=204559&r2=204560&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Instrumentation/BoundsChecking.cpp?rev=204560&r1=204559&r2=204560&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Transforms/Instrumentation/BoundsChecking.cpp (original)<br>
+++ llvm/trunk/lib/Transforms/Instrumentation/BoundsChecking.cpp Sun Mar 23 12:09:26 2014<br>
@@ -62,8 +62,6 @@ namespace {<br>
<br>
BasicBlock *getTrapBB();<br>
void emitBranchToTrap(Value *Cmp = 0);<br>
- bool computeAllocSize(Value *Ptr, APInt &Offset, Value* &OffsetValue,<br>
- APInt &Size, Value* &SizeValue);<br>
bool instrument(Value *Ptr, Value *Val);<br>
};<br>
}<br>
<br>
Modified: llvm/trunk/lib/Transforms/Instrumentation/MemorySanitizer.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Instrumentation/MemorySanitizer.cpp?rev=204560&r1=204559&r2=204560&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Instrumentation/MemorySanitizer.cpp?rev=204560&r1=204559&r2=204560&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Transforms/Instrumentation/MemorySanitizer.cpp (original)<br>
+++ llvm/trunk/lib/Transforms/Instrumentation/MemorySanitizer.cpp Sun Mar 23 12:09:26 2014<br>
@@ -501,7 +501,6 @@ struct MemorySanitizerVisitor : public I<br>
Instruction *OrigIns;<br>
ShadowOriginAndInsertPoint(Value *S, Value *O, Instruction *I)<br>
: Shadow(S), Origin(O), OrigIns(I) { }<br>
- ShadowOriginAndInsertPoint() : Shadow(0), Origin(0), OrigIns(0) { }<br>
};<br>
SmallVector<ShadowOriginAndInsertPoint, 16> InstrumentationList;<br>
SmallVector<Instruction*, 16> StoreList;<br>
<br>
Modified: llvm/trunk/lib/Transforms/Scalar/LoopIdiomRecognize.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/LoopIdiomRecognize.cpp?rev=204560&r1=204559&r2=204560&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/LoopIdiomRecognize.cpp?rev=204560&r1=204559&r2=204560&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Transforms/Scalar/LoopIdiomRecognize.cpp (original)<br>
+++ llvm/trunk/lib/Transforms/Scalar/LoopIdiomRecognize.cpp Sun Mar 23 12:09:26 2014<br>
@@ -79,9 +79,6 @@ namespace {<br>
return dyn_cast<BranchInst>(BB->getTerminator());<br>
}<br>
<br>
- /// Return the condition of the branch terminating the given basic block.<br>
- static Value *getBrCondtion(BasicBlock *);<br>
-<br>
/// Derive the precondition block (i.e the block that guards the loop<br>
/// preheader) from the given preheader.<br>
static BasicBlock *getPrecondBb(BasicBlock *PreHead);<br>
@@ -292,11 +289,6 @@ bool LIRUtil::isAlmostEmpty(BasicBlock *<br>
return false;<br>
}<br>
<br>
-Value *LIRUtil::getBrCondtion(BasicBlock *BB) {<br>
- BranchInst *Br = getBranch(BB);<br>
- return Br ? Br->getCondition() : 0;<br>
-}<br>
-<br>
BasicBlock *LIRUtil::getPrecondBb(BasicBlock *PreHead) {<br>
if (BasicBlock *BB = PreHead->getSinglePredecessor()) {<br>
BranchInst *Br = getBranch(BB);<br>
<br>
Modified: llvm/trunk/lib/Transforms/Scalar/SCCP.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/SCCP.cpp?rev=204560&r1=204559&r2=204560&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/SCCP.cpp?rev=204560&r1=204559&r2=204560&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Transforms/Scalar/SCCP.cpp (original)<br>
+++ llvm/trunk/lib/Transforms/Scalar/SCCP.cpp Sun Mar 23 12:09:26 2014<br>
@@ -491,7 +491,6 @@ private:<br>
}<br>
void visitCallSite (CallSite CS);<br>
void visitResumeInst (TerminatorInst &I) { /*returns void*/ }<br>
- void visitUnwindInst (TerminatorInst &I) { /*returns void*/ }<br>
void visitUnreachableInst(TerminatorInst &I) { /*returns void*/ }<br>
void visitFenceInst (FenceInst &I) { /*returns void*/ }<br>
void visitAtomicCmpXchgInst (AtomicCmpXchgInst &I) { markOverdefined(&I); }<br>
<br>
Modified: llvm/trunk/utils/TableGen/CodeEmitterGen.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/CodeEmitterGen.cpp?rev=204560&r1=204559&r2=204560&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/CodeEmitterGen.cpp?rev=204560&r1=204559&r2=204560&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/utils/TableGen/CodeEmitterGen.cpp (original)<br>
+++ llvm/trunk/utils/TableGen/CodeEmitterGen.cpp Sun Mar 23 12:09:26 2014<br>
@@ -41,8 +41,6 @@ public:<br>
<br>
void run(raw_ostream &o);<br>
private:<br>
- void emitMachineOpEmitter(raw_ostream &o, const std::string &Namespace);<br>
- void emitGetValueBit(raw_ostream &o, const std::string &Namespace);<br>
int getVariableBit(const std::string &VarName, BitsInit *BI, int bit);<br>
std::string getInstructionCase(Record *R, CodeGenTarget &Target);<br>
void AddCodeToMergeInOperand(Record *R, BitsInit *BI,<br>
<br>
<br>
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</blockquote></div>