<html><head><meta http-equiv="Content-Type" content="text/html charset=windows-1252"></head><body style="word-wrap: break-word; -webkit-nbsp-mode: space; -webkit-line-break: after-white-space;">Hi Eric,<div><br></div><div>I did not expect any performance changes and honestly, I haven’t measured.</div><div>This patch was more a “hey, we are missing obvious scheduling resources here!”</div><div><br></div><div>I hope that’s fine.</div><div><br></div><div>Thanks,</div><div><div apple-content-edited="true">
<div style="color: rgb(0, 0, 0); font-family: Helvetica; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; orphans: 2; text-align: -webkit-auto; text-indent: 0px; text-transform: none; white-space: normal; widows: 2; word-spacing: 0px; -webkit-text-size-adjust: auto; -webkit-text-stroke-width: 0px; word-wrap: break-word; -webkit-nbsp-mode: space; -webkit-line-break: after-white-space; ">-Quentin</div>
</div>
<br><div><div>On Mar 12, 2014, at 1:50 PM, Eric Christopher <<a href="mailto:echristo@gmail.com">echristo@gmail.com</a>> wrote:</div><br class="Apple-interchange-newline"><blockquote type="cite">Any performance changes? :)<br><br>-eric<br><br>On Wed, Mar 12, 2014 at 10:33 AM, Quentin Colombet <<a href="mailto:qcolombet@apple.com">qcolombet@apple.com</a>> wrote:<br><blockquote type="cite">Author: qcolombet<br>Date: Wed Mar 12 12:33:42 2014<br>New Revision: 203682<br><br>URL: <a href="http://llvm.org/viewvc/llvm-project?rev=203682&view=rev">http://llvm.org/viewvc/llvm-project?rev=203682&view=rev</a><br>Log:<br>[X86] Set the scheduling resources of some of the FPStack instructions.<br>This is related to <<a href="rdar://problem/15607571">rdar://problem/15607571</a>>.<br><br>Modified:<br> llvm/trunk/lib/Target/X86/X86InstrFPStack.td<br><br>Modified: llvm/trunk/lib/Target/X86/X86InstrFPStack.td<br>URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrFPStack.td?rev=203682&r1=203681&r2=203682&view=diff">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrFPStack.td?rev=203682&r1=203681&r2=203682&view=diff</a><br>==============================================================================<br>--- llvm/trunk/lib/Target/X86/X86InstrFPStack.td (original)<br>+++ llvm/trunk/lib/Target/X86/X86InstrFPStack.td Wed Mar 12 12:33:42 2014<br>@@ -206,17 +206,26 @@ def _FI32m : FPI<0xDA, fp, (outs), (ins<br> }<br><br> let Defs = [FPSW] in {<br>+// FPBinary_rr just defines pseudo-instructions, no need to set a scheduling<br>+// resources.<br> defm ADD : FPBinary_rr<fadd>;<br> defm SUB : FPBinary_rr<fsub>;<br> defm MUL : FPBinary_rr<fmul>;<br> defm DIV : FPBinary_rr<fdiv>;<br>+// Sets the scheduling resources for the actual NAME#_F<size>m defintions.<br>+let SchedRW = [WriteFAddLd] in {<br> defm ADD : FPBinary<fadd, MRM0m, "add">;<br> defm SUB : FPBinary<fsub, MRM4m, "sub">;<br> defm SUBR: FPBinary<fsub ,MRM5m, "subr">;<br>+}<br>+let SchedRW = [WriteFMulLd] in {<br> defm MUL : FPBinary<fmul, MRM1m, "mul">;<br>+}<br>+let SchedRW = [WriteFDivLd] in {<br> defm DIV : FPBinary<fdiv, MRM6m, "div">;<br> defm DIVR: FPBinary<fdiv, MRM7m, "divr">;<br> }<br>+}<br><br> class FPST0rInst<Format fp, string asm><br> : FPI<0xD8, fp, (outs), (ins RST:$op), asm>;<br>@@ -228,6 +237,7 @@ class FPrST0PInst<Format fp, string asm><br> // NOTE: GAS and apparently all other AT&T style assemblers have a broken notion<br> // of some of the 'reverse' forms of the fsub and fdiv instructions. As such,<br> // we have to put some 'r's in and take them out of weird places.<br>+let SchedRW = [WriteFAdd] in {<br> def ADD_FST0r : FPST0rInst <MRM0r, "fadd\t$op">;<br> def ADD_FrST0 : FPrST0Inst <MRM0r, "fadd\t{%st(0), $op|$op, st(0)}">;<br> def ADD_FPrST0 : FPrST0PInst<MRM0r, "faddp\t$op">;<br>@@ -237,15 +247,20 @@ def SUB_FPrST0 : FPrST0PInst<MRM5r, "fs<br> def SUB_FST0r : FPST0rInst <MRM4r, "fsub\t$op">;<br> def SUBR_FrST0 : FPrST0Inst <MRM4r, "fsub{|r}\t{%st(0), $op|$op, st(0)}">;<br> def SUBR_FPrST0 : FPrST0PInst<MRM4r, "fsub{|r}p\t$op">;<br>+} // SchedRW<br>+let SchedRW = [WriteFMul] in {<br> def MUL_FST0r : FPST0rInst <MRM1r, "fmul\t$op">;<br> def MUL_FrST0 : FPrST0Inst <MRM1r, "fmul\t{%st(0), $op|$op, st(0)}">;<br> def MUL_FPrST0 : FPrST0PInst<MRM1r, "fmulp\t$op">;<br>+} // SchedRW<br>+let SchedRW = [WriteFDiv] in {<br> def DIVR_FST0r : FPST0rInst <MRM7r, "fdivr\t$op">;<br> def DIV_FrST0 : FPrST0Inst <MRM7r, "fdiv{r}\t{%st(0), $op|$op, st(0)}">;<br> def DIV_FPrST0 : FPrST0PInst<MRM7r, "fdiv{r}p\t$op">;<br> def DIV_FST0r : FPST0rInst <MRM6r, "fdiv\t$op">;<br> def DIVR_FrST0 : FPrST0Inst <MRM6r, "fdiv{|r}\t{%st(0), $op|$op, st(0)}">;<br> def DIVR_FPrST0 : FPrST0PInst<MRM6r, "fdiv{|r}p\t$op">;<br>+} // SchedRW<br><br> def COM_FST0r : FPST0rInst <MRM2r, "fcom\t$op">;<br> def COMP_FST0r : FPST0rInst <MRM3r, "fcomp\t$op">;<br>@@ -264,7 +279,9 @@ def _F : FPI<0xD9, fp, (outs), (ins)<br> let Defs = [FPSW] in {<br> defm CHS : FPUnary<fneg, MRM_E0, "fchs">;<br> defm ABS : FPUnary<fabs, MRM_E1, "fabs">;<br>+let SchedRW = [WriteFSqrt] in {<br> defm SQRT: FPUnary<fsqrt,MRM_FA, "fsqrt">;<br>+}<br> defm SIN : FPUnary<fsin, MRM_FE, "fsin">;<br> defm COS : FPUnary<fcos, MRM_FF, "fcos">;<br><br><br><br>_______________________________________________<br>llvm-commits mailing list<br><a href="mailto:llvm-commits@cs.uiuc.edu">llvm-commits@cs.uiuc.edu</a><br>http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits<br></blockquote></blockquote></div><br></div></body></html>