<div dir="ltr">I've tried to fix this in r203441 to get the bot green again.</div><div class="gmail_extra"><br><br><div class="gmail_quote">On Fri, Mar 7, 2014 at 12:36 AM, Evgeniy Stepanov <span dir="ltr"><<a href="mailto:eugeni.stepanov@gmail.com" target="_blank">eugeni.stepanov@gmail.com</a>></span> wrote:<br>
<blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">I think this is causing a new MSan failing in bootstrap:<br>
./bin/llc < ../llvm/test/CodeGen/AArch64/cpus.ll<br>
-mtriple=aarch64-unknown-unknown -mcpu=cortex-a57<br>
WARNING: MemorySanitizer: use-of-uninitialized-value<br>
#0 0x7fc10875db23 in<br>
llvm::AArch64Subtarget::ParseSubtargetFeatures(llvm::StringRef,<br>
llvm::StringRef)<br>
llvm_build_msan/lib/Target/AArch64/AArch64GenSubtargetInfo.inc:189<br>
#1 0x7fc10875e5bd in<br>
llvm::AArch64Subtarget::initializeSubtargetFeatures(llvm::StringRef,<br>
llvm::StringRef) llvm/lib/Target/AArch64/AArch64Subtarget.cpp:54<br>
#2 0x7fc10875e16e in<br>
llvm::AArch64Subtarget::AArch64Subtarget(llvm::StringRef,<br>
llvm::StringRef, llvm::StringRef, bool)<br>
llvm/lib/Target/AArch64/AArch64Subtarget.cpp:37<br>
#3 0x7fc10875f071 in<br>
llvm::AArch64TargetMachine::AArch64TargetMachine(llvm::Target const&,<br>
llvm::StringRef, llvm::StringRef, llvm::StringRef, llvm::TargetOptions<br>
const&, llvm::Reloc::Model, llvm::CodeModel::Model,<br>
llvm::CodeGenOpt::Level, bool)<br>
llvm/lib/Target/AArch64/AArch64TargetMachine.cpp:44<br>
#4 0x7fc10875fff5 in AArch64leTargetMachine<br>
llvm/lib/Target/AArch64/AArch64TargetMachine.cpp:55<br>
#5 0x7fc10875fff5 in<br>
llvm::RegisterTargetMachine<llvm::AArch64leTargetMachine>::Allocator(llvm::Target<br>
const&, llvm::StringRef, llvm::StringRef, llvm::StringRef,<br>
llvm::TargetOptions const&, llvm::Reloc::Model,<br>
llvm::CodeModel::Model, llvm::CodeGenOpt::Level)<br>
llvm/include/llvm/Support/TargetRegistry.h:1060<br>
#6 0x7fc10874804a in StringRef<br>
llvm/include/llvm/Support/TargetRegistry.h:346<br>
#7 0x7fc10874804a in compileModule llvm/tools/llc/llc.cpp:270<br>
#8 0x7fc10874804a in main llvm/tools/llc/llc.cpp:201<br>
<div class="HOEnZb"><div class="h5"><br>
<br>
On Thu, Mar 6, 2014 at 8:04 PM, Chad Rosier <<a href="mailto:mcrosier@codeaurora.org">mcrosier@codeaurora.org</a>> wrote:<br>
> Author: mcrosier<br>
> Date: Thu Mar 6 10:04:00 2014<br>
> New Revision: 203125<br>
><br>
> URL: <a href="http://llvm.org/viewvc/llvm-project?rev=203125&view=rev" target="_blank">http://llvm.org/viewvc/llvm-project?rev=203125&view=rev</a><br>
> Log:<br>
> [AArch64] This is a work in progress to provide a machine description<br>
> for the Cortex-A53 subtarget in the AArch64 backend.<br>
><br>
> This patch lays the ground work to annotate each AArch64 instruction<br>
> (no NEON yet) with a list of SchedReadWrite types. The patch also<br>
> provides the Cortex-A53 processor resources, maps those the the default<br>
> SchedReadWrites, and provides basic latency. NEON support will be added<br>
> in a subsequent patch with proper forwarding logic.<br>
><br>
> Verification was done by setting the pre-RA scheduler to linearize to<br>
> better gauge the effect of the MIScheduler. Even without modeling the<br>
> forward logic, the results show a modest improvement for Cortex-A53.<br>
><br>
> Reviewers: apazos, mcrosier, atrick<br>
> Patch by Dave Estes <<a href="mailto:cestes@codeaurora.org">cestes@codeaurora.org</a>>!<br>
><br>
> Added:<br>
> llvm/trunk/lib/Target/AArch64/AArch64ScheduleA53.td<br>
> llvm/trunk/test/CodeGen/AArch64/misched-basic-A53.ll<br>
> Modified:<br>
> llvm/trunk/lib/Target/AArch64/AArch64.td<br>
> llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.td<br>
> llvm/trunk/lib/Target/AArch64/AArch64Schedule.td<br>
> llvm/trunk/lib/Target/AArch64/AArch64Subtarget.h<br>
><br>
> Modified: llvm/trunk/lib/Target/AArch64/AArch64.td<br>
> URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64.td?rev=203125&r1=203124&r2=203125&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64.td?rev=203125&r1=203124&r2=203125&view=diff</a><br>
> ==============================================================================<br>
> --- llvm/trunk/lib/Target/AArch64/AArch64.td (original)<br>
> +++ llvm/trunk/lib/Target/AArch64/AArch64.td Thu Mar 6 10:04:00 2014<br>
> @@ -41,13 +41,20 @@ class ProcNoItin<string Name, list<Subta<br>
><br>
> def : Processor<"generic", GenericItineraries, [FeatureFPARMv8, FeatureNEON]>;<br>
><br>
> -def : ProcNoItin<"cortex-a53", [FeatureFPARMv8,<br>
> - FeatureNEON,<br>
> - FeatureCrypto]>;<br>
> +def ProcA53 : SubtargetFeature<"a53", "ARMProcFamily", "CortexA53",<br>
> + "Cortex-A53 ARM processors",<br>
> + [FeatureFPARMv8,<br>
> + FeatureNEON,<br>
> + FeatureCrypto]>;<br>
><br>
> -def : ProcNoItin<"cortex-a57", [FeatureFPARMv8,<br>
> - FeatureNEON,<br>
> - FeatureCrypto]>;<br>
> +def ProcA57 : SubtargetFeature<"a57", "ARMProcFamily", "CortexA57",<br>
> + "Cortex-A57 ARM processors",<br>
> + [FeatureFPARMv8,<br>
> + FeatureNEON,<br>
> + FeatureCrypto]>;<br>
> +<br>
> +def : ProcessorModel<"cortex-a53", CortexA53Model, [ProcA53]>;<br>
> +def : Processor<"cortex-a57", NoItineraries, [ProcA57]>;<br>
><br>
> //===----------------------------------------------------------------------===//<br>
> // Register File Description<br>
><br>
> Modified: llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.td<br>
> URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.td?rev=203125&r1=203124&r2=203125&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.td?rev=203125&r1=203124&r2=203125&view=diff</a><br>
> ==============================================================================<br>
> --- llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.td (original)<br>
> +++ llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.td Thu Mar 6 10:04:00 2014<br>
> @@ -350,33 +350,39 @@ multiclass addsub_exts<bit sf, bit op, b<br>
> outs, (ins exts.GPR:$Rn, GPR32:$Rm, UXTB_operand:$Imm3),<br>
> !strconcat(asmop, "$Rn, $Rm, $Imm3"),<br>
> [(opfrag exts.ty:$Rn, (shl exts.uxtb, UXTB_operand:$Imm3))],<br>
> - NoItinerary>;<br>
> + NoItinerary>,<br>
> + Sched<[WriteALU, ReadALU, ReadALU]>;<br>
> def w_uxth : A64I_addsubext<sf, op, S, 0b00, 0b001,<br>
> outs, (ins exts.GPR:$Rn, GPR32:$Rm, UXTH_operand:$Imm3),<br>
> !strconcat(asmop, "$Rn, $Rm, $Imm3"),<br>
> [(opfrag exts.ty:$Rn, (shl exts.uxth, UXTH_operand:$Imm3))],<br>
> - NoItinerary>;<br>
> + NoItinerary>,<br>
> + Sched<[WriteALU, ReadALU, ReadALU]>;<br>
> def w_uxtw : A64I_addsubext<sf, op, S, 0b00, 0b010,<br>
> outs, (ins exts.GPR:$Rn, GPR32:$Rm, UXTW_operand:$Imm3),<br>
> !strconcat(asmop, "$Rn, $Rm, $Imm3"),<br>
> [(opfrag exts.ty:$Rn, (shl exts.uxtw, UXTW_operand:$Imm3))],<br>
> - NoItinerary>;<br>
> + NoItinerary>,<br>
> + Sched<[WriteALU, ReadALU, ReadALU]>;<br>
><br>
> def w_sxtb : A64I_addsubext<sf, op, S, 0b00, 0b100,<br>
> outs, (ins exts.GPR:$Rn, GPR32:$Rm, SXTB_operand:$Imm3),<br>
> !strconcat(asmop, "$Rn, $Rm, $Imm3"),<br>
> [(opfrag exts.ty:$Rn, (shl exts.sxtb, SXTB_operand:$Imm3))],<br>
> - NoItinerary>;<br>
> + NoItinerary>,<br>
> + Sched<[WriteALU, ReadALU, ReadALU]>;<br>
> def w_sxth : A64I_addsubext<sf, op, S, 0b00, 0b101,<br>
> outs, (ins exts.GPR:$Rn, GPR32:$Rm, SXTH_operand:$Imm3),<br>
> !strconcat(asmop, "$Rn, $Rm, $Imm3"),<br>
> [(opfrag exts.ty:$Rn, (shl exts.sxth, SXTH_operand:$Imm3))],<br>
> - NoItinerary>;<br>
> + NoItinerary>,<br>
> + Sched<[WriteALU, ReadALU, ReadALU]>;<br>
> def w_sxtw : A64I_addsubext<sf, op, S, 0b00, 0b110,<br>
> outs, (ins exts.GPR:$Rn, GPR32:$Rm, SXTW_operand:$Imm3),<br>
> !strconcat(asmop, "$Rn, $Rm, $Imm3"),<br>
> [(opfrag exts.ty:$Rn, (shl exts.sxtw, SXTW_operand:$Imm3))],<br>
> - NoItinerary>;<br>
> + NoItinerary>,<br>
> + Sched<[WriteALU, ReadALU, ReadALU]>;<br>
> }<br>
><br>
> // These two could be merge in with the above, but their patterns aren't really<br>
> @@ -388,30 +394,32 @@ multiclass addsub_xxtx<bit op, bit S, st<br>
> (ins GPR64xsp:$Rn, GPR64:$Rm, UXTX_operand:$Imm3),<br>
> !strconcat(asmop, "$Rn, $Rm, $Imm3"),<br>
> [(opfrag i64:$Rn, (shl i64:$Rm, UXTX_operand:$Imm3))],<br>
> - NoItinerary>;<br>
> + NoItinerary>,<br>
> + Sched<[WriteALU, ReadALU, ReadALU]>;<br>
><br>
> def x_sxtx : A64I_addsubext<0b1, op, S, 0b00, 0b111,<br>
> outs,<br>
> (ins GPR64xsp:$Rn, GPR64:$Rm, SXTX_operand:$Imm3),<br>
> !strconcat(asmop, "$Rn, $Rm, $Imm3"),<br>
> [/* No Pattern: same as uxtx */],<br>
> - NoItinerary>;<br>
> + NoItinerary>,<br>
> + Sched<[WriteALU, ReadALU, ReadALU]>;<br>
> }<br>
><br>
> multiclass addsub_wxtx<bit op, bit S, string asmop, dag outs> {<br>
> def w_uxtx : A64I_addsubext<0b0, op, S, 0b00, 0b011,<br>
> - outs,<br>
> - (ins GPR32wsp:$Rn, GPR32:$Rm, UXTX_operand:$Imm3),<br>
> - !strconcat(asmop, "$Rn, $Rm, $Imm3"),<br>
> - [/* No pattern: probably same as uxtw */],<br>
> - NoItinerary>;<br>
> + outs, (ins GPR32wsp:$Rn, GPR32:$Rm, UXTX_operand:$Imm3),<br>
> + !strconcat(asmop, "$Rn, $Rm, $Imm3"),<br>
> + [/* No pattern: probably same as uxtw */],<br>
> + NoItinerary>,<br>
> + Sched<[WriteALU, ReadALU, ReadALU]>;<br>
><br>
> def w_sxtx : A64I_addsubext<0b0, op, S, 0b00, 0b111,<br>
> - outs,<br>
> - (ins GPR32wsp:$Rn, GPR32:$Rm, SXTX_operand:$Imm3),<br>
> - !strconcat(asmop, "$Rn, $Rm, $Imm3"),<br>
> - [/* No Pattern: probably same as uxtw */],<br>
> - NoItinerary>;<br>
> + outs, (ins GPR32wsp:$Rn, GPR32:$Rm, SXTX_operand:$Imm3),<br>
> + !strconcat(asmop, "$Rn, $Rm, $Imm3"),<br>
> + [/* No Pattern: probably same as uxtw */],<br>
> + NoItinerary>,<br>
> + Sched<[WriteALU, ReadALU, ReadALU]>;<br>
> }<br>
><br>
> class SetRD<RegisterClass RC, SDPatternOperator op><br>
> @@ -657,7 +665,8 @@ multiclass addsubimm_varieties<string pr<br>
> (ins GPRsp:$Rn, imm_operand:$Imm12),<br>
> !strconcat(asmop, "\t$Rd, $Rn, $Imm12"),<br>
> [(set Ty:$Rd, (add Ty:$Rn, imm_operand:$Imm12))],<br>
> - NoItinerary>;<br>
> + NoItinerary>,<br>
> + Sched<[WriteALU, ReadALU]>;<br>
><br>
><br>
> // S variants can read SP but would write to ZR<br>
> @@ -666,7 +675,8 @@ multiclass addsubimm_varieties<string pr<br>
> (ins GPRsp:$Rn, imm_operand:$Imm12),<br>
> !strconcat(asmop, "s\t$Rd, $Rn, $Imm12"),<br>
> [(set Ty:$Rd, (addc Ty:$Rn, imm_operand:$Imm12))],<br>
> - NoItinerary> {<br>
> + NoItinerary>,<br>
> + Sched<[WriteALU, ReadALU]> {<br>
> let Defs = [NZCV];<br>
> }<br>
><br>
> @@ -678,7 +688,8 @@ multiclass addsubimm_varieties<string pr<br>
> !strconcat(cmpasmop, " $Rn, $Imm12"),<br>
> [(set NZCV,<br>
> (A64cmp Ty:$Rn, cmp_imm_operand:$Imm12))],<br>
> - NoItinerary> {<br>
> + NoItinerary>,<br>
> + Sched<[WriteALU, ReadALU]> {<br>
> let Rd = 0b11111;<br>
> let Defs = [NZCV];<br>
> let isCompare = 1;<br>
> @@ -740,7 +751,7 @@ defm MOVww : MOVsp<GPR32wsp, Rwsp, ADDww<br>
> // Contains: ADD, ADDS, SUB, SUBS + aliases CMN, CMP, NEG, NEGS<br>
><br>
> //===-------------------------------<br>
> -// 1. The "shifed register" operands. Shared with logical insts.<br>
> +// 1. The "shifted register" operands. Shared with logical insts.<br>
> //===-------------------------------<br>
><br>
> multiclass shift_operands<string prefix, string form> {<br>
> @@ -800,7 +811,8 @@ multiclass addsub_shifts<string prefix,<br>
> [(set GPR:$Rd, (opfrag ty:$Rn, (shl ty:$Rm,<br>
> !cast<Operand>("lsl_operand_" # ty):$Imm6))<br>
> )],<br>
> - NoItinerary>;<br>
> + NoItinerary>,<br>
> + Sched<[WriteALU, ReadALU]>;<br>
><br>
> def _lsr : A64I_addsubshift<sf, op, s, 0b01,<br>
> (outs GPR:$Rd),<br>
> @@ -810,7 +822,8 @@ multiclass addsub_shifts<string prefix,<br>
> [(set ty:$Rd, (opfrag ty:$Rn, (srl ty:$Rm,<br>
> !cast<Operand>("lsr_operand_" # ty):$Imm6))<br>
> )],<br>
> - NoItinerary>;<br>
> + NoItinerary>,<br>
> + Sched<[WriteALU, ReadALU]>;<br>
><br>
> def _asr : A64I_addsubshift<sf, op, s, 0b10,<br>
> (outs GPR:$Rd),<br>
> @@ -820,7 +833,8 @@ multiclass addsub_shifts<string prefix,<br>
> [(set ty:$Rd, (opfrag ty:$Rn, (sra ty:$Rm,<br>
> !cast<Operand>("asr_operand_" # ty):$Imm6))<br>
> )],<br>
> - NoItinerary>;<br>
> + NoItinerary>,<br>
> + Sched<[WriteALU, ReadALU]>;<br>
> }<br>
><br>
> def _noshift<br>
> @@ -906,7 +920,8 @@ multiclass cmp_shifts<string prefix, bit<br>
> [(set NZCV, (opfrag ty:$Rn, (shl ty:$Rm,<br>
> !cast<Operand>("lsl_operand_" # ty):$Imm6))<br>
> )],<br>
> - NoItinerary>;<br>
> + NoItinerary>,<br>
> + Sched<[WriteCMP, ReadCMP, ReadCMP]>;<br>
><br>
> def _lsr : A64I_addsubshift<sf, op, 0b1, 0b01,<br>
> (outs),<br>
> @@ -916,7 +931,8 @@ multiclass cmp_shifts<string prefix, bit<br>
> [(set NZCV, (opfrag ty:$Rn, (srl ty:$Rm,<br>
> !cast<Operand>("lsr_operand_" # ty):$Imm6))<br>
> )],<br>
> - NoItinerary>;<br>
> + NoItinerary>,<br>
> + Sched<[WriteCMP, ReadCMP, ReadCMP]>;<br>
><br>
> def _asr : A64I_addsubshift<sf, op, 0b1, 0b10,<br>
> (outs),<br>
> @@ -926,7 +942,8 @@ multiclass cmp_shifts<string prefix, bit<br>
> [(set NZCV, (opfrag ty:$Rn, (sra ty:$Rm,<br>
> !cast<Operand>("asr_operand_" # ty):$Imm6))<br>
> )],<br>
> - NoItinerary>;<br>
> + NoItinerary>,<br>
> + Sched<[WriteCMP, ReadCMP, ReadCMP]>;<br>
> }<br>
><br>
> def _noshift<br>
> @@ -953,12 +970,14 @@ multiclass A64I_addsubcarrySizes<bit op,<br>
> def www : A64I_addsubcarry<0b0, op, s, 0b000000,<br>
> (outs GPR32:$Rd), (ins GPR32:$Rn, GPR32:$Rm),<br>
> !strconcat(asmop, "\t$Rd, $Rn, $Rm"),<br>
> - [], NoItinerary>;<br>
> + [], NoItinerary>,<br>
> + Sched<[WriteALU, ReadALU, ReadALU]>;<br>
><br>
> def xxx : A64I_addsubcarry<0b1, op, s, 0b000000,<br>
> (outs GPR64:$Rd), (ins GPR64:$Rn, GPR64:$Rm),<br>
> !strconcat(asmop, "\t$Rd, $Rn, $Rm"),<br>
> - [], NoItinerary>;<br>
> + [], NoItinerary>,<br>
> + Sched<[WriteALU, ReadALU, ReadALU]>;<br>
> }<br>
> }<br>
><br>
> @@ -1044,14 +1063,16 @@ multiclass A64I_bitfieldSizes<bits<2> op<br>
> def wwii : A64I_bitfield<0b0, opc, 0b0, (outs GPR32:$Rd),<br>
> (ins GPR32:$Rn, bitfield32_imm:$ImmR, bitfield32_imm:$ImmS),<br>
> !strconcat(asmop, "\t$Rd, $Rn, $ImmR, $ImmS"),<br>
> - [], NoItinerary> {<br>
> + [], NoItinerary>,<br>
> + Sched<[WriteALU, ReadALU]> {<br>
> let DecoderMethod = "DecodeBitfieldInstruction";<br>
> }<br>
><br>
> def xxii : A64I_bitfield<0b1, opc, 0b1, (outs GPR64:$Rd),<br>
> (ins GPR64:$Rn, bitfield64_imm:$ImmR, bitfield64_imm:$ImmS),<br>
> !strconcat(asmop, "\t$Rd, $Rn, $ImmR, $ImmS"),<br>
> - [], NoItinerary> {<br>
> + [], NoItinerary>,<br>
> + Sched<[WriteALU, ReadALU]> {<br>
> let DecoderMethod = "DecodeBitfieldInstruction";<br>
> }<br>
> }<br>
> @@ -1064,7 +1085,8 @@ defm UBFM : A64I_bitfieldSizes<0b10, "ub<br>
> def BFMwwii :<br>
> A64I_bitfield<0b0, 0b01, 0b0, (outs GPR32:$Rd),<br>
> (ins GPR32:$src, GPR32:$Rn, bitfield32_imm:$ImmR, bitfield32_imm:$ImmS),<br>
> - "bfm\t$Rd, $Rn, $ImmR, $ImmS", [], NoItinerary> {<br>
> + "bfm\t$Rd, $Rn, $ImmR, $ImmS", [], NoItinerary>,<br>
> + Sched<[WriteALU, ReadALU]> {<br>
> let DecoderMethod = "DecodeBitfieldInstruction";<br>
> let Constraints = "$src = $Rd";<br>
> }<br>
> @@ -1072,7 +1094,8 @@ def BFMwwii :<br>
> def BFMxxii :<br>
> A64I_bitfield<0b1, 0b01, 0b1, (outs GPR64:$Rd),<br>
> (ins GPR64:$src, GPR64:$Rn, bitfield64_imm:$ImmR, bitfield64_imm:$ImmS),<br>
> - "bfm\t$Rd, $Rn, $ImmR, $ImmS", [], NoItinerary> {<br>
> + "bfm\t$Rd, $Rn, $ImmR, $ImmS", [], NoItinerary>,<br>
> + Sched<[WriteALU, ReadALU]> {<br>
> let DecoderMethod = "DecodeBitfieldInstruction";<br>
> let Constraints = "$src = $Rd";<br>
> }<br>
> @@ -1094,7 +1117,8 @@ class A64I_bf_ext<bit sf, bits<2> opc, R<br>
> : A64I_bitfield<sf, opc, sf,<br>
> (outs GPRDest:$Rd), (ins GPR32:$Rn),<br>
> !strconcat(asmop, "\t$Rd, $Rn"),<br>
> - [(set dty:$Rd, pattern)], NoItinerary> {<br>
> + [(set dty:$Rd, pattern)], NoItinerary>,<br>
> + Sched<[WriteALU, ReadALU]> {<br>
> let ImmR = 0b000000;<br>
> let ImmS = imms;<br>
> }<br>
> @@ -1148,7 +1172,8 @@ multiclass A64I_shift<bits<2> opc, strin<br>
> (outs GPR32:$Rd), (ins GPR32:$Rn, bitfield32_imm:$ImmR),<br>
> !strconcat(asmop, "\t$Rd, $Rn, $ImmR"),<br>
> [(set i32:$Rd, (opnode i32:$Rn, bitfield32_imm:$ImmR))],<br>
> - NoItinerary> {<br>
> + NoItinerary>,<br>
> + Sched<[WriteALU, ReadALU]> {<br>
> let ImmS = 31;<br>
> }<br>
><br>
> @@ -1156,7 +1181,8 @@ multiclass A64I_shift<bits<2> opc, strin<br>
> (outs GPR64:$Rd), (ins GPR64:$Rn, bitfield64_imm:$ImmR),<br>
> !strconcat(asmop, "\t$Rd, $Rn, $ImmR"),<br>
> [(set i64:$Rd, (opnode i64:$Rn, bitfield64_imm:$ImmR))],<br>
> - NoItinerary> {<br>
> + NoItinerary>,<br>
> + Sched<[WriteALU, ReadALU]> {<br>
> let ImmS = 63;<br>
> }<br>
><br>
> @@ -1197,7 +1223,8 @@ class A64I_bitfield_lsl<bit sf, Register<br>
> : A64I_bitfield<sf, 0b10, sf, (outs GPR:$Rd), (ins GPR:$Rn, operand:$FullImm),<br>
> "lsl\t$Rd, $Rn, $FullImm",<br>
> [(set ty:$Rd, (shl ty:$Rn, operand:$FullImm))],<br>
> - NoItinerary> {<br>
> + NoItinerary>,<br>
> + Sched<[WriteALU, ReadALU]> {<br>
> bits<12> FullImm;<br>
> let ImmR = FullImm{5-0};<br>
> let ImmS = FullImm{11-6};<br>
> @@ -1244,7 +1271,8 @@ multiclass A64I_bitfield_extract<bits<2><br>
> (ins GPR32:$Rn, bitfield32_imm:$ImmR, bfx32_width:$ImmS),<br>
> !strconcat(asmop, "\t$Rd, $Rn, $ImmR, $ImmS"),<br>
> [(set i32:$Rd, (op i32:$Rn, imm:$ImmR, imm:$ImmS))],<br>
> - NoItinerary> {<br>
> + NoItinerary>,<br>
> + Sched<[WriteALU, ReadALU]> {<br>
> // As above, no disassembler allowed.<br>
> let isAsmParserOnly = 1;<br>
> }<br>
> @@ -1253,7 +1281,8 @@ multiclass A64I_bitfield_extract<bits<2><br>
> (ins GPR64:$Rn, bitfield64_imm:$ImmR, bfx64_width:$ImmS),<br>
> !strconcat(asmop, "\t$Rd, $Rn, $ImmR, $ImmS"),<br>
> [(set i64:$Rd, (op i64:$Rn, imm:$ImmR, imm:$ImmS))],<br>
> - NoItinerary> {<br>
> + NoItinerary>,<br>
> + Sched<[WriteALU, ReadALU]> {<br>
> // As above, no disassembler allowed.<br>
> let isAsmParserOnly = 1;<br>
> }<br>
> @@ -1264,16 +1293,18 @@ defm UBFX : A64I_bitfield_extract<0b10,<br>
><br>
> // Again, variants based on BFM modify Rd so need it as an input too.<br>
> def BFXILwwii : A64I_bitfield<0b0, 0b01, 0b0, (outs GPR32:$Rd),<br>
> - (ins GPR32:$src, GPR32:$Rn, bitfield32_imm:$ImmR, bfx32_width:$ImmS),<br>
> - "bfxil\t$Rd, $Rn, $ImmR, $ImmS", [], NoItinerary> {<br>
> + (ins GPR32:$src, GPR32:$Rn, bitfield32_imm:$ImmR, bfx32_width:$ImmS),<br>
> + "bfxil\t$Rd, $Rn, $ImmR, $ImmS", [], NoItinerary>,<br>
> + Sched<[WriteALU, ReadALU]> {<br>
> // As above, no disassembler allowed.<br>
> let isAsmParserOnly = 1;<br>
> let Constraints = "$src = $Rd";<br>
> }<br>
><br>
> def BFXILxxii : A64I_bitfield<0b1, 0b01, 0b1, (outs GPR64:$Rd),<br>
> - (ins GPR64:$src, GPR64:$Rn, bitfield64_imm:$ImmR, bfx64_width:$ImmS),<br>
> - "bfxil\t$Rd, $Rn, $ImmR, $ImmS", [], NoItinerary> {<br>
> + (ins GPR64:$src, GPR64:$Rn, bitfield64_imm:$ImmR, bfx64_width:$ImmS),<br>
> + "bfxil\t$Rd, $Rn, $ImmR, $ImmS", [], NoItinerary>,<br>
> + Sched<[WriteALU, ReadALU]> {<br>
> // As above, no disassembler allowed.<br>
> let isAsmParserOnly = 1;<br>
> let Constraints = "$src = $Rd";<br>
> @@ -1353,7 +1384,8 @@ multiclass A64I_bitfield_insert<bits<2><br>
> def wwii : A64I_bitfield<0b0, opc, 0b0, (outs GPR32:$Rd),<br>
> (ins GPR32:$Rn, bfi32_lsb:$ImmR, bfi32_width:$ImmS),<br>
> !strconcat(asmop, "\t$Rd, $Rn, $ImmR, $ImmS"),<br>
> - [], NoItinerary> {<br>
> + [], NoItinerary>,<br>
> + Sched<[WriteALU, ReadALU]> {<br>
> // As above, no disassembler allowed.<br>
> let isAsmParserOnly = 1;<br>
> }<br>
> @@ -1361,7 +1393,8 @@ multiclass A64I_bitfield_insert<bits<2><br>
> def xxii : A64I_bitfield<0b1, opc, 0b1, (outs GPR64:$Rd),<br>
> (ins GPR64:$Rn, bfi64_lsb:$ImmR, bfi64_width:$ImmS),<br>
> !strconcat(asmop, "\t$Rd, $Rn, $ImmR, $ImmS"),<br>
> - [], NoItinerary> {<br>
> + [], NoItinerary>,<br>
> + Sched<[WriteALU, ReadALU]> {<br>
> // As above, no disassembler allowed.<br>
> let isAsmParserOnly = 1;<br>
> }<br>
> @@ -1373,7 +1406,8 @@ defm UBFIZ : A64I_bitfield_insert<0b10,<br>
><br>
> def BFIwwii : A64I_bitfield<0b0, 0b01, 0b0, (outs GPR32:$Rd),<br>
> (ins GPR32:$src, GPR32:$Rn, bfi32_lsb:$ImmR, bfi32_width:$ImmS),<br>
> - "bfi\t$Rd, $Rn, $ImmR, $ImmS", [], NoItinerary> {<br>
> + "bfi\t$Rd, $Rn, $ImmR, $ImmS", [], NoItinerary>,<br>
> + Sched<[WriteALU, ReadALU]> {<br>
> // As above, no disassembler allowed.<br>
> let isAsmParserOnly = 1;<br>
> let Constraints = "$src = $Rd";<br>
> @@ -1381,7 +1415,8 @@ def BFIwwii : A64I_bitfield<0b0, 0b01, 0<br>
><br>
> def BFIxxii : A64I_bitfield<0b1, 0b01, 0b1, (outs GPR64:$Rd),<br>
> (ins GPR64:$src, GPR64:$Rn, bfi64_lsb:$ImmR, bfi64_width:$ImmS),<br>
> - "bfi\t$Rd, $Rn, $ImmR, $ImmS", [], NoItinerary> {<br>
> + "bfi\t$Rd, $Rn, $ImmR, $ImmS", [], NoItinerary>,<br>
> + Sched<[WriteALU, ReadALU]> {<br>
> // As above, no disassembler allowed.<br>
> let isAsmParserOnly = 1;<br>
> let Constraints = "$src = $Rd";<br>
> @@ -1418,14 +1453,16 @@ multiclass cmpbr_sizes<bit op, string as<br>
> (ins GPR64:$Rt, bcc_target:$Label),<br>
> !strconcat(asmop,"\t$Rt, $Label"),<br>
> [(A64br_cc (A64cmp i64:$Rt, 0), SETOP, bb:$Label)],<br>
> - NoItinerary>;<br>
> + NoItinerary>,<br>
> + Sched<[WriteBr, ReadBr]>;<br>
><br>
> def w : A64I_cmpbr<0b0, op,<br>
> (outs),<br>
> (ins GPR32:$Rt, bcc_target:$Label),<br>
> !strconcat(asmop,"\t$Rt, $Label"),<br>
> [(A64br_cc (A64cmp i32:$Rt, 0), SETOP, bb:$Label)],<br>
> - NoItinerary>;<br>
> + NoItinerary>,<br>
> + Sched<[WriteBr, ReadBr]>;<br>
> }<br>
> }<br>
><br>
> @@ -1456,7 +1493,8 @@ def cond_code : Operand<i32>, ImmLeaf<i3<br>
> def Bcc : A64I_condbr<0b0, 0b0, (outs),<br>
> (ins cond_code:$Cond, bcc_target:$Label),<br>
> "b.$Cond $Label", [(A64br_cc NZCV, (i32 imm:$Cond), bb:$Label)],<br>
> - NoItinerary> {<br>
> + NoItinerary>,<br>
> + Sched<[WriteBr]> {<br>
> let Uses = [NZCV];<br>
> let isBranch = 1;<br>
> let isTerminator = 1;<br>
> @@ -1502,7 +1540,8 @@ class A64I_condcmpimmImpl<bit sf, bit op<br>
> : A64I_condcmpimm<sf, op, 0b0, 0b0, 0b1, (outs),<br>
> (ins GPR:$Rn, uimm5:$UImm5, uimm4:$NZCVImm, cond_code_op:$Cond),<br>
> !strconcat(asmop, "\t$Rn, $UImm5, $NZCVImm, $Cond"),<br>
> - [], NoItinerary> {<br>
> + [], NoItinerary>,<br>
> + Sched<[WriteCMP, ReadCMP]> {<br>
> let Defs = [NZCV];<br>
> }<br>
><br>
> @@ -1568,7 +1607,8 @@ multiclass A64I_condselSizes<bit op, bit<br>
> (ins GPR32:$Rn, GPR32:$Rm, cond_code_op:$Cond),<br>
> !strconcat(asmop, "\t$Rd, $Rn, $Rm, $Cond"),<br>
> [(set i32:$Rd, (select i32:$Rn, i32:$Rm))],<br>
> - NoItinerary>;<br>
> + NoItinerary>,<br>
> + Sched<[WriteCMP, ReadCMP]>;<br>
><br>
><br>
> def xxxc : A64I_condsel<0b1, op, 0b0, op2,<br>
> @@ -1576,7 +1616,8 @@ multiclass A64I_condselSizes<bit op, bit<br>
> (ins GPR64:$Rn, GPR64:$Rm, cond_code_op:$Cond),<br>
> !strconcat(asmop, "\t$Rd, $Rn, $Rm, $Cond"),<br>
> [(set i64:$Rd, (select i64:$Rn, i64:$Rm))],<br>
> - NoItinerary>;<br>
> + NoItinerary>,<br>
> + Sched<[WriteCMP, ReadCMP]>;<br>
> }<br>
> }<br>
><br>
> @@ -1686,7 +1727,8 @@ class A64I_dp_1src_impl<bit sf, bits<6><br>
> (outs GPRrc:$Rd),<br>
> (ins GPRrc:$Rn),<br>
> patterns,<br>
> - itin>;<br>
> + itin>,<br>
> + Sched<[WriteALU, ReadALU]>;<br>
><br>
> multiclass A64I_dp_1src <bits<6> opcode, string asmop> {<br>
> let hasSideEffects = 0 in {<br>
> @@ -1742,7 +1784,8 @@ class dp_2src_impl<bit sf, bits<6> opcod<br>
> (outs GPRsp:$Rd),<br>
> (ins GPRsp:$Rn, GPRsp:$Rm),<br>
> patterns,<br>
> - itin>;<br>
> + itin>,<br>
> + Sched<[WriteALU, ReadALU, ReadALU]>;<br>
><br>
> multiclass dp_2src_crc<bit c, string asmop> {<br>
> def B_www : dp_2src_impl<0b0, {0, 1, 0, c, 0, 0},<br>
> @@ -1793,13 +1836,17 @@ multiclass dp_2src <bits<6> opcode, stri<br>
> defm CRC32 : dp_2src_crc<0b0, "crc32">;<br>
> defm CRC32C : dp_2src_crc<0b1, "crc32c">;<br>
><br>
> -defm UDIV : dp_2src<0b000010, "udiv", udiv>;<br>
> -defm SDIV : dp_2src<0b000011, "sdiv", sdiv>;<br>
> +let SchedRW = [WriteDiv, ReadDiv, ReadDiv] in {<br>
> + defm UDIV : dp_2src<0b000010, "udiv", udiv>;<br>
> + defm SDIV : dp_2src<0b000011, "sdiv", sdiv>;<br>
> +}<br>
><br>
> -defm LSLV : dp_2src_zext<0b001000, "lsl", shl>;<br>
> -defm LSRV : dp_2src_zext<0b001001, "lsr", srl>;<br>
> -defm ASRV : dp_2src_zext<0b001010, "asr", sra>;<br>
> -defm RORV : dp_2src_zext<0b001011, "ror", rotr>;<br>
> +let SchedRW = [WriteALUs, ReadALU, ReadALU] in {<br>
> + defm LSLV : dp_2src_zext<0b001000, "lsl", shl>;<br>
> + defm LSRV : dp_2src_zext<0b001001, "lsr", srl>;<br>
> + defm ASRV : dp_2src_zext<0b001010, "asr", sra>;<br>
> + defm RORV : dp_2src_zext<0b001011, "ror", rotr>;<br>
> +}<br>
><br>
> // Extra patterns for an incoming 64-bit value for a 32-bit<br>
> // operation. Since the LLVM operations are undefined (as in C) if the<br>
> @@ -1832,7 +1879,8 @@ class A64I_dp3_4operand<bit sf, bits<6><br>
> : A64I_dp3<sf, opcode,<br>
> (outs AccReg:$Rd), (ins SrcReg:$Rn, SrcReg:$Rm, AccReg:$Ra),<br>
> !strconcat(asmop, "\t$Rd, $Rn, $Rm, $Ra"),<br>
> - [(set AccTy:$Rd, pattern)], NoItinerary> {<br>
> + [(set AccTy:$Rd, pattern)], NoItinerary>,<br>
> + Sched<[WriteMAC, ReadMAC, ReadMAC, ReadMAC]> {<br>
> RegisterClass AccGPR = AccReg;<br>
> RegisterClass SrcGPR = SrcReg;<br>
> }<br>
> @@ -1862,13 +1910,15 @@ let isCommutable = 1, PostEncoderMethod<br>
> (ins GPR64:$Rn, GPR64:$Rm),<br>
> "umulh\t$Rd, $Rn, $Rm",<br>
> [(set i64:$Rd, (mulhu i64:$Rn, i64:$Rm))],<br>
> - NoItinerary>;<br>
> + NoItinerary>,<br>
> + Sched<[WriteMAC, ReadMAC, ReadMAC]>;<br>
><br>
> def SMULHxxx : A64I_dp3<0b1, 0b000100, (outs GPR64:$Rd),<br>
> (ins GPR64:$Rn, GPR64:$Rm),<br>
> "smulh\t$Rd, $Rn, $Rm",<br>
> [(set i64:$Rd, (mulhs i64:$Rn, i64:$Rm))],<br>
> - NoItinerary>;<br>
> + NoItinerary>,<br>
> + Sched<[WriteMAC, ReadMAC, ReadMAC]>;<br>
> }<br>
><br>
> multiclass A64I_dp3_3operand<string asmop, A64I_dp3_4operand INST,<br>
> @@ -1916,7 +1966,8 @@ def uimm16 : Operand<i32> {<br>
><br>
> class A64I_exceptImpl<bits<3> opc, bits<2> ll, string asmop><br>
> : A64I_exception<opc, 0b000, ll, (outs), (ins uimm16:$UImm16),<br>
> - !strconcat(asmop, "\t$UImm16"), [], NoItinerary> {<br>
> + !strconcat(asmop, "\t$UImm16"), [], NoItinerary>,<br>
> + Sched<[WriteBr]> {<br>
> let isBranch = 1;<br>
> let isTerminator = 1;<br>
> }<br>
> @@ -1947,14 +1998,16 @@ def EXTRwwwi : A64I_extract<0b0, 0b000,<br>
> "extr\t$Rd, $Rn, $Rm, $LSB",<br>
> [(set i32:$Rd,<br>
> (A64Extr i32:$Rn, i32:$Rm, imm:$LSB))],<br>
> - NoItinerary>;<br>
> + NoItinerary>,<br>
> + Sched<[WriteALU, ReadALU, ReadALU]>;<br>
> def EXTRxxxi : A64I_extract<0b1, 0b000, 0b1,<br>
> (outs GPR64:$Rd),<br>
> (ins GPR64:$Rn, GPR64:$Rm, bitfield64_imm:$LSB),<br>
> "extr\t$Rd, $Rn, $Rm, $LSB",<br>
> [(set i64:$Rd,<br>
> (A64Extr i64:$Rn, i64:$Rm, imm:$LSB))],<br>
> - NoItinerary>;<br>
> + NoItinerary>,<br>
> + Sched<[WriteALU, ReadALU, ReadALU]>;<br>
><br>
> def : InstAlias<"ror $Rd, $Rs, $LSB",<br>
> (EXTRwwwi GPR32:$Rd, GPR32:$Rs, GPR32:$Rs, bitfield32_imm:$LSB)>;<br>
> @@ -2001,12 +2054,14 @@ def fpz64movi : Operand<i64>,<br>
> multiclass A64I_fpcmpSignal<bits<2> type, bit imm, dag ins, dag pattern> {<br>
> def _quiet : A64I_fpcmp<0b0, 0b0, type, 0b00, {0b0, imm, 0b0, 0b0, 0b0},<br>
> (outs), ins, "fcmp\t$Rn, $Rm", [pattern],<br>
> - NoItinerary> {<br>
> + NoItinerary>,<br>
> + Sched<[WriteFPALU, ReadFPALU, ReadFPALU]> {<br>
> let Defs = [NZCV];<br>
> }<br>
><br>
> def _sig : A64I_fpcmp<0b0, 0b0, type, 0b00, {0b1, imm, 0b0, 0b0, 0b0},<br>
> - (outs), ins, "fcmpe\t$Rn, $Rm", [], NoItinerary> {<br>
> + (outs), ins, "fcmpe\t$Rn, $Rm", [], NoItinerary>,<br>
> + Sched<[WriteFPALU, ReadFPALU, ReadFPALU]> {<br>
> let Defs = [NZCV];<br>
> }<br>
> }<br>
> @@ -2035,7 +2090,8 @@ class A64I_fpccmpImpl<bits<2> type, bit<br>
> (outs),<br>
> (ins FPR:$Rn, FPR:$Rm, uimm4:$NZCVImm, cond_code_op:$Cond),<br>
> !strconcat(asmop, "\t$Rn, $Rm, $NZCVImm, $Cond"),<br>
> - [], NoItinerary> {<br>
> + [], NoItinerary>,<br>
> + Sched<[WriteFPALU, ReadFPALU, ReadFPALU]> {<br>
> let Defs = [NZCV];<br>
> }<br>
><br>
> @@ -2053,9 +2109,10 @@ let Uses = [NZCV] in {<br>
> def FCSELsssc : A64I_fpcondsel<0b0, 0b0, 0b00, (outs FPR32:$Rd),<br>
> (ins FPR32:$Rn, FPR32:$Rm, cond_code_op:$Cond),<br>
> "fcsel\t$Rd, $Rn, $Rm, $Cond",<br>
> - [(set f32:$Rd,<br>
> + [(set f32:$Rd,<br>
> (simple_select f32:$Rn, f32:$Rm))],<br>
> - NoItinerary>;<br>
> + NoItinerary>,<br>
> + Sched<[WriteFPALU, ReadFPALU, ReadFPALU]>;<br>
><br>
><br>
> def FCSELdddc : A64I_fpcondsel<0b0, 0b0, 0b01, (outs FPR64:$Rd),<br>
> @@ -2063,7 +2120,8 @@ let Uses = [NZCV] in {<br>
> "fcsel\t$Rd, $Rn, $Rm, $Cond",<br>
> [(set f64:$Rd,<br>
> (simple_select f64:$Rn, f64:$Rm))],<br>
> - NoItinerary>;<br>
> + NoItinerary>,<br>
> + Sched<[WriteFPALU, ReadFPALU, ReadFPALU]>;<br>
> }<br>
><br>
> //===----------------------------------------------------------------------===//<br>
> @@ -2081,18 +2139,22 @@ multiclass A64I_fpdp1sizes<bits<6> opcod<br>
> def ss : A64I_fpdp1<0b0, 0b0, 0b00, opcode, (outs FPR32:$Rd), (ins FPR32:$Rn),<br>
> !strconcat(asmstr, "\t$Rd, $Rn"),<br>
> [(set f32:$Rd, (opnode f32:$Rn))],<br>
> - NoItinerary>;<br>
> + NoItinerary>,<br>
> + Sched<[WriteFPALU, ReadFPALU]>;<br>
><br>
> def dd : A64I_fpdp1<0b0, 0b0, 0b01, opcode, (outs FPR64:$Rd), (ins FPR64:$Rn),<br>
> !strconcat(asmstr, "\t$Rd, $Rn"),<br>
> [(set f64:$Rd, (opnode f64:$Rn))],<br>
> - NoItinerary>;<br>
> + NoItinerary>,<br>
> + Sched<[WriteFPALU, ReadFPALU]>;<br>
> }<br>
><br>
> defm FMOV : A64I_fpdp1sizes<0b000000, "fmov">;<br>
> defm FABS : A64I_fpdp1sizes<0b000001, "fabs", fabs>;<br>
> defm FNEG : A64I_fpdp1sizes<0b000010, "fneg", fneg>;<br>
> -defm FSQRT : A64I_fpdp1sizes<0b000011, "fsqrt", fsqrt>;<br>
> +let SchedRW = [WriteFPSqrt, ReadFPSqrt] in {<br>
> + defm FSQRT : A64I_fpdp1sizes<0b000011, "fsqrt", fsqrt>;<br>
> +}<br>
><br>
> defm FRINTN : A64I_fpdp1sizes<0b001000, "frintn">;<br>
> defm FRINTP : A64I_fpdp1sizes<0b001001, "frintp", fceil>;<br>
> @@ -2121,7 +2183,8 @@ class A64I_fpdp1_fcvt<FCVTRegType DestRe<br>
> {0,0,0,1, DestReg.t1, DestReg.t0},<br>
> (outs DestReg.Class:$Rd), (ins SrcReg.Class:$Rn),<br>
> "fcvt\t$Rd, $Rn",<br>
> - [(set DestReg.VT:$Rd, (opnode SrcReg.VT:$Rn))], NoItinerary>;<br>
> + [(set DestReg.VT:$Rd, (opnode SrcReg.VT:$Rn))], NoItinerary>,<br>
> + Sched<[WriteFPALU, ReadFPALU]>;<br>
><br>
> def FCVTds : A64I_fpdp1_fcvt<FCVT64, FCVT32, fextend>;<br>
> def FCVThs : A64I_fpdp1_fcvt<FCVT16, FCVT32, fround>;<br>
> @@ -2146,18 +2209,22 @@ multiclass A64I_fpdp2sizes<bits<4> opcod<br>
> (ins FPR32:$Rn, FPR32:$Rm),<br>
> !strconcat(asmstr, "\t$Rd, $Rn, $Rm"),<br>
> [(set f32:$Rd, (opnode f32:$Rn, f32:$Rm))],<br>
> - NoItinerary>;<br>
> + NoItinerary>,<br>
> + Sched<[WriteFPALU, ReadFPALU, ReadFPALU]>;<br>
><br>
> def ddd : A64I_fpdp2<0b0, 0b0, 0b01, opcode,<br>
> (outs FPR64:$Rd),<br>
> (ins FPR64:$Rn, FPR64:$Rm),<br>
> !strconcat(asmstr, "\t$Rd, $Rn, $Rm"),<br>
> [(set f64:$Rd, (opnode f64:$Rn, f64:$Rm))],<br>
> - NoItinerary>;<br>
> + NoItinerary>,<br>
> + Sched<[WriteFPALU, ReadFPALU, ReadFPALU]>;<br>
> }<br>
><br>
> let isCommutable = 1 in {<br>
> - defm FMUL : A64I_fpdp2sizes<0b0000, "fmul", fmul>;<br>
> + let SchedRW = [WriteFPMul, ReadFPMul, ReadFPMul] in {<br>
> + defm FMUL : A64I_fpdp2sizes<0b0000, "fmul", fmul>;<br>
> + }<br>
> defm FADD : A64I_fpdp2sizes<0b0010, "fadd", fadd>;<br>
><br>
> // No patterns for these.<br>
> @@ -2166,12 +2233,16 @@ let isCommutable = 1 in {<br>
> defm FMAXNM : A64I_fpdp2sizes<0b0110, "fmaxnm", FPNoBinop>;<br>
> defm FMINNM : A64I_fpdp2sizes<0b0111, "fminnm", FPNoBinop>;<br>
><br>
> - defm FNMUL : A64I_fpdp2sizes<0b1000, "fnmul",<br>
> - PatFrag<(ops node:$lhs, node:$rhs),<br>
> - (fneg (fmul node:$lhs, node:$rhs))> >;<br>
> + let SchedRW = [WriteFPMul, ReadFPMul, ReadFPMul] in {<br>
> + defm FNMUL : A64I_fpdp2sizes<0b1000, "fnmul",<br>
> + PatFrag<(ops node:$lhs, node:$rhs),<br>
> + (fneg (fmul node:$lhs, node:$rhs))> >;<br>
> + }<br>
> }<br>
><br>
> -defm FDIV : A64I_fpdp2sizes<0b0001, "fdiv", fdiv>;<br>
> +let SchedRW = [WriteFPDiv, ReadFPDiv, ReadFPDiv] in {<br>
> + defm FDIV : A64I_fpdp2sizes<0b0001, "fdiv", fdiv>;<br>
> +}<br>
> defm FSUB : A64I_fpdp2sizes<0b0011, "fsub", fsub>;<br>
><br>
> //===----------------------------------------------------------------------===//<br>
> @@ -2192,7 +2263,8 @@ class A64I_fpdp3Impl<string asmop, Regis<br>
> (ins FPR:$Rn, FPR:$Rm, FPR:$Ra),<br>
> !strconcat(asmop,"\t$Rd, $Rn, $Rm, $Ra"),<br>
> [(set VT:$Rd, (fmakind VT:$Rn, VT:$Rm, VT:$Ra))],<br>
> - NoItinerary>;<br>
> + NoItinerary>,<br>
> + Sched<[WriteFPMAC, ReadFPMAC, ReadFPMAC, ReadFPMAC]>;<br>
><br>
> def FMADDssss : A64I_fpdp3Impl<"fmadd", FPR32, f32, 0b00, 0b0, 0b0, fma>;<br>
> def FMSUBssss : A64I_fpdp3Impl<"fmsub", FPR32, f32, 0b00, 0b0, 0b1, fmsub>;<br>
> @@ -2271,14 +2343,15 @@ class cvtfix_i64_op<ValueType FloatVT><br>
> // worth going for a multiclass here. Oh well.<br>
><br>
> class A64I_fptofix<bit sf, bits<2> type, bits<3> opcode,<br>
> - RegisterClass GPR, RegisterClass FPR,<br>
> - ValueType DstTy, ValueType SrcTy,<br>
> + RegisterClass GPR, RegisterClass FPR,<br>
> + ValueType DstTy, ValueType SrcTy,<br>
> Operand scale_op, string asmop, SDNode cvtop><br>
> : A64I_fpfixed<sf, 0b0, type, 0b11, opcode,<br>
> (outs GPR:$Rd), (ins FPR:$Rn, scale_op:$Scale),<br>
> !strconcat(asmop, "\t$Rd, $Rn, $Scale"),<br>
> [(set DstTy:$Rd, (cvtop (fmul SrcTy:$Rn, scale_op:$Scale)))],<br>
> - NoItinerary>;<br>
> + NoItinerary>,<br>
> + Sched<[WriteFPALU, ReadFPALU]>;<br>
><br>
> def FCVTZSwsi : A64I_fptofix<0b0, 0b00, 0b000, GPR32, FPR32, i32, f32,<br>
> cvtfix_i32_op<f32>, "fcvtzs", fp_to_sint>;<br>
> @@ -2307,7 +2380,8 @@ class A64I_fixtofp<bit sf, bits<2> type,<br>
> (outs FPR:$Rd), (ins GPR:$Rn, scale_op:$Scale),<br>
> !strconcat(asmop, "\t$Rd, $Rn, $Scale"),<br>
> [(set DstTy:$Rd, (fdiv (cvtop SrcTy:$Rn), scale_op:$Scale))],<br>
> - NoItinerary>;<br>
> + NoItinerary>,<br>
> + Sched<[WriteFPALU, ReadFPALU]>;<br>
><br>
> def SCVTFswi : A64I_fixtofp<0b0, 0b00, 0b010, FPR32, GPR32, f32, i32,<br>
> cvtfix_i32_op<f32>, "scvtf", sint_to_fp>;<br>
> @@ -2334,7 +2408,8 @@ def UCVTFdxi : A64I_fixtofp<0b1, 0b01, 0<br>
> class A64I_fpintI<bit sf, bits<2> type, bits<2> rmode, bits<3> opcode,<br>
> RegisterClass DestPR, RegisterClass SrcPR, string asmop><br>
> : A64I_fpint<sf, 0b0, type, rmode, opcode, (outs DestPR:$Rd), (ins SrcPR:$Rn),<br>
> - !strconcat(asmop, "\t$Rd, $Rn"), [], NoItinerary>;<br>
> + !strconcat(asmop, "\t$Rd, $Rn"), [], NoItinerary>,<br>
> + Sched<[WriteFPALU, ReadFPALU]>;<br>
><br>
> multiclass A64I_fptointRM<bits<2> rmode, bit o2, string asmop> {<br>
> def Sws : A64I_fpintI<0b0, 0b00, rmode, {o2, 0, 0},<br>
> @@ -2420,11 +2495,13 @@ def lane1 : Operand<i32> {<br>
> let DecoderMethod = "DecodeFMOVLaneInstruction" in {<br>
> def FMOVxv : A64I_fpint<0b1, 0b0, 0b10, 0b01, 0b110,<br>
> (outs GPR64:$Rd), (ins VPR128:$Rn, lane1:$Lane),<br>
> - "fmov\t$Rd, $Rn.d[$Lane]", [], NoItinerary>;<br>
> + "fmov\t$Rd, $Rn.d[$Lane]", [], NoItinerary>,<br>
> + Sched<[WriteFPALU, ReadFPALU]>;<br>
><br>
> def FMOVvx : A64I_fpint<0b1, 0b0, 0b10, 0b01, 0b111,<br>
> (outs VPR128:$Rd), (ins GPR64:$Rn, lane1:$Lane),<br>
> - "fmov\t$Rd.d[$Lane], $Rn", [], NoItinerary>;<br>
> + "fmov\t$Rd.d[$Lane], $Rn", [], NoItinerary>,<br>
> + Sched<[WriteFPALU, ReadFPALU]>;<br>
> }<br>
><br>
> let Predicates = [HasFPARMv8] in {<br>
> @@ -2471,7 +2548,8 @@ class A64I_fpimm_impl<bits<2> type, Regi<br>
> (ins fmov_operand:$Imm8),<br>
> "fmov\t$Rd, $Imm8",<br>
> [(set VT:$Rd, fmov_operand:$Imm8)],<br>
> - NoItinerary>;<br>
> + NoItinerary>,<br>
> + Sched<[WriteFPALU]>;<br>
><br>
> def FMOVsi : A64I_fpimm_impl<0b00, FPR32, f32, fmov32_operand>;<br>
> def FMOVdi : A64I_fpimm_impl<0b01, FPR64, f64, fmov64_operand>;<br>
> @@ -2520,7 +2598,8 @@ defm prefetch : namedimm<"prefetch", "A6<br>
> class A64I_LDRlitSimple<bits<2> opc, bit v, RegisterClass OutReg,<br>
> list<dag> patterns = []><br>
> : A64I_LDRlit<opc, v, (outs OutReg:$Rt), (ins ldrlit_label:$Imm19),<br>
> - "ldr\t$Rt, $Imm19", patterns, NoItinerary>;<br>
> + "ldr\t$Rt, $Imm19", patterns, NoItinerary>,<br>
> + Sched<[WriteLd]>;<br>
><br>
> let mayLoad = 1 in {<br>
> def LDRw_lit : A64I_LDRlitSimple<0b00, 0b0, GPR32>;<br>
> @@ -2541,12 +2620,14 @@ let mayLoad = 1 in {<br>
> (outs GPR64:$Rt),<br>
> (ins ldrlit_label:$Imm19),<br>
> "ldrsw\t$Rt, $Imm19",<br>
> - [], NoItinerary>;<br>
> + [], NoItinerary>,<br>
> + Sched<[WriteLd]>;<br>
><br>
> def PRFM_lit : A64I_LDRlit<0b11, 0b0,<br>
> (outs), (ins prefetch_op:$Rt, ldrlit_label:$Imm19),<br>
> "prfm\t$Rt, $Imm19",<br>
> - [], NoItinerary>;<br>
> + [], NoItinerary>,<br>
> + Sched<[WriteLd]>;<br>
> }<br>
><br>
> //===----------------------------------------------------------------------===//<br>
> @@ -2638,19 +2719,23 @@ class A64I_LRexs_impl<bits<2> size, bits<br>
> multiclass A64I_LRex<string asmstr, bits<3> opcode> {<br>
> def _byte: A64I_LRexs_impl<0b00, opcode, !strconcat(asmstr, "b"),<br>
> (outs GPR32:$Rt), (ins GPR64xsp0:$Rn),<br>
> - [], NoItinerary>;<br>
> + [], NoItinerary>,<br>
> + Sched<[WriteLd]>;<br>
><br>
> def _hword: A64I_LRexs_impl<0b01, opcode, !strconcat(asmstr, "h"),<br>
> (outs GPR32:$Rt), (ins GPR64xsp0:$Rn),<br>
> - [], NoItinerary>;<br>
> + [], NoItinerary>,<br>
> + Sched<[WriteLd]>;<br>
><br>
> def _word: A64I_LRexs_impl<0b10, opcode, asmstr,<br>
> (outs GPR32:$Rt), (ins GPR64xsp0:$Rn),<br>
> - [], NoItinerary>;<br>
> + [], NoItinerary>,<br>
> + Sched<[WriteLd]>;<br>
><br>
> def _dword: A64I_LRexs_impl<0b11, opcode, asmstr,<br>
> (outs GPR64:$Rt), (ins GPR64xsp0:$Rn),<br>
> - [], NoItinerary>;<br>
> + [], NoItinerary>,<br>
> + Sched<[WriteLd]>;<br>
> }<br>
><br>
> defm LDXR : A64I_LRex<"ldxr", 0b000>;<br>
> @@ -2776,12 +2861,14 @@ multiclass A64I_LPex<string asmstr, bits<br>
> def _word: A64I_LPexs_impl<0b10, opcode, asmstr,<br>
> (outs GPR32:$Rt, GPR32:$Rt2),<br>
> (ins GPR64xsp0:$Rn),<br>
> - [], NoItinerary>;<br>
> + [], NoItinerary>,<br>
> + Sched<[WriteLd]>;<br>
><br>
> def _dword: A64I_LPexs_impl<0b11, opcode, asmstr,<br>
> (outs GPR64:$Rt, GPR64:$Rt2),<br>
> (ins GPR64xsp0:$Rn),<br>
> - [], NoItinerary>;<br>
> + [], NoItinerary>,<br>
> + Sched<[WriteLd]>;<br>
> }<br>
><br>
> defm LDXP : A64I_LPex<"ldxp", 0b010>;<br>
> @@ -3004,7 +3091,8 @@ multiclass A64I_LDRSTR_unsigned<string p<br>
> def _LDR : A64I_LSunsigimm<size, v, {high_opc, 0b1},<br>
> (outs GPR:$Rt), (ins GPR64xsp:$Rn, params.uimm12:$UImm12),<br>
> "ldr" # asmsuffix # "\t$Rt, [$Rn, $UImm12]",<br>
> - [], NoItinerary> {<br>
> + [], NoItinerary>,<br>
> + Sched<[WriteLd, ReadLd]> {<br>
> let mayLoad = 1;<br>
> }<br>
> def : InstAlias<"ldr" # asmsuffix # " $Rt, [$Rn]",<br>
> @@ -3016,13 +3104,15 @@ multiclass A64I_LDRSTR_unsigned<string p<br>
> (outs GPR:$Rt),<br>
> (ins GPR64xsp:$Rn, GPR32:$Rm, params.regextWm:$Ext),<br>
> "ldr" # asmsuffix # "\t$Rt, [$Rn, $Rm, $Ext]",<br>
> - [], NoItinerary>;<br>
> + [], NoItinerary>,<br>
> + Sched<[WriteLd, ReadLd, ReadLd]>;<br>
><br>
> def _Xm_RegOffset_LDR : A64I_LSregoff<size, v, {high_opc, 0b1}, 0b1,<br>
> (outs GPR:$Rt),<br>
> (ins GPR64xsp:$Rn, GPR64:$Rm, params.regextXm:$Ext),<br>
> "ldr" # asmsuffix # "\t$Rt, [$Rn, $Rm, $Ext]",<br>
> - [], NoItinerary>;<br>
> + [], NoItinerary>,<br>
> + Sched<[WriteLd, ReadLd, ReadLd]>;<br>
> }<br>
> def : InstAlias<"ldr" # asmsuffix # " $Rt, [$Rn, $Rm]",<br>
> (!cast<Instruction>(prefix # "_Xm_RegOffset_LDR") GPR:$Rt, GPR64xsp:$Rn,<br>
> @@ -3058,7 +3148,8 @@ multiclass A64I_LDRSTR_unsigned<string p<br>
> def _LDUR : A64I_LSunalimm<size, v, {high_opc, 0b1},<br>
> (outs GPR:$Rt), (ins GPR64xsp:$Rn, simm9:$SImm9),<br>
> "ldur" # asmsuffix # "\t$Rt, [$Rn, $SImm9]",<br>
> - [], NoItinerary> {<br>
> + [], NoItinerary>,<br>
> + Sched<[WriteLd, ReadLd]> {<br>
> let mayLoad = 1;<br>
> }<br>
> def : InstAlias<"ldur" # asmsuffix # " $Rt, [$Rn]",<br>
> @@ -3081,7 +3172,8 @@ multiclass A64I_LDRSTR_unsigned<string p<br>
> (outs GPR:$Rt, GPR64xsp:$Rn_wb),<br>
> (ins GPR64xsp:$Rn, simm9:$SImm9),<br>
> "ldr" # asmsuffix # "\t$Rt, [$Rn], $SImm9",<br>
> - [], NoItinerary> {<br>
> + [], NoItinerary>,<br>
> + Sched<[WriteLd, ReadLd]> {<br>
> let mayLoad = 1;<br>
> let Constraints = "$Rn = $Rn_wb";<br>
> let DecoderMethod = "DecodeSingleIndexedInstruction";<br>
> @@ -3104,7 +3196,8 @@ multiclass A64I_LDRSTR_unsigned<string p<br>
> (outs GPR:$Rt, GPR64xsp:$Rn_wb),<br>
> (ins GPR64xsp:$Rn, simm9:$SImm9),<br>
> "ldr" # asmsuffix # "\t$Rt, [$Rn, $SImm9]!",<br>
> - [], NoItinerary> {<br>
> + [], NoItinerary>,<br>
> + Sched<[WriteLd, ReadLd]> {<br>
> let mayLoad = 1;<br>
> let Constraints = "$Rn = $Rn_wb";<br>
> let DecoderMethod = "DecodeSingleIndexedInstruction";<br>
> @@ -3164,7 +3257,8 @@ multiclass A64I_LDR_signed<bits<2> size,<br>
> (outs GPR32:$Rt),<br>
> (ins GPR64xsp:$Rn, params.uimm12:$UImm12),<br>
> "ldrs" # asmopcode # "\t$Rt, [$Rn, $UImm12]",<br>
> - [], NoItinerary> {<br>
> + [], NoItinerary>,<br>
> + Sched<[WriteLd, ReadLd]> {<br>
> let mayLoad = 1;<br>
> }<br>
> def : InstAlias<"ldrs" # asmopcode # " $Rt, [$Rn]",<br>
> @@ -3174,7 +3268,8 @@ multiclass A64I_LDR_signed<bits<2> size,<br>
> (outs GPR64:$Rt),<br>
> (ins GPR64xsp:$Rn, params.uimm12:$UImm12),<br>
> "ldrs" # asmopcode # "\t$Rt, [$Rn, $UImm12]",<br>
> - [], NoItinerary> {<br>
> + [], NoItinerary>,<br>
> + Sched<[WriteLd, ReadLd]> {<br>
> let mayLoad = 1;<br>
> }<br>
> def : InstAlias<"ldrs" # asmopcode # " $Rt, [$Rn]",<br>
> @@ -3186,25 +3281,29 @@ multiclass A64I_LDR_signed<bits<2> size,<br>
> (outs GPR32:$Rt),<br>
> (ins GPR64xsp:$Rn, GPR32:$Rm, params.regextWm:$Ext),<br>
> "ldrs" # asmopcode # "\t$Rt, [$Rn, $Rm, $Ext]",<br>
> - [], NoItinerary>;<br>
> + [], NoItinerary>,<br>
> + Sched<[WriteLd, ReadLd, ReadLd]>;<br>
><br>
> def w_Xm_RegOffset : A64I_LSregoff<size, 0b0, 0b11, 0b1,<br>
> (outs GPR32:$Rt),<br>
> (ins GPR64xsp:$Rn, GPR64:$Rm, params.regextXm:$Ext),<br>
> "ldrs" # asmopcode # "\t$Rt, [$Rn, $Rm, $Ext]",<br>
> - [], NoItinerary>;<br>
> + [], NoItinerary>,<br>
> + Sched<[WriteLd, ReadLd, ReadLd]>;<br>
><br>
> def x_Wm_RegOffset : A64I_LSregoff<size, 0b0, 0b10, 0b0,<br>
> (outs GPR64:$Rt),<br>
> (ins GPR64xsp:$Rn, GPR32:$Rm, params.regextWm:$Ext),<br>
> "ldrs" # asmopcode # "\t$Rt, [$Rn, $Rm, $Ext]",<br>
> - [], NoItinerary>;<br>
> + [], NoItinerary>,<br>
> + Sched<[WriteLd, ReadLd, ReadLd]>;<br>
><br>
> def x_Xm_RegOffset : A64I_LSregoff<size, 0b0, 0b10, 0b1,<br>
> (outs GPR64:$Rt),<br>
> (ins GPR64xsp:$Rn, GPR64:$Rm, params.regextXm:$Ext),<br>
> "ldrs" # asmopcode # "\t$Rt, [$Rn, $Rm, $Ext]",<br>
> - [], NoItinerary>;<br>
> + [], NoItinerary>,<br>
> + Sched<[WriteLd, ReadLd, ReadLd]>;<br>
> }<br>
> def : InstAlias<"ldrs" # asmopcode # " $Rt, [$Rn, $Rm]",<br>
> (!cast<Instruction>(prefix # "w_Xm_RegOffset") GPR32:$Rt, GPR64xsp:$Rn,<br>
> @@ -3221,13 +3320,15 @@ multiclass A64I_LDR_signed<bits<2> size,<br>
> (outs GPR32:$Rt),<br>
> (ins GPR64xsp:$Rn, simm9:$SImm9),<br>
> "ldurs" # asmopcode # "\t$Rt, [$Rn, $SImm9]",<br>
> - [], NoItinerary>;<br>
> + [], NoItinerary>,<br>
> + Sched<[WriteLd, ReadLd]>;<br>
><br>
> def x_U : A64I_LSunalimm<size, 0b0, 0b10,<br>
> (outs GPR64:$Rt),<br>
> (ins GPR64xsp:$Rn, simm9:$SImm9),<br>
> "ldurs" # asmopcode # "\t$Rt, [$Rn, $SImm9]",<br>
> - [], NoItinerary>;<br>
> + [], NoItinerary>,<br>
> + Sched<[WriteLd, ReadLd]>;<br>
><br>
><br>
> // Post-indexed<br>
> @@ -3235,7 +3336,8 @@ multiclass A64I_LDR_signed<bits<2> size,<br>
> (outs GPR32:$Rt, GPR64xsp:$Rn_wb),<br>
> (ins GPR64xsp:$Rn, simm9:$SImm9),<br>
> "ldrs" # asmopcode # "\t$Rt, [$Rn], $SImm9",<br>
> - [], NoItinerary> {<br>
> + [], NoItinerary>,<br>
> + Sched<[WriteLd, ReadLd]> {<br>
> let Constraints = "$Rn = $Rn_wb";<br>
> let DecoderMethod = "DecodeSingleIndexedInstruction";<br>
> }<br>
> @@ -3244,7 +3346,8 @@ multiclass A64I_LDR_signed<bits<2> size,<br>
> (outs GPR64:$Rt, GPR64xsp:$Rn_wb),<br>
> (ins GPR64xsp:$Rn, simm9:$SImm9),<br>
> "ldrs" # asmopcode # "\t$Rt, [$Rn], $SImm9",<br>
> - [], NoItinerary> {<br>
> + [], NoItinerary>,<br>
> + Sched<[WriteLd, ReadLd]> {<br>
> let Constraints = "$Rn = $Rn_wb";<br>
> let DecoderMethod = "DecodeSingleIndexedInstruction";<br>
> }<br>
> @@ -3254,7 +3357,8 @@ multiclass A64I_LDR_signed<bits<2> size,<br>
> (outs GPR32:$Rt, GPR64xsp:$Rn_wb),<br>
> (ins GPR64xsp:$Rn, simm9:$SImm9),<br>
> "ldrs" # asmopcode # "\t$Rt, [$Rn, $SImm9]!",<br>
> - [], NoItinerary> {<br>
> + [], NoItinerary>,<br>
> + Sched<[WriteLd, ReadLd]> {<br>
> let Constraints = "$Rn = $Rn_wb";<br>
> let DecoderMethod = "DecodeSingleIndexedInstruction";<br>
> }<br>
> @@ -3263,7 +3367,8 @@ multiclass A64I_LDR_signed<bits<2> size,<br>
> (outs GPR64:$Rt, GPR64xsp:$Rn_wb),<br>
> (ins GPR64xsp:$Rn, simm9:$SImm9),<br>
> "ldrs" # asmopcode # "\t$Rt, [$Rn, $SImm9]!",<br>
> - [], NoItinerary> {<br>
> + [], NoItinerary>,<br>
> + Sched<[WriteLd, ReadLd]> {<br>
> let Constraints = "$Rn = $Rn_wb";<br>
> let DecoderMethod = "DecodeSingleIndexedInstruction";<br>
> }<br>
> @@ -3281,7 +3386,8 @@ def LDRSWx<br>
> (outs GPR64:$Rt),<br>
> (ins GPR64xsp:$Rn, word_uimm12:$UImm12),<br>
> "ldrsw\t$Rt, [$Rn, $UImm12]",<br>
> - [], NoItinerary> {<br>
> + [], NoItinerary>,<br>
> + Sched<[WriteLd, ReadLd]> {<br>
> let mayLoad = 1;<br>
> }<br>
> def : InstAlias<"ldrsw $Rt, [$Rn]", (LDRSWx GPR64:$Rt, GPR64xsp:$Rn, 0)>;<br>
> @@ -3291,13 +3397,15 @@ let mayLoad = 1 in {<br>
> (outs GPR64:$Rt),<br>
> (ins GPR64xsp:$Rn, GPR32:$Rm, word_Wm_regext:$Ext),<br>
> "ldrsw\t$Rt, [$Rn, $Rm, $Ext]",<br>
> - [], NoItinerary>;<br>
> + [], NoItinerary>,<br>
> + Sched<[WriteLd, ReadLd, ReadLd]>;<br>
><br>
> def LDRSWx_Xm_RegOffset : A64I_LSregoff<0b10, 0b0, 0b10, 0b1,<br>
> (outs GPR64:$Rt),<br>
> (ins GPR64xsp:$Rn, GPR64:$Rm, word_Xm_regext:$Ext),<br>
> "ldrsw\t$Rt, [$Rn, $Rm, $Ext]",<br>
> - [], NoItinerary>;<br>
> + [], NoItinerary>,<br>
> + Sched<[WriteLd, ReadLd, ReadLd]>;<br>
> }<br>
> def : InstAlias<"ldrsw $Rt, [$Rn, $Rm]",<br>
> (LDRSWx_Xm_RegOffset GPR64:$Rt, GPR64xsp:$Rn, GPR64:$Rm, 2)>;<br>
> @@ -3308,7 +3416,8 @@ def LDURSWx<br>
> (outs GPR64:$Rt),<br>
> (ins GPR64xsp:$Rn, simm9:$SImm9),<br>
> "ldursw\t$Rt, [$Rn, $SImm9]",<br>
> - [], NoItinerary> {<br>
> + [], NoItinerary>,<br>
> + Sched<[WriteLd, ReadLd]> {<br>
> let mayLoad = 1;<br>
> }<br>
> def : InstAlias<"ldursw $Rt, [$Rn]", (LDURSWx GPR64:$Rt, GPR64xsp:$Rn, 0)>;<br>
> @@ -3318,7 +3427,8 @@ def LDRSWx_PostInd<br>
> (outs GPR64:$Rt, GPR64xsp:$Rn_wb),<br>
> (ins GPR64xsp:$Rn, simm9:$SImm9),<br>
> "ldrsw\t$Rt, [$Rn], $SImm9",<br>
> - [], NoItinerary> {<br>
> + [], NoItinerary>,<br>
> + Sched<[WriteLd, ReadLd]> {<br>
> let mayLoad = 1;<br>
> let Constraints = "$Rn = $Rn_wb";<br>
> let DecoderMethod = "DecodeSingleIndexedInstruction";<br>
> @@ -3328,7 +3438,8 @@ def LDRSWx_PreInd : A64I_LSpreind<0b10,<br>
> (outs GPR64:$Rt, GPR64xsp:$Rn_wb),<br>
> (ins GPR64xsp:$Rn, simm9:$SImm9),<br>
> "ldrsw\t$Rt, [$Rn, $SImm9]!",<br>
> - [], NoItinerary> {<br>
> + [], NoItinerary>,<br>
> + Sched<[WriteLd, ReadLd]> {<br>
> let mayLoad = 1;<br>
> let Constraints = "$Rn = $Rn_wb";<br>
> let DecoderMethod = "DecodeSingleIndexedInstruction";<br>
> @@ -3341,7 +3452,8 @@ def LDRSWx_PreInd : A64I_LSpreind<0b10,<br>
> def PRFM : A64I_LSunsigimm<0b11, 0b0, 0b10, (outs),<br>
> (ins prefetch_op:$Rt, GPR64xsp:$Rn, dword_uimm12:$UImm12),<br>
> "prfm\t$Rt, [$Rn, $UImm12]",<br>
> - [], NoItinerary> {<br>
> + [], NoItinerary>,<br>
> + Sched<[WritePreLd, ReadPreLd]> {<br>
> let mayLoad = 1;<br>
> }<br>
> def : InstAlias<"prfm $Rt, [$Rn]",<br>
> @@ -3352,12 +3464,14 @@ let mayLoad = 1 in {<br>
> (ins prefetch_op:$Rt, GPR64xsp:$Rn,<br>
> GPR32:$Rm, dword_Wm_regext:$Ext),<br>
> "prfm\t$Rt, [$Rn, $Rm, $Ext]",<br>
> - [], NoItinerary>;<br>
> + [], NoItinerary>,<br>
> + Sched<[WritePreLd, ReadPreLd]>;<br>
> def PRFM_Xm_RegOffset : A64I_LSregoff<0b11, 0b0, 0b10, 0b1, (outs),<br>
> (ins prefetch_op:$Rt, GPR64xsp:$Rn,<br>
> GPR64:$Rm, dword_Xm_regext:$Ext),<br>
> "prfm\t$Rt, [$Rn, $Rm, $Ext]",<br>
> - [], NoItinerary>;<br>
> + [], NoItinerary>,<br>
> + Sched<[WritePreLd, ReadPreLd]>;<br>
> }<br>
><br>
> def : InstAlias<"prfm $Rt, [$Rn, $Rm]",<br>
> @@ -3368,7 +3482,8 @@ def : InstAlias<"prfm $Rt, [$Rn, $Rm]",<br>
> def PRFUM : A64I_LSunalimm<0b11, 0b0, 0b10, (outs),<br>
> (ins prefetch_op:$Rt, GPR64xsp:$Rn, simm9:$SImm9),<br>
> "prfum\t$Rt, [$Rn, $SImm9]",<br>
> - [], NoItinerary> {<br>
> + [], NoItinerary>,<br>
> + Sched<[WritePreLd, ReadPreLd]> {<br>
> let mayLoad = 1;<br>
> }<br>
> def : InstAlias<"prfum $Rt, [$Rn]",<br>
> @@ -3388,7 +3503,8 @@ multiclass A64I_LDTRSTTR<bits<2> size, s<br>
> def _UnPriv_STR : A64I_LSunpriv<size, 0b0, 0b00,<br>
> (outs), (ins GPR:$Rt, GPR64xsp:$Rn, simm9:$SImm9),<br>
> "sttr" # asmsuffix # "\t$Rt, [$Rn, $SImm9]",<br>
> - [], NoItinerary> {<br>
> + [], NoItinerary>,<br>
> + Sched<[WriteLd, ReadLd]> {<br>
> let mayStore = 1;<br>
> }<br>
><br>
> @@ -3398,7 +3514,8 @@ multiclass A64I_LDTRSTTR<bits<2> size, s<br>
> def _UnPriv_LDR : A64I_LSunpriv<size, 0b0, 0b01,<br>
> (outs GPR:$Rt), (ins GPR64xsp:$Rn, simm9:$SImm9),<br>
> "ldtr" # asmsuffix # "\t$Rt, [$Rn, $SImm9]",<br>
> - [], NoItinerary> {<br>
> + [], NoItinerary>,<br>
> + Sched<[WriteLd, ReadLd]> {<br>
> let mayLoad = 1;<br>
> }<br>
><br>
> @@ -3427,13 +3544,15 @@ multiclass A64I_LDTR_signed<bits<2> size<br>
> (outs GPR32:$Rt),<br>
> (ins GPR64xsp:$Rn, simm9:$SImm9),<br>
> "ldtrs" # asmopcode # "\t$Rt, [$Rn, $SImm9]",<br>
> - [], NoItinerary>;<br>
> + [], NoItinerary>,<br>
> + Sched<[WriteLd, ReadLd]>;<br>
><br>
> def x : A64I_LSunpriv<size, 0b0, 0b10,<br>
> (outs GPR64:$Rt),<br>
> (ins GPR64xsp:$Rn, simm9:$SImm9),<br>
> "ldtrs" # asmopcode # "\t$Rt, [$Rn, $SImm9]",<br>
> - [], NoItinerary>;<br>
> + [], NoItinerary>,<br>
> + Sched<[WriteLd, ReadLd]>;<br>
> }<br>
><br>
> def : InstAlias<"ldtrs" # asmopcode # " $Rt, [$Rn]",<br>
> @@ -3454,7 +3573,8 @@ def LDTRSWx : A64I_LSunpriv<0b10, 0b0, 0<br>
> (outs GPR64:$Rt),<br>
> (ins GPR64xsp:$Rn, simm9:$SImm9),<br>
> "ldtrsw\t$Rt, [$Rn, $SImm9]",<br>
> - [], NoItinerary> {<br>
> + [], NoItinerary>,<br>
> + Sched<[WriteLd, ReadLd]> {<br>
> let mayLoad = 1;<br>
> }<br>
> def : InstAlias<"ldtrsw $Rt, [$Rn]", (LDTRSWx GPR64:$Rt, GPR64xsp:$Rn, 0)>;<br>
> @@ -3516,7 +3636,8 @@ multiclass A64I_LSPsimple<bits<2> opc, b<br>
> Operand simm7, string prefix> {<br>
> def _STR : A64I_LSPoffset<opc, v, 0b0, (outs),<br>
> (ins SomeReg:$Rt, SomeReg:$Rt2, GPR64xsp:$Rn, simm7:$SImm7),<br>
> - "stp\t$Rt, $Rt2, [$Rn, $SImm7]", [], NoItinerary> {<br>
> + "stp\t$Rt, $Rt2, [$Rn, $SImm7]", [], NoItinerary>,<br>
> + Sched<[WriteLd, ReadLd]> {<br>
> let mayStore = 1;<br>
> let DecoderMethod = "DecodeLDSTPairInstruction";<br>
> }<br>
> @@ -3527,7 +3648,8 @@ multiclass A64I_LSPsimple<bits<2> opc, b<br>
> def _LDR : A64I_LSPoffset<opc, v, 0b1,<br>
> (outs SomeReg:$Rt, SomeReg:$Rt2),<br>
> (ins GPR64xsp:$Rn, simm7:$SImm7),<br>
> - "ldp\t$Rt, $Rt2, [$Rn, $SImm7]", [], NoItinerary> {<br>
> + "ldp\t$Rt, $Rt2, [$Rn, $SImm7]", [], NoItinerary>,<br>
> + Sched<[WriteLd, ReadLd]> {<br>
> let mayLoad = 1;<br>
> let DecoderMethod = "DecodeLDSTPairInstruction";<br>
> }<br>
> @@ -3553,7 +3675,8 @@ multiclass A64I_LSPsimple<bits<2> opc, b<br>
> (outs SomeReg:$Rt, SomeReg:$Rt2, GPR64xsp:$Rn_wb),<br>
> (ins GPR64xsp:$Rn, simm7:$SImm7),<br>
> "ldp\t$Rt, $Rt2, [$Rn], $SImm7",<br>
> - [], NoItinerary> {<br>
> + [], NoItinerary>,<br>
> + Sched<[WriteLd, ReadLd]> {<br>
> let mayLoad = 1;<br>
> let Constraints = "$Rn = $Rn_wb";<br>
> let DecoderMethod = "DecodeLDSTPairInstruction";<br>
> @@ -3572,7 +3695,8 @@ multiclass A64I_LSPsimple<bits<2> opc, b<br>
> (outs SomeReg:$Rt, SomeReg:$Rt2, GPR64xsp:$Rn_wb),<br>
> (ins GPR64xsp:$Rn, simm7:$SImm7),<br>
> "ldp\t$Rt, $Rt2, [$Rn, $SImm7]!",<br>
> - [], NoItinerary> {<br>
> + [], NoItinerary>,<br>
> + Sched<[WriteLd, ReadLd]> {<br>
> let mayLoad = 1;<br>
> let Constraints = "$Rn = $Rn_wb";<br>
> let DecoderMethod = "DecodeLDSTPairInstruction";<br>
> @@ -3591,7 +3715,8 @@ multiclass A64I_LSPsimple<bits<2> opc, b<br>
> def _NonTemp_LDR : A64I_LSPnontemp<opc, v, 0b1,<br>
> (outs SomeReg:$Rt, SomeReg:$Rt2),<br>
> (ins GPR64xsp:$Rn, simm7:$SImm7),<br>
> - "ldnp\t$Rt, $Rt2, [$Rn, $SImm7]", [], NoItinerary> {<br>
> + "ldnp\t$Rt, $Rt2, [$Rn, $SImm7]", [], NoItinerary>,<br>
> + Sched<[WriteLd, ReadLd]> {<br>
> let mayLoad = 1;<br>
> let DecoderMethod = "DecodeLDSTPairInstruction";<br>
> }<br>
> @@ -3616,7 +3741,8 @@ defm LSFPPair128 : A64I_LSPsimple<0b10,<br>
> def LDPSWx : A64I_LSPoffset<0b01, 0b0, 0b1,<br>
> (outs GPR64:$Rt, GPR64:$Rt2),<br>
> (ins GPR64xsp:$Rn, word_simm7:$SImm7),<br>
> - "ldpsw\t$Rt, $Rt2, [$Rn, $SImm7]", [], NoItinerary> {<br>
> + "ldpsw\t$Rt, $Rt2, [$Rn, $SImm7]", [], NoItinerary>,<br>
> + Sched<[WriteLd, ReadLd]> {<br>
> let mayLoad = 1;<br>
> let DecoderMethod = "DecodeLDSTPairInstruction";<br>
> }<br>
> @@ -3637,7 +3763,8 @@ def LDPSWx_PreInd : A64I_LSPpreind<0b01,<br>
> (outs GPR64:$Rt, GPR64:$Rt2, GPR64:$Rn_wb),<br>
> (ins GPR64xsp:$Rn, word_simm7:$SImm7),<br>
> "ldpsw\t$Rt, $Rt2, [$Rn, $SImm7]!",<br>
> - [], NoItinerary> {<br>
> + [], NoItinerary>,<br>
> + Sched<[WriteLd, ReadLd]> {<br>
> let mayLoad = 1;<br>
> let Constraints = "$Rn = $Rn_wb";<br>
> let DecoderMethod = "DecodeLDSTPairInstruction";<br>
> @@ -3682,14 +3809,16 @@ multiclass A64I_logimmSizes<bits<2> opc,<br>
> !strconcat(asmop, "\t$Rd, $Rn, $Imm"),<br>
> [(set i32:$Rd,<br>
> (opnode i32:$Rn, logical_imm32_operand:$Imm))],<br>
> - NoItinerary>;<br>
> + NoItinerary>,<br>
> + Sched<[WriteALU, ReadALU]>;<br>
><br>
> def xxi : A64I_logicalimm<0b1, opc, (outs GPR64xsp:$Rd),<br>
> (ins GPR64:$Rn, logical_imm64_operand:$Imm),<br>
> !strconcat(asmop, "\t$Rd, $Rn, $Imm"),<br>
> [(set i64:$Rd,<br>
> (opnode i64:$Rn, logical_imm64_operand:$Imm))],<br>
> - NoItinerary>;<br>
> + NoItinerary>,<br>
> + Sched<[WriteALU, ReadALU]>;<br>
> }<br>
><br>
> defm AND : A64I_logimmSizes<0b00, "and", and>;<br>
> @@ -3700,12 +3829,14 @@ let Defs = [NZCV] in {<br>
> def ANDSwwi : A64I_logicalimm<0b0, 0b11, (outs GPR32:$Rd),<br>
> (ins GPR32:$Rn, logical_imm32_operand:$Imm),<br>
> "ands\t$Rd, $Rn, $Imm",<br>
> - [], NoItinerary>;<br>
> + [], NoItinerary>,<br>
> + Sched<[WriteALU, ReadALU]>;<br>
><br>
> def ANDSxxi : A64I_logicalimm<0b1, 0b11, (outs GPR64:$Rd),<br>
> (ins GPR64:$Rn, logical_imm64_operand:$Imm),<br>
> "ands\t$Rd, $Rn, $Imm",<br>
> - [], NoItinerary>;<br>
> + [], NoItinerary>,<br>
> + Sched<[WriteALU, ReadALU]>;<br>
> }<br>
><br>
><br>
> @@ -3750,7 +3881,8 @@ multiclass logical_shifts<string prefix,<br>
> [(set ty:$Rd, (opfrag ty:$Rn, (shl ty:$Rm,<br>
> !cast<Operand>("lsl_operand_" # ty):$Imm6))<br>
> )],<br>
> - NoItinerary>;<br>
> + NoItinerary>,<br>
> + Sched<[WriteALU, ReadALU, ReadALU]>;<br>
><br>
> def _lsr : A64I_logicalshift<sf, opc, 0b01, N,<br>
> (outs GPR:$Rd),<br>
> @@ -3760,7 +3892,8 @@ multiclass logical_shifts<string prefix,<br>
> [(set ty:$Rd, (opfrag ty:$Rn, (srl ty:$Rm,<br>
> !cast<Operand>("lsr_operand_" # ty):$Imm6))<br>
> )],<br>
> - NoItinerary>;<br>
> + NoItinerary>,<br>
> + Sched<[WriteALU, ReadALU, ReadALU]>;<br>
><br>
> def _asr : A64I_logicalshift<sf, opc, 0b10, N,<br>
> (outs GPR:$Rd),<br>
> @@ -3770,7 +3903,8 @@ multiclass logical_shifts<string prefix,<br>
> [(set ty:$Rd, (opfrag ty:$Rn, (sra ty:$Rm,<br>
> !cast<Operand>("asr_operand_" # ty):$Imm6))<br>
> )],<br>
> - NoItinerary>;<br>
> + NoItinerary>,<br>
> + Sched<[WriteALU, ReadALU, ReadALU]>;<br>
><br>
> def _ror : A64I_logicalshift<sf, opc, 0b11, N,<br>
> (outs GPR:$Rd),<br>
> @@ -3780,7 +3914,8 @@ multiclass logical_shifts<string prefix,<br>
> [(set ty:$Rd, (opfrag ty:$Rn, (rotr ty:$Rm,<br>
> !cast<Operand>("ror_operand_" # ty):$Imm6))<br>
> )],<br>
> - NoItinerary>;<br>
> + NoItinerary>,<br>
> + Sched<[WriteALU, ReadALU, ReadALU]>;<br>
> }<br>
><br>
> def _noshift<br>
> @@ -3835,7 +3970,8 @@ multiclass tst_shifts<string prefix, bit<br>
> [(set NZCV, (A64setcc (and ty:$Rn, (shl ty:$Rm,<br>
> !cast<Operand>("lsl_operand_" # ty):$Imm6)),<br>
> 0, signed_cond))],<br>
> - NoItinerary>;<br>
> + NoItinerary>,<br>
> + Sched<[WriteALU, ReadALU, ReadALU]>;<br>
><br>
><br>
> def _lsr : A64I_logicalshift<sf, 0b11, 0b01, 0b0,<br>
> @@ -3846,7 +3982,8 @@ multiclass tst_shifts<string prefix, bit<br>
> [(set NZCV, (A64setcc (and ty:$Rn, (srl ty:$Rm,<br>
> !cast<Operand>("lsr_operand_" # ty):$Imm6)),<br>
> 0, signed_cond))],<br>
> - NoItinerary>;<br>
> + NoItinerary>,<br>
> + Sched<[WriteALU, ReadALU, ReadALU]>;<br>
><br>
> def _asr : A64I_logicalshift<sf, 0b11, 0b10, 0b0,<br>
> (outs),<br>
> @@ -3856,7 +3993,8 @@ multiclass tst_shifts<string prefix, bit<br>
> [(set NZCV, (A64setcc (and ty:$Rn, (sra ty:$Rm,<br>
> !cast<Operand>("asr_operand_" # ty):$Imm6)),<br>
> 0, signed_cond))],<br>
> - NoItinerary>;<br>
> + NoItinerary>,<br>
> + Sched<[WriteALU, ReadALU, ReadALU]>;<br>
><br>
> def _ror : A64I_logicalshift<sf, 0b11, 0b11, 0b0,<br>
> (outs),<br>
> @@ -3866,7 +4004,8 @@ multiclass tst_shifts<string prefix, bit<br>
> [(set NZCV, (A64setcc (and ty:$Rn, (rotr ty:$Rm,<br>
> !cast<Operand>("ror_operand_" # ty):$Imm6)),<br>
> 0, signed_cond))],<br>
> - NoItinerary>;<br>
> + NoItinerary>,<br>
> + Sched<[WriteALU, ReadALU, ReadALU]>;<br>
> }<br>
><br>
> def _noshift : InstAlias<"tst $Rn, $Rm",<br>
> @@ -3889,7 +4028,8 @@ multiclass mvn_shifts<string prefix, bit<br>
> "mvn\t$Rd, $Rm, $Imm6",<br>
> [(set ty:$Rd, (not (shl ty:$Rm,<br>
> !cast<Operand>("lsl_operand_" # ty):$Imm6)))],<br>
> - NoItinerary>;<br>
> + NoItinerary>,<br>
> + Sched<[WriteALU, ReadALU, ReadALU]>;<br>
><br>
><br>
> def _lsr : A64I_logicalshift<sf, 0b01, 0b01, 0b1,<br>
> @@ -3899,7 +4039,8 @@ multiclass mvn_shifts<string prefix, bit<br>
> "mvn\t$Rd, $Rm, $Imm6",<br>
> [(set ty:$Rd, (not (srl ty:$Rm,<br>
> !cast<Operand>("lsr_operand_" # ty):$Imm6)))],<br>
> - NoItinerary>;<br>
> + NoItinerary>,<br>
> + Sched<[WriteALU, ReadALU, ReadALU]>;<br>
><br>
> def _asr : A64I_logicalshift<sf, 0b01, 0b10, 0b1,<br>
> (outs GPR:$Rd),<br>
> @@ -3908,7 +4049,8 @@ multiclass mvn_shifts<string prefix, bit<br>
> "mvn\t$Rd, $Rm, $Imm6",<br>
> [(set ty:$Rd, (not (sra ty:$Rm,<br>
> !cast<Operand>("asr_operand_" # ty):$Imm6)))],<br>
> - NoItinerary>;<br>
> + NoItinerary>,<br>
> + Sched<[WriteALU, ReadALU, ReadALU]>;<br>
><br>
> def _ror : A64I_logicalshift<sf, 0b01, 0b11, 0b1,<br>
> (outs GPR:$Rd),<br>
> @@ -3917,7 +4059,8 @@ multiclass mvn_shifts<string prefix, bit<br>
> "mvn\t$Rd, $Rm, $Imm6",<br>
> [(set ty:$Rd, (not (rotr ty:$Rm,<br>
> !cast<Operand>("lsl_operand_" # ty):$Imm6)))],<br>
> - NoItinerary>;<br>
> + NoItinerary>,<br>
> + Sched<[WriteALU, ReadALU, ReadALU]>;<br>
> }<br>
><br>
> def _noshift : InstAlias<"mvn $Rn, $Rm",<br>
> @@ -3972,7 +4115,8 @@ multiclass A64I_movwSizes<bits<2> opc, s<br>
><br>
> def wii : A64I_movw<0b0, opc, (outs GPR32:$Rd), ins32bit,<br>
> !strconcat(asmop, "\t$Rd, $FullImm"),<br>
> - [], NoItinerary> {<br>
> + [], NoItinerary>,<br>
> + Sched<[WriteALU]> {<br>
> bits<18> FullImm;<br>
> let UImm16 = FullImm{15-0};<br>
> let Shift = FullImm{17-16};<br>
> @@ -3980,7 +4124,8 @@ multiclass A64I_movwSizes<bits<2> opc, s<br>
><br>
> def xii : A64I_movw<0b1, opc, (outs GPR64:$Rd), ins64bit,<br>
> !strconcat(asmop, "\t$Rd, $FullImm"),<br>
> - [], NoItinerary> {<br>
> + [], NoItinerary>,<br>
> + Sched<[WriteALU]> {<br>
> bits<18> FullImm;<br>
> let UImm16 = FullImm{15-0};<br>
> let Shift = FullImm{17-16};<br>
> @@ -4088,10 +4233,12 @@ def adrp_label : Operand<i64> {<br>
><br>
> let hasSideEffects = 0 in {<br>
> def ADRxi : A64I_PCADR<0b0, (outs GPR64:$Rd), (ins adr_label:$Label),<br>
> - "adr\t$Rd, $Label", [], NoItinerary>;<br>
> + "adr\t$Rd, $Label", [], NoItinerary>,<br>
> + Sched<[WriteALUs]>;<br>
><br>
> def ADRPxi : A64I_PCADR<0b1, (outs GPR64:$Rd), (ins adrp_label:$Label),<br>
> - "adrp\t$Rd, $Label", [], NoItinerary>;<br>
> + "adrp\t$Rd, $Label", [], NoItinerary>,<br>
> + Sched<[WriteALUs]>;<br>
> }<br>
><br>
> //===----------------------------------------------------------------------===//<br>
> @@ -4377,14 +4524,16 @@ let isBranch = 1, isTerminator = 1 in {<br>
> "tbz\t$Rt, $Imm, $Label",<br>
> [(A64br_cc (A64cmp (and i64:$Rt, tstb64_pat:$Imm), 0),<br>
> A64eq, bb:$Label)],<br>
> - NoItinerary>;<br>
> + NoItinerary>,<br>
> + Sched<[WriteBr]>;<br>
><br>
> def TBNZxii : A64I_TBimm<0b1, (outs),<br>
> (ins GPR64:$Rt, uimm6:$Imm, tbimm_target:$Label),<br>
> "tbnz\t$Rt, $Imm, $Label",<br>
> [(A64br_cc (A64cmp (and i64:$Rt, tstb64_pat:$Imm), 0),<br>
> A64ne, bb:$Label)],<br>
> - NoItinerary>;<br>
> + NoItinerary>,<br>
> + Sched<[WriteBr]>;<br>
><br>
><br>
> // Note, these instructions overlap with the above 64-bit patterns. This is<br>
> @@ -4396,7 +4545,8 @@ let isBranch = 1, isTerminator = 1 in {<br>
> "tbz\t$Rt, $Imm, $Label",<br>
> [(A64br_cc (A64cmp (and i32:$Rt, tstb32_pat:$Imm), 0),<br>
> A64eq, bb:$Label)],<br>
> - NoItinerary> {<br>
> + NoItinerary>,<br>
> + Sched<[WriteBr]> {<br>
> let Imm{5} = 0b0;<br>
> }<br>
><br>
> @@ -4405,7 +4555,8 @@ let isBranch = 1, isTerminator = 1 in {<br>
> "tbnz\t$Rt, $Imm, $Label",<br>
> [(A64br_cc (A64cmp (and i32:$Rt, tstb32_pat:$Imm), 0),<br>
> A64ne, bb:$Label)],<br>
> - NoItinerary> {<br>
> + NoItinerary>,<br>
> + Sched<[WriteBr]> {<br>
> let Imm{5} = 0b0;<br>
> }<br>
> }<br>
> @@ -4440,7 +4591,8 @@ def blimm_target : Operand<i64> {<br>
> class A64I_BimmImpl<bit op, string asmop, list<dag> patterns, Operand lbl_type><br>
> : A64I_Bimm<op, (outs), (ins lbl_type:$Label),<br>
> !strconcat(asmop, "\t$Label"), patterns,<br>
> - NoItinerary>;<br>
> + NoItinerary>,<br>
> + Sched<[WriteBr]>;<br>
><br>
> let isBranch = 1 in {<br>
> def Bimm : A64I_BimmImpl<0b0, "b", [(br bb:$Label)], bimm_target> {<br>
> @@ -4448,10 +4600,12 @@ let isBranch = 1 in {<br>
> let isBarrier = 1;<br>
> }<br>
><br>
> - def BLimm : A64I_BimmImpl<0b1, "bl",<br>
> - [(AArch64Call tglobaladdr:$Label)], blimm_target> {<br>
> - let isCall = 1;<br>
> - let Defs = [X30];<br>
> + let SchedRW = [WriteBrL] in {<br>
> + def BLimm : A64I_BimmImpl<0b1, "bl",<br>
> + [(AArch64Call tglobaladdr:$Label)], blimm_target> {<br>
> + let isCall = 1;<br>
> + let Defs = [X30];<br>
> + }<br>
> }<br>
> }<br>
><br>
> @@ -4468,7 +4622,8 @@ class A64I_BregImpl<bits<4> opc,<br>
> dag outs, dag ins, string asmstr, list<dag> patterns,<br>
> InstrItinClass itin = NoItinerary><br>
> : A64I_Breg<opc, 0b11111, 0b000000, 0b00000,<br>
> - outs, ins, asmstr, patterns, itin> {<br>
> + outs, ins, asmstr, patterns, itin>,<br>
> + Sched<[WriteBr]> {<br>
> let isBranch = 1;<br>
> let isIndirectBranch = 1;<br>
> }<br>
> @@ -4484,11 +4639,13 @@ let isBranch = 1 in {<br>
> let isTerminator = 1;<br>
> }<br>
><br>
> - def BLRx : A64I_BregImpl<0b0001, (outs), (ins GPR64:$Rn),<br>
> - "blr\t$Rn", [(AArch64Call i64:$Rn)]> {<br>
> - let isBarrier = 0;<br>
> - let isCall = 1;<br>
> - let Defs = [X30];<br>
> + let SchedRW = [WriteBrL] in {<br>
> + def BLRx : A64I_BregImpl<0b0001, (outs), (ins GPR64:$Rn),<br>
> + "blr\t$Rn", [(AArch64Call i64:$Rn)]> {<br>
> + let isBarrier = 0;<br>
> + let isCall = 1;<br>
> + let Defs = [X30];<br>
> + }<br>
> }<br>
><br>
> def RETx : A64I_BregImpl<0b0010, (outs), (ins GPR64:$Rn),<br>
><br>
> Modified: llvm/trunk/lib/Target/AArch64/AArch64Schedule.td<br>
> URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64Schedule.td?rev=203125&r1=203124&r2=203125&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64Schedule.td?rev=203125&r1=203124&r2=203125&view=diff</a><br>
> ==============================================================================<br>
> --- llvm/trunk/lib/Target/AArch64/AArch64Schedule.td (original)<br>
> +++ llvm/trunk/lib/Target/AArch64/AArch64Schedule.td Thu Mar 6 10:04:00 2014<br>
> @@ -7,4 +7,66 @@<br>
> //<br>
> //===----------------------------------------------------------------------===//<br>
><br>
> +//===----------------------------------------------------------------------===//<br>
> +// Generic processor itineraries for legacy compatibility.<br>
> +<br>
> def GenericItineraries : ProcessorItineraries<[], [], []>;<br>
> +<br>
> +<br>
> +//===----------------------------------------------------------------------===//<br>
> +// Base SchedReadWrite types<br>
> +<br>
> +// Basic ALU<br>
> +def WriteALU : SchedWrite; // Generic: may contain shift and/or ALU operation<br>
> +def WriteALUs : SchedWrite; // Shift only with no ALU operation<br>
> +def ReadALU : SchedRead; // Operand not needed for shifting<br>
> +def ReadALUs : SchedRead; // Operand needed for shifting<br>
> +<br>
> +// Multiply with optional accumulate<br>
> +def WriteMAC : SchedWrite;<br>
> +def ReadMAC : SchedRead;<br>
> +<br>
> +// Compares<br>
> +def WriteCMP : SchedWrite;<br>
> +def ReadCMP : SchedRead;<br>
> +<br>
> +// Division<br>
> +def WriteDiv : SchedWrite;<br>
> +def ReadDiv : SchedRead;<br>
> +<br>
> +// Loads<br>
> +def WriteLd : SchedWrite;<br>
> +def WritePreLd : SchedWrite;<br>
> +def ReadLd : SchedRead;<br>
> +def ReadPreLd : SchedRead;<br>
> +<br>
> +// Branches<br>
> +def WriteBr : SchedWrite;<br>
> +def WriteBrL : SchedWrite;<br>
> +def ReadBr : SchedRead;<br>
> +<br>
> +// Floating Point ALU<br>
> +def WriteFPALU : SchedWrite;<br>
> +def ReadFPALU : SchedRead;<br>
> +<br>
> +// Floating Point MAC, Mul, Div, Sqrt<br>
> +// Most processors will simply send all of these down a dedicated pipe, but<br>
> +// they're explicitly seperated here for flexibility of modeling later. May<br>
> +// consider consolidating them into a single WriteFPXXXX type in the future.<br>
> +def WriteFPMAC : SchedWrite;<br>
> +def WriteFPMul : SchedWrite;<br>
> +def WriteFPDiv : SchedWrite;<br>
> +def WriteFPSqrt : SchedWrite;<br>
> +def ReadFPMAC : SchedRead;<br>
> +def ReadFPMul : SchedRead;<br>
> +def ReadFPDiv : SchedRead;<br>
> +def ReadFPSqrt : SchedRead;<br>
> +<br>
> +// Noop<br>
> +def WriteNoop : SchedWrite;<br>
> +<br>
> +<br>
> +//===----------------------------------------------------------------------===//<br>
> +// Subtarget specific Machine Models.<br>
> +<br>
> +include "AArch64ScheduleA53.td"<br>
><br>
> Added: llvm/trunk/lib/Target/AArch64/AArch64ScheduleA53.td<br>
> URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64ScheduleA53.td?rev=203125&view=auto" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64ScheduleA53.td?rev=203125&view=auto</a><br>
> ==============================================================================<br>
> --- llvm/trunk/lib/Target/AArch64/AArch64ScheduleA53.td (added)<br>
> +++ llvm/trunk/lib/Target/AArch64/AArch64ScheduleA53.td Thu Mar 6 10:04:00 2014<br>
> @@ -0,0 +1,130 @@<br>
> +//=- AArch64ScheduleA53.td - ARM Cortex-A53 Scheduling Definitions -*- tablegen -*-=//<br>
> +//<br>
> +// The LLVM Compiler Infrastructure<br>
> +//<br>
> +// This file is distributed under the University of Illinois Open Source<br>
> +// License. See LICENSE.TXT for details.<br>
> +//<br>
> +//===----------------------------------------------------------------------===//<br>
> +//<br>
> +// This file defines the itinerary class data for the ARM Cortex A53 processors.<br>
> +//<br>
> +//===----------------------------------------------------------------------===//<br>
> +<br>
> +// ===---------------------------------------------------------------------===//<br>
> +// The following definitions describe the simpler per-operand machine model.<br>
> +// This works with MachineScheduler. See MCSchedModel.h for details.<br>
> +<br>
> +// Cortex-A53 machine model for scheduling and other instruction cost heuristics.<br>
> +def CortexA53Model : SchedMachineModel {<br>
> + let IssueWidth = 2; // 2 micro-ops are dispatched per cycle.<br>
> + let MinLatency = 1 ; // OperandCycles are interpreted as MinLatency.<br>
> + let LoadLatency = 2; // Optimistic load latency assuming bypass.<br>
> + // This is overriden by OperandCycles if the<br>
> + // Itineraries are queried instead.<br>
> + let MispredictPenalty = 9; // Based on "Cortex-A53 Software Optimisation<br>
> + // Specification - Instruction Timings"<br>
> + // v 1.0 Spreadsheet<br>
> +}<br>
> +<br>
> +<br>
> +//===----------------------------------------------------------------------===//<br>
> +// Define each kind of processor resource and number available.<br>
> +<br>
> +// Modeling each pipeline as a ProcResource using the default BufferSize = -1.<br>
> +// Cortex-A53 is in-order and therefore should be using BufferSize = 0. The<br>
> +// current configuration performs better with the basic latencies provided so<br>
> +// far. Will revisit BufferSize once the latency information is more accurate.<br>
> +<br>
> +let SchedModel = CortexA53Model in {<br>
> +<br>
> +def A53UnitALU : ProcResource<2>; // Int ALU<br>
> +def A53UnitMAC : ProcResource<1>; // Int MAC<br>
> +def A53UnitDiv : ProcResource<1>; // Int Division<br>
> +def A53UnitLdSt : ProcResource<1>; // Load/Store<br>
> +def A53UnitB : ProcResource<1>; // Branch<br>
> +def A53UnitFPALU : ProcResource<1>; // FP ALU<br>
> +def A53UnitFPMDS : ProcResource<1>; // FP Mult/Div/Sqrt<br>
> +<br>
> +<br>
> +//===----------------------------------------------------------------------===//<br>
> +// Subtarget-specific SchedWrite types which both map the ProcResources and<br>
> +// set the latency.<br>
> +<br>
> +// Issue - Every instruction must consume an A53WriteIssue. Optionally,<br>
> +// instructions that cannot be dual-issued will also include the<br>
> +// A53WriteIssue2nd in their SchedRW list. That second WriteRes will<br>
> +// ensure that a second issue slot is consumed.<br>
> +def A53WriteIssue : SchedWriteRes<[]>;<br>
> +def A53WriteIssue2nd : SchedWriteRes<[]> { let Latency = 0; }<br>
> +<br>
> +// ALU - These are reduced to 1 despite a true latency of 4 in order to easily<br>
> +// model forwarding logic. Once forwarding is properly modelled, then<br>
> +// they'll be corrected.<br>
> +def : WriteRes<WriteALU, [A53UnitALU]> { let Latency = 1; }<br>
> +def : WriteRes<WriteALUs, [A53UnitALU]> { let Latency = 1; }<br>
> +def : WriteRes<WriteCMP, [A53UnitALU]> { let Latency = 1; }<br>
> +<br>
> +// MAC<br>
> +def : WriteRes<WriteMAC, [A53UnitMAC]> { let Latency = 4; }<br>
> +<br>
> +// Div<br>
> +def : WriteRes<WriteDiv, [A53UnitDiv]> { let Latency = 4; }<br>
> +<br>
> +// Load<br>
> +def : WriteRes<WriteLd, [A53UnitLdSt]> { let Latency = 4; }<br>
> +def : WriteRes<WritePreLd, [A53UnitLdSt]> { let Latency = 4; }<br>
> +<br>
> +// Branch<br>
> +def : WriteRes<WriteBr, [A53UnitB]>;<br>
> +def : WriteRes<WriteBrL, [A53UnitB]>;<br>
> +<br>
> +// FP ALU<br>
> +def : WriteRes<WriteFPALU, [A53UnitFPALU]> {let Latency = 6; }<br>
> +<br>
> +// FP MAC, Mul, Div, Sqrt<br>
> +// Using Double Precision numbers for now as a worst case. Additionally, not<br>
> +// modeling the exact hazard but instead treating the whole pipe as a hazard.<br>
> +// As an example VMUL, VMLA, and others are actually pipelined. VDIV and VSQRT<br>
> +// have a total latency of 33 and 32 respectively but only a hazard of 29 and<br>
> +// 28 (double-prescion example).<br>
> +def : WriteRes<WriteFPMAC, [A53UnitFPMDS]> { let Latency = 10; }<br>
> +def : WriteRes<WriteFPMul, [A53UnitFPMDS]> { let Latency = 6; }<br>
> +def : WriteRes<WriteFPDiv, [A53UnitFPMDS]> { let Latency = 33;<br>
> + let ResourceCycles = [29]; }<br>
> +def : WriteRes<WriteFPSqrt, [A53UnitFPMDS]> { let Latency = 32;<br>
> + let ResourceCycles = [28]; }<br>
> +<br>
> +<br>
> +//===----------------------------------------------------------------------===//<br>
> +// Subtarget-specific SchedRead types.<br>
> +<br>
> +// No forwarding defined for ReadALU yet.<br>
> +def : ReadAdvance<ReadALU, 0>;<br>
> +<br>
> +// No forwarding defined for ReadCMP yet.<br>
> +def : ReadAdvance<ReadCMP, 0>;<br>
> +<br>
> +// No forwarding defined for ReadBr yet.<br>
> +def : ReadAdvance<ReadBr, 0>;<br>
> +<br>
> +// No forwarding defined for ReadMAC yet.<br>
> +def : ReadAdvance<ReadMAC, 0>;<br>
> +<br>
> +// No forwarding defined for ReadDiv yet.<br>
> +def : ReadAdvance<ReadDiv, 0>;<br>
> +<br>
> +// No forwarding defined for ReadLd, ReadPreLd yet.<br>
> +def : ReadAdvance<ReadLd, 0>;<br>
> +def : ReadAdvance<ReadPreLd, 0>;<br>
> +<br>
> +// No forwarding defined for ReadFPALU yet.<br>
> +def : ReadAdvance<ReadFPALU, 0>;<br>
> +<br>
> +// No forwarding defined for ReadFPMAC/Mul/Div/Sqrt yet.<br>
> +def : ReadAdvance<ReadFPMAC, 0>;<br>
> +def : ReadAdvance<ReadFPMul, 0>;<br>
> +def : ReadAdvance<ReadFPDiv, 0>;<br>
> +def : ReadAdvance<ReadFPSqrt, 0>;<br>
> +<br>
> +}<br>
><br>
> Modified: llvm/trunk/lib/Target/AArch64/AArch64Subtarget.h<br>
> URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64Subtarget.h?rev=203125&r1=203124&r2=203125&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64Subtarget.h?rev=203125&r1=203124&r2=203125&view=diff</a><br>
> ==============================================================================<br>
> --- llvm/trunk/lib/Target/AArch64/AArch64Subtarget.h (original)<br>
> +++ llvm/trunk/lib/Target/AArch64/AArch64Subtarget.h Thu Mar 6 10:04:00 2014<br>
> @@ -29,6 +29,11 @@ class GlobalValue;<br>
> class AArch64Subtarget : public AArch64GenSubtargetInfo {<br>
> virtual void anchor();<br>
> protected:<br>
> + enum ARMProcFamilyEnum {Others, CortexA53, CortexA57};<br>
> +<br>
> + /// ARMProcFamily - ARM processor family: Cortex-A53, Cortex-A57, and others.<br>
> + ARMProcFamilyEnum ARMProcFamily;<br>
> +<br>
> bool HasFPARMv8;<br>
> bool HasNEON;<br>
> bool HasCrypto;<br>
><br>
> Added: llvm/trunk/test/CodeGen/AArch64/misched-basic-A53.ll<br>
> URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/misched-basic-A53.ll?rev=203125&view=auto" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/misched-basic-A53.ll?rev=203125&view=auto</a><br>
> ==============================================================================<br>
> --- llvm/trunk/test/CodeGen/AArch64/misched-basic-A53.ll (added)<br>
> +++ llvm/trunk/test/CodeGen/AArch64/misched-basic-A53.ll Thu Mar 6 10:04:00 2014<br>
> @@ -0,0 +1,83 @@<br>
> +; REQUIRES: asserts<br>
> +; RUN: llc < %s -mtriple=aarch64-none-linux-gnu -mcpu=cortex-a53 -pre-RA-sched=source -enable-misched -verify-misched -debug-only=misched -o - 2>&1 > /dev/null | FileCheck %s<br>
> +;<br>
> +; The Cortex-A53 machine model will cause the MADD instruction to be scheduled<br>
> +; much higher than the ADD instructions in order to hide latency. When not<br>
> +; specifying a subtarget, the MADD will remain near the end of the block.<br>
> +; CHECK: main<br>
> +; CHECK: *** Final schedule for BB#2 ***<br>
> +; CHECK: SU(13)<br>
> +; CHECK: MADDwwww<br>
> +; CHECK: SU(4)<br>
> +; CHECK: ADDwwi_lsl0_s<br>
> +; CHECK: ********** MI Scheduling **********<br>
> +@main.x = private unnamed_addr constant [8 x i32] [i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1], align 4<br>
> +@main.y = private unnamed_addr constant [8 x i32] [i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2], align 4<br>
> +<br>
> +; Function Attrs: nounwind<br>
> +define i32 @main() #0 {<br>
> +entry:<br>
> + %retval = alloca i32, align 4<br>
> + %x = alloca [8 x i32], align 4<br>
> + %y = alloca [8 x i32], align 4<br>
> + %i = alloca i32, align 4<br>
> + %xx = alloca i32, align 4<br>
> + %yy = alloca i32, align 4<br>
> + store i32 0, i32* %retval<br>
> + %0 = bitcast [8 x i32]* %x to i8*<br>
> + call void @llvm.memcpy.p0i8.p0i8.i64(i8* %0, i8* bitcast ([8 x i32]* @main.x to i8*), i64 32, i32 4, i1 false)<br>
> + %1 = bitcast [8 x i32]* %y to i8*<br>
> + call void @llvm.memcpy.p0i8.p0i8.i64(i8* %1, i8* bitcast ([8 x i32]* @main.y to i8*), i64 32, i32 4, i1 false)<br>
> + store i32 0, i32* %xx, align 4<br>
> + store i32 0, i32* %yy, align 4<br>
> + store i32 0, i32* %i, align 4<br>
> + br label %for.cond<br>
> +<br>
> +for.cond: ; preds = %for.inc, %entry<br>
> + %2 = load i32* %i, align 4<br>
> + %cmp = icmp slt i32 %2, 8<br>
> + br i1 %cmp, label %for.body, label %for.end<br>
> +<br>
> +for.body: ; preds = %for.cond<br>
> + %3 = load i32* %i, align 4<br>
> + %idxprom = sext i32 %3 to i64<br>
> + %arrayidx = getelementptr inbounds [8 x i32]* %x, i32 0, i64 %idxprom<br>
> + %4 = load i32* %arrayidx, align 4<br>
> + %add = add nsw i32 %4, 1<br>
> + store i32 %add, i32* %xx, align 4<br>
> + %5 = load i32* %xx, align 4<br>
> + %add1 = add nsw i32 %5, 12<br>
> + store i32 %add1, i32* %xx, align 4<br>
> + %6 = load i32* %xx, align 4<br>
> + %add2 = add nsw i32 %6, 23<br>
> + store i32 %add2, i32* %xx, align 4<br>
> + %7 = load i32* %xx, align 4<br>
> + %add3 = add nsw i32 %7, 34<br>
> + store i32 %add3, i32* %xx, align 4<br>
> + %8 = load i32* %i, align 4<br>
> + %idxprom4 = sext i32 %8 to i64<br>
> + %arrayidx5 = getelementptr inbounds [8 x i32]* %y, i32 0, i64 %idxprom4<br>
> + %9 = load i32* %arrayidx5, align 4<br>
> + %10 = load i32* %yy, align 4<br>
> + %mul = mul nsw i32 %10, %9<br>
> + store i32 %mul, i32* %yy, align 4<br>
> + br label %for.inc<br>
> +<br>
> +for.inc: ; preds = %for.body<br>
> + %11 = load i32* %i, align 4<br>
> + %inc = add nsw i32 %11, 1<br>
> + store i32 %inc, i32* %i, align 4<br>
> + br label %for.cond<br>
> +<br>
> +for.end: ; preds = %for.cond<br>
> + %12 = load i32* %xx, align 4<br>
> + %13 = load i32* %yy, align 4<br>
> + %add6 = add nsw i32 %12, %13<br>
> + ret i32 %add6<br>
> +}<br>
> +<br>
> +; Function Attrs: nounwind<br>
> +declare void @llvm.memcpy.p0i8.p0i8.i64(i8* nocapture, i8* nocapture readonly, i64, i32, i1) #1<br>
> +<br>
> +attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }<br>
> +attributes #1 = { nounwind }<br>
><br>
><br>
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</div></div></blockquote></div><br></div>