<div dir="ltr"><br><div class="gmail_extra"><br><br><div class="gmail_quote">On Thu, Jan 30, 2014 at 4:51 PM, Owen Anderson <span dir="ltr"><<a href="mailto:resistor@mac.com" target="_blank">resistor@mac.com</a>></span> wrote:<br>
<blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">Author: resistor<br>
Date: Thu Jan 30 18:51:43 2014<br>
New Revision: 200503<br>
<br>
URL: <a href="http://llvm.org/viewvc/llvm-project?rev=200503&view=rev" target="_blank">http://llvm.org/viewvc/llvm-project?rev=200503&view=rev</a><br>
Log:<br>
DAGCombine should not produce ISD::OR nodes after operation legalization if they're not legal.<br></blockquote><div><br></div><div>Is this not testable for some reason?</div><div> </div><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">

<br>
Modified:<br>
    llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp<br>
<br>
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=200503&r1=200502&r2=200503&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=200503&r1=200502&r2=200503&view=diff</a><br>

==============================================================================<br>
--- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original)<br>
+++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Thu Jan 30 18:51:43 2014<br>
@@ -1544,8 +1544,10 @@ SDValue DAGCombiner::visitADD(SDNode *N)<br>
<br>
       // If all possibly-set bits on the LHS are clear on the RHS, return an OR.<br>
       // If all possibly-set bits on the RHS are clear on the LHS, return an OR.<br>
-      if ((RHSZero & ~LHSZero) == ~LHSZero || (LHSZero & ~RHSZero) == ~RHSZero)<br>
-        return DAG.getNode(ISD::OR, SDLoc(N), VT, N0, N1);<br>
+      if ((RHSZero & ~LHSZero) == ~LHSZero || (LHSZero & ~RHSZero) == ~RHSZero){<br>
+        if (!LegalOperations || TLI.isOperationLegal(ISD::OR, VT))<br>
+          return DAG.getNode(ISD::OR, SDLoc(N), VT, N0, N1);<br>
+      }<br>
     }<br>
   }<br>
<br>
<br>
<br>
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</blockquote></div><br></div></div>