<div dir="ltr">Hi Chandler,<div><br></div><div><div>Sorry for responding late. It's because of old version of patch I used to commit. I fixed the test and recommitted as r199704.</div></div></div><div class="gmail_extra">
<br><br><div class="gmail_quote">2014/1/20 Chandler Carruth <span dir="ltr"><<a href="mailto:chandlerc@gmail.com" target="_blank">chandlerc@gmail.com</a>></span><br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">
Author: chandlerc<br>
Date: Mon Jan 20 02:18:01 2014<br>
New Revision: 199631<br>
<br>
URL: <a href="http://llvm.org/viewvc/llvm-project?rev=199631&view=rev" target="_blank">http://llvm.org/viewvc/llvm-project?rev=199631&view=rev</a><br>
Log:<br>
Revert r199628: "[AArch64 NEON] Fix a bug caused by undef lane when generating VEXT."<br>
<br>
This test fails the newly added regression tests.<br>
<br>
Modified:<br>
llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp<br>
llvm/trunk/test/CodeGen/AArch64/neon-extract.ll<br>
<br>
Modified: llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp?rev=199631&r1=199630&r2=199631&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp?rev=199631&r1=199630&r2=199631&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp (original)<br>
+++ llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp Mon Jan 20 02:18:01 2014<br>
@@ -4654,28 +4654,22 @@ AArch64TargetLowering::LowerVECTOR_SHUFF<br>
// it into NEON_VEXTRACT.<br>
if (V1EltNum == Length) {<br>
// Check if the shuffle mask is sequential.<br>
- int SkipUndef = 0;<br>
- while (ShuffleMask[SkipUndef] == -1) {<br>
- SkipUndef++;<br>
- }<br>
- int CurMask = ShuffleMask[SkipUndef];<br>
- if (CurMask >= SkipUndef) {<br>
- bool IsSequential = true;<br>
- for (int I = SkipUndef; I < Length; ++I) {<br>
- if (ShuffleMask[I] != -1 && ShuffleMask[I] != CurMask) {<br>
- IsSequential = false;<br>
- break;<br>
- }<br>
- CurMask++;<br>
- }<br>
- if (IsSequential) {<br>
- assert((EltSize % 8 == 0) && "Bitsize of vector element is incorrect");<br>
- unsigned VecSize = EltSize * V1EltNum;<br>
- unsigned Index = (EltSize / 8) * (ShuffleMask[SkipUndef] - SkipUndef);<br>
- if (VecSize == 64 || VecSize == 128)<br>
- return DAG.getNode(AArch64ISD::NEON_VEXTRACT, dl, VT, V1, V2,<br>
- DAG.getConstant(Index, MVT::i64));<br>
+ bool IsSequential = true;<br>
+ int CurMask = ShuffleMask[0];<br>
+ for (int I = 0; I < Length; ++I) {<br>
+ if (ShuffleMask[I] != CurMask) {<br>
+ IsSequential = false;<br>
+ break;<br>
}<br>
+ CurMask++;<br>
+ }<br>
+ if (IsSequential) {<br>
+ assert((EltSize % 8 == 0) && "Bitsize of vector element is incorrect");<br>
+ unsigned VecSize = EltSize * V1EltNum;<br>
+ unsigned Index = (EltSize/8) * ShuffleMask[0];<br>
+ if (VecSize == 64 || VecSize == 128)<br>
+ return DAG.getNode(AArch64ISD::NEON_VEXTRACT, dl, VT, V1, V2,<br>
+ DAG.getConstant(Index, MVT::i64));<br>
}<br>
}<br>
<br>
<br>
Modified: llvm/trunk/test/CodeGen/AArch64/neon-extract.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/neon-extract.ll?rev=199631&r1=199630&r2=199631&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/neon-extract.ll?rev=199631&r1=199630&r2=199631&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/AArch64/neon-extract.ll (original)<br>
+++ llvm/trunk/test/CodeGen/AArch64/neon-extract.ll Mon Jan 20 02:18:01 2014<br>
@@ -188,35 +188,3 @@ entry:<br>
%vext = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10><br>
ret <8 x i16> %vext<br>
}<br>
-<br>
-define <8 x i8> @test_undef_vext_s8(<8 x i8> %a) {<br>
-; CHECK: test_undef_vext_s8:<br>
-; CHECK: ext {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, #0x2<br>
-entry:<br>
- %vext = shufflevector <8 x i8> %a, <8 x i8> undef, <8 x i32> <i32 10, i32 10, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9><br>
- ret <8 x i8> %vext<br>
-}<br>
-<br>
-define <16 x i8> @test_undef_vextq_s8(<16 x i8> %a) {<br>
-; CHECK: test_undef_vextq_s8:<br>
-; CHECK: ext {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, #0x6<br>
-entry:<br>
- %vext = shufflevector <16 x i8> %a, <16 x i8> undef, <16 x i32> <i32 20, i32 20, i32 20, i32 20, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 20, i32 20, i32 20, i32 20, i32 20><br>
- ret <16 x i8> %vext<br>
-}<br>
-<br>
-define <4 x i16> @test_undef_vext_s16(<4 x i16> %a) {<br>
-; CHECK: test_undef_vext_s16:<br>
-; CHECK: ext {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, #0x2<br>
-entry:<br>
- %vext = shufflevector <4 x i16> %a, <4 x i16> undef, <4 x i32> <i32 4, i32 2, i32 3, i32 4><br>
- ret <4 x i16> %vext<br>
-}<br>
-<br>
-define <8 x i16> @test_undef_vextq_s16(<8 x i16> %a) {<br>
-; CHECK: test_undef_vextq_s16:<br>
-; CHECK: ext {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, #0x6<br>
-entry:<br>
- %vext = shufflevector <8 x i16> %a, <8 x i16> undef, <8 x i32> <i32 10, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10><br>
- ret <8 x i16> %vext<br>
-}<br>
<br>
<br>
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</blockquote></div><br><br clear="all"><div><br></div>-- <br><div dir="ltr">Best Regards,<div><br></div><div>Kevin Qin</div></div>
</div>