<div dir="ltr"><div class="gmail_extra"><div class="gmail_quote">On Fri, Jan 10, 2014 at 6:26 AM, Oliver Stannard <span dir="ltr"><<a href="mailto:oliver.stannard@arm.com" target="_blank">oliver.stannard@arm.com</a>></span> wrote:<br>
<blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left-width:1px;border-left-color:rgb(204,204,204);border-left-style:solid;padding-left:1ex">Hi Saleem,<br>
<br>
It seems this commit introduced a regression.<br></blockquote><div><br></div><div>Seems so, sorry. SVN r198944 should address it. Please note that the result will change to the implicit immediate 0 form:</div><div><br>
</div><div>$ echo "0x00,0x10,0xa0,0x04" | llvm-mc -mcpu=cortex-a15 -triple armv7 -disassemble</div><div> .text</div><div> strteq r1, [r0]</div><div><br></div><div>Thanks for catching this issue.</div>
<div> </div><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left-width:1px;border-left-color:rgb(204,204,204);border-left-style:solid;padding-left:1ex">
Before this commit, I get:<br>
$ echo "0x00,0x10,0xa0,0x04" | llvm-mc -mcpu=cortex-a15 -triple armv7<br>
-disassemble<br>
.text<br>
strteq r1, [r0], #0<br>
<br>
After this commit, I get:<br>
$ echo "0x00,0x10,0xa0,0x04" | llvm-mc -mcpu=cortex-a15 -triple armv7<br>
-disassemble<br>
.text<br>
strtUnknown condition code<br>
UNREACHABLE executed at<br>
/work/llvm/lib/Target/ARM/MCTargetDesc/ARMBaseInfo.h:86!<br>
0 llvm-mc 0x00000000006567f2<br>
1 llvm-mc 0x0000000000656429<br>
2 libpthread.so.0 0x00007f18c076a8f0<br>
3 libc.so.6 0x00007f18bfa56b25 gsignal + 53<br>
4 libc.so.6 0x00007f18bfa5a670 abort + 384<br>
5 llvm-mc 0x0000000000639cbc<br>
6 llvm-mc 0x0000000000573a61<br>
7 llvm-mc 0x000000000057774c<br>
8 llvm-mc 0x000000000057d20e<br>
9 llvm-mc 0x0000000000580906<br>
10 llvm-mc 0x00000000005d776b<br>
11 llvm-mc 0x000000000041998c<br>
12 llvm-mc 0x000000000040fbf5<br>
13 libc.so.6 0x00007f18bfa41c4d __libc_start_main + 253<br>
14 llvm-mc 0x000000000041369d<br>
Stack dump:<br>
0. Program arguments: /work/llvm/bin/llvm-mc -mcpu=cortex-a15 -triple<br>
armv7 -disassemble<br>
Aborted<br>
<br>
Would it be possible to fix this regression (and add the necessary test<br>
cases that trigger this bug)?<br>
<br>
Thank,<br>
Oliver<br>
<div class=""><div class="h5"><br>
-----Original Message-----<br>
From: <a href="mailto:llvm-commits-bounces@cs.uiuc.edu">llvm-commits-bounces@cs.uiuc.edu</a><br>
[mailto:<a href="mailto:llvm-commits-bounces@cs.uiuc.edu">llvm-commits-bounces@cs.uiuc.edu</a>] On Behalf Of Saleem Abdulrasool<br>
Sent: 10 January 2014 04:39<br>
To: <a href="mailto:llvm-commits@cs.uiuc.edu">llvm-commits@cs.uiuc.edu</a><br>
Subject: [llvm] r198914 - ARM IAS: support implicit immediate 0s for {LD,<br>
ST}R{B, }T<br>
<br>
Author: compnerd<br>
Date: Thu Jan 9 22:38:31 2014<br>
New Revision: 198914<br>
<br>
URL: <a href="http://llvm.org/viewvc/llvm-project?rev=198914&view=rev" target="_blank">http://llvm.org/viewvc/llvm-project?rev=198914&view=rev</a><br>
Log:<br>
ARM IAS: support implicit immediate 0s for {LD,ST}R{B,}T<br>
<br>
The ARM ARM indicates the mnemonics as follows:<br>
<br>
ldrbt{<c>}{<q>} <Rt>, [<Rn>], {, #+/-<imm>}<br>
ldrt{<c>}{<q>} <Rt>, [<Rn>] {, #+/-<imm>}<br>
strbt{<c>}{<q>} <Rt>, [<Rn>] {, #<imm>}<br>
strt{<c>}{<q>} <Rt>, [<Rn>] {, #+/-<imm>}<br>
<br>
This improves the parser to deal with the implicit immediate 0 for the<br>
mnemonics<br>
as per the specification.<br>
<br>
Thanks to Joerg Sonnenberger for the tests!<br>
<br>
Modified:<br>
llvm/trunk/lib/Target/ARM/ARMInstrInfo.td<br>
llvm/trunk/test/MC/ARM/arm_addrmode2.s<br>
<br>
Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td<br>
URL:<br>
<a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.t
d?rev=198914&r1=198913&r2=198914&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.t<br>
d?rev=198914&r1=198913&r2=198914&view=diff</a><br>
============================================================================<br>
==<br>
--- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original)<br>
+++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Thu Jan 9 22:38:31 2014<br>
@@ -2444,23 +2444,28 @@ def LDRT_POST_REG : AI2ldstidx<1, 0, 0,<br>
let DecoderMethod = "DecodeAddrMode2IdxInstruction";<br>
}<br>
<br>
-def LDRT_POST_IMM : AI2ldstidx<1, 0, 0, (outs GPR:$Rt, GPR:$Rn_wb),<br>
- (ins addr_offset_none:$addr, am2offset_imm:$offset),<br>
- IndexModePost, LdFrm, IIC_iLoad_ru,<br>
- "ldrt", "\t$Rt, $addr, $offset",<br>
- "$addr.base = $Rn_wb", []> {<br>
+class LDRTImmediate<bit has_offset, string args, dag iops><br>
+ : AI2ldstidx<1, 0, 0, (outs GPR:$Rt, GPR:$Rn_wb), iops,<br>
+ IndexModePost, LdFrm, IIC_iLoad_ru,<br>
+ "ldrt", args, "$addr.base = $Rn_wb", []> {<br>
// {12} isAdd<br>
// {11-0} imm12/Rm<br>
bits<14> offset;<br>
bits<4> addr;<br>
let Inst{25} = 0;<br>
- let Inst{23} = offset{12};<br>
+ let Inst{23} = !if(has_offset, offset{12}, 1);<br>
let Inst{21} = 1; // overwrite<br>
let Inst{19-16} = addr;<br>
- let Inst{11-0} = offset{11-0};<br>
+ let Inst{11-0} = !if(has_offset, offset{11-0}, 0);<br>
let DecoderMethod = "DecodeAddrMode2IdxInstruction";<br>
}<br>
<br>
+def LDRT_POST_IMM<br>
+ : LDRTImmediate<1, "\t$Rt, $addr, $offset",<br>
+ (ins addr_offset_none:$addr, am2offset_imm:$offset)>;<br>
+def LDRT_POST_IMM_0<br>
+ : LDRTImmediate<0, "\t$Rt, $addr", (ins addr_offset_none:$addr)>;<br>
+<br>
def LDRBT_POST_REG : AI2ldstidx<1, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),<br>
(ins addr_offset_none:$addr, am2offset_reg:$offset),<br>
IndexModePost, LdFrm, IIC_iLoad_bh_ru,<br>
@@ -2480,23 +2485,28 @@ def LDRBT_POST_REG : AI2ldstidx<1, 1, 0,<br>
let DecoderMethod = "DecodeAddrMode2IdxInstruction";<br>
}<br>
<br>
-def LDRBT_POST_IMM : AI2ldstidx<1, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),<br>
- (ins addr_offset_none:$addr, am2offset_imm:$offset),<br>
+class LDRBTImmediate<bit has_offset, string args, dag iops><br>
+ : AI2ldstidx<1, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb), iops,<br>
IndexModePost, LdFrm, IIC_iLoad_bh_ru,<br>
- "ldrbt", "\t$Rt, $addr, $offset",<br>
- "$addr.base = $Rn_wb", []> {<br>
+ "ldrbt", args, "$addr.base = $Rn_wb", []> {<br>
// {12} isAdd<br>
// {11-0} imm12/Rm<br>
bits<14> offset;<br>
bits<4> addr;<br>
let Inst{25} = 0;<br>
- let Inst{23} = offset{12};<br>
+ let Inst{23} = !if(has_offset, offset{12}, 1);<br>
let Inst{21} = 1; // overwrite<br>
let Inst{19-16} = addr;<br>
- let Inst{11-0} = offset{11-0};<br>
+ let Inst{11-0} = !if(has_offset, offset{11-0}, 0);<br>
let DecoderMethod = "DecodeAddrMode2IdxInstruction";<br>
}<br>
<br>
+def LDRBT_POST_IMM<br>
+ : LDRBTImmediate<1, "\t$Rt, $addr, $offset",<br>
+ (ins addr_offset_none:$addr, am2offset_imm:$offset)>;<br>
+def LDRBT_POST_IMM_0<br>
+ : LDRBTImmediate<0, "\t$Rt, $addr", (ins addr_offset_none:$addr)>;<br>
+<br>
multiclass AI3ldrT<bits<4> op, string opc> {<br>
def i : AI3ldstidxT<op, 1, (outs GPR:$Rt, GPR:$base_wb),<br>
(ins addr_offset_none:$addr, postidx_imm8:$offset),<br>
@@ -2748,23 +2758,27 @@ def STRBT_POST_REG : AI2ldstidx<0, 1, 0,<br>
let DecoderMethod = "DecodeAddrMode2IdxInstruction";<br>
}<br>
<br>
-def STRBT_POST_IMM : AI2ldstidx<0, 1, 0, (outs GPR:$Rn_wb),<br>
- (ins GPR:$Rt, addr_offset_none:$addr,<br>
am2offset_imm:$offset),<br>
- IndexModePost, StFrm, IIC_iStore_bh_ru,<br>
- "strbt", "\t$Rt, $addr, $offset",<br>
- "$addr.base = $Rn_wb", []> {<br>
+class STRBTImmediate<bit has_offset, string args, dag iops><br>
+ : AI2ldstidx<0, 1, 0, (outs GPR:$Rn_wb), iops, IndexModePost, StFrm,<br>
+ IIC_iStore_bh_ru, "strbt", args, "$addr.base = $Rn_wb", []><br>
{<br>
// {12} isAdd<br>
// {11-0} imm12/Rm<br>
bits<14> offset;<br>
bits<4> addr;<br>
let Inst{25} = 0;<br>
- let Inst{23} = offset{12};<br>
+ let Inst{23} = !if(has_offset, offset{12}, 1);<br>
let Inst{21} = 1; // overwrite<br>
let Inst{19-16} = addr;<br>
- let Inst{11-0} = offset{11-0};<br>
+ let Inst{11-0} = !if(has_offset, offset{11-0}, 0);<br>
let DecoderMethod = "DecodeAddrMode2IdxInstruction";<br>
}<br>
<br>
+def STRBT_POST_IMM<br>
+ : STRBTImmediate<1, "\t$Rt, $addr, $offset",<br>
+ (ins GPR:$Rt, addr_offset_none:$addr,<br>
am2offset_imm:$offset)>;<br>
+def STRBT_POST_IMM_0<br>
+ : STRBTImmediate<0, "\t$Rt, $addr", (ins GPR:$Rt,<br>
addr_offset_none:$addr)>;<br>
+<br>
let mayStore = 1, neverHasSideEffects = 1 in {<br>
def STRT_POST_REG : AI2ldstidx<0, 0, 0, (outs GPR:$Rn_wb),<br>
(ins GPR:$Rt, addr_offset_none:$addr,<br>
am2offset_reg:$offset),<br>
@@ -2785,22 +2799,26 @@ def STRT_POST_REG : AI2ldstidx<0, 0, 0,<br>
let DecoderMethod = "DecodeAddrMode2IdxInstruction";<br>
}<br>
<br>
-def STRT_POST_IMM : AI2ldstidx<0, 0, 0, (outs GPR:$Rn_wb),<br>
- (ins GPR:$Rt, addr_offset_none:$addr,<br>
am2offset_imm:$offset),<br>
- IndexModePost, StFrm, IIC_iStore_ru,<br>
- "strt", "\t$Rt, $addr, $offset",<br>
- "$addr.base = $Rn_wb", []> {<br>
+class STRTImmediate<bit has_offset, string args, dag iops><br>
+ : AI2ldstidx<0, 0, 0, (outs GPR:$Rn_wb), iops, IndexModePost, StFrm,<br>
+ IIC_iStore_ru, "strt", args, "$addr.base = $Rn_wb", []> {<br>
// {12} isAdd<br>
// {11-0} imm12/Rm<br>
bits<14> offset;<br>
bits<4> addr;<br>
let Inst{25} = 0;<br>
- let Inst{23} = offset{12};<br>
+ let Inst{23} = !if(has_offset, offset{12}, 1);<br>
let Inst{21} = 1; // overwrite<br>
let Inst{19-16} = addr;<br>
- let Inst{11-0} = offset{11-0};<br>
+ let Inst{11-0} = !if(has_offset, offset{11-0}, 0);<br>
let DecoderMethod = "DecodeAddrMode2IdxInstruction";<br>
}<br>
+<br>
+def STRT_POST_IMM<br>
+ : STRTImmediate<1, "\t$Rt, $addr, $offset",<br>
+ (ins GPR:$Rt, addr_offset_none:$addr,<br>
am2offset_imm:$offset)>;<br>
+def STRT_POST_IMM_0<br>
+ : STRTImmediate<0, "\t$Rt, $addr", (ins GPR:$Rt,<br>
addr_offset_none:$addr)>;<br>
}<br>
<br>
<br>
<br>
Modified: llvm/trunk/test/MC/ARM/arm_addrmode2.s<br>
URL:<br>
<a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/arm_addrmode2.s?r
ev=198914&r1=198913&r2=198914&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/arm_addrmode2.s?r<br>
ev=198914&r1=198913&r2=198914&view=diff</a><br>
============================================================================<br>
==<br>
--- llvm/trunk/test/MC/ARM/arm_addrmode2.s (original)<br>
+++ llvm/trunk/test/MC/ARM/arm_addrmode2.s Thu Jan 9 22:38:31 2014<br>
@@ -4,27 +4,35 @@<br>
@ CHECK: ldrt r1, [r0], r2 @ encoding: [0x02,0x10,0xb0,0xe6]<br>
@ CHECK: ldrt r1, [r0], r2, lsr #3 @ encoding: [0xa2,0x11,0xb0,0xe6]<br>
@ CHECK: ldrt r1, [r0], #4 @ encoding: [0x04,0x10,0xb0,0xe4]<br>
+@ CHECK: ldrt r1, [r0] @ encoding: [0x00,0x10,0xb0,0xe4]<br>
@ CHECK: ldrbt r1, [r0], r2 @ encoding: [0x02,0x10,0xf0,0xe6]<br>
@ CHECK: ldrbt r1, [r0], r2, lsr #3 @ encoding: [0xa2,0x11,0xf0,0xe6]<br>
@ CHECK: ldrbt r1, [r0], #4 @ encoding: [0x04,0x10,0xf0,0xe4]<br>
+@ CHECK: ldrbt r1, [r0] @ encoding: [0x00,0x10,0xf0,0xe4]<br>
@ CHECK: strt r1, [r0], r2 @ encoding: [0x02,0x10,0xa0,0xe6]<br>
@ CHECK: strt r1, [r0], r2, lsr #3 @ encoding: [0xa2,0x11,0xa0,0xe6]<br>
@ CHECK: strt r1, [r0], #4 @ encoding: [0x04,0x10,0xa0,0xe4]<br>
+@ CHECK: strt r1, [r0] @ encoding: [0x00,0x10,0xa0,0xe4]<br>
@ CHECK: strbt r1, [r0], r2 @ encoding: [0x02,0x10,0xe0,0xe6]<br>
@ CHECK: strbt r1, [r0], r2, lsr #3 @ encoding: [0xa2,0x11,0xe0,0xe6]<br>
@ CHECK: strbt r1, [r0], #4 @ encoding: [0x04,0x10,0xe0,0xe4]<br>
+@ CHECK: strbt r1, [r0] @ encoding: [0x00,0x10,0xe0,0xe4]<br>
ldrt r1, [r0], r2<br>
ldrt r1, [r0], r2, lsr #3<br>
ldrt r1, [r0], #4<br>
+ ldrt r1, [r0]<br>
ldrbt r1, [r0], r2<br>
ldrbt r1, [r0], r2, lsr #3<br>
ldrbt r1, [r0], #4<br>
+ ldrbt r1, [r0]<br>
strt r1, [r0], r2<br>
strt r1, [r0], r2, lsr #3<br>
strt r1, [r0], #4<br>
+ strt r1, [r0]<br>
strbt r1, [r0], r2<br>
strbt r1, [r0], r2, lsr #3<br>
strbt r1, [r0], #4<br>
+ strbt r1, [r0]<br>
<br>
@ Pre-indexed<br>
@ CHECK: ldr r1, [r0, r2, lsr #3]! @ encoding: [0xa2,0x11,0xb0,0xe7]<br>
<br>
<br>
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<br>
</div></div></blockquote></div><br><br clear="all"><div><br></div>-- <br>Saleem Abdulrasool<br>compnerd (at) compnerd (dot) org
</div></div>