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</o:shapelayout></xml><![endif]--></head><body lang=EN-US link=blue vlink=purple><div class=WordSection1><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'>Thanks Jiangning,<o:p></o:p></span></p><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'><o:p> </o:p></span></p><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'>It looks like the failing patterns are corrected in this patch.<o:p></o:p></span></p><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'><o:p> </o:p></span></p><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'>I will rerun the benchmarks with –mfpu=neon using this patch and let you know if I encounter failures.<o:p></o:p></span></p><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'><o:p> </o:p></span></p><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'>Your solution is fine, but I think doing it at the time of lowering sext_inreg would be simpler, since you do not have to re-discover that the pattern SHL/SHRA is doing a sext_inreg.<o:p></o:p></span></p><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'><o:p> </o:p></span></p><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'>Thanks,<o:p></o:p></span></p><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'>Ana.<o:p></o:p></span></p><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'><o:p> </o:p></span></p><p class=MsoNormal><b><span style='font-size:10.0pt;font-family:"Tahoma","sans-serif"'>From:</span></b><span style='font-size:10.0pt;font-family:"Tahoma","sans-serif"'> Jiangning Liu [mailto:liujiangning1@gmail.com] <br><b>Sent:</b> Tuesday, January 07, 2014 11:22 PM<br><b>To:</b> Ana Pazos<br><b>Cc:</b> llvm-commits@cs.uiuc.edu for LLVM; mcrosier@codeaurora.org<br><b>Subject:</b> Re: [PATCH] [AArch64] Support ISD::SIGN_EXTEND_INREG<o:p></o:p></span></p><p class=MsoNormal><o:p> </o:p></p><div><div><p class=MsoNormal><span style='font-family:"Arial","sans-serif"'>Hi Ana,<o:p></o:p></span></p></div><div><p class=MsoNormal><span style='font-family:"Arial","sans-serif"'><o:p> </o:p></span></p></div><div><p class=MsoNormal><span style='font-family:"Arial","sans-serif"'>I'm attaching a new patch and now we can generate more SSHLL instructions. Refer to my test cases, please!<o:p></o:p></span></p></div><div><p class=MsoNormal><span style='font-family:"Arial","sans-serif"'><o:p> </o:p></span></p></div><div><p class=MsoNormal><span style='font-family:"Arial","sans-serif"'>However, there is a hole in lowering shuffle_vector, so we couldn't generate instruction uzip1 yet.<o:p></o:p></span></p></div><div><p class=MsoNormal><span style='font-family:"Arial","sans-serif"'><o:p> </o:p></span></p></div><div><p class=MsoNormal><span style='font-family:"Arial","sans-serif"'>Kevin is giving follow-up and will upstream a separate patch to generate uzip1, and he will also adding more CHECK in my test case to capture this instruction.<o:p></o:p></span></p></div><div><p class=MsoNormal><span style='font-family:"Arial","sans-serif"'><o:p> </o:p></span></p></div><div><p class=MsoNormal><span style='font-family:"Arial","sans-serif"'>Thanks,<o:p></o:p></span></p></div><div><p class=MsoNormal><span style='font-family:"Arial","sans-serif"'>-Jiangning<o:p></o:p></span></p></div><div><p class=MsoNormal><span style='font-family:"Arial","sans-serif"'><o:p> </o:p></span></p></div></div><div><p class=MsoNormal style='margin-bottom:12.0pt'><o:p> </o:p></p><div><p class=MsoNormal>2014/1/8 Jiangning Liu <<a href="mailto:liujiangning1@gmail.com" target="_blank">liujiangning1@gmail.com</a>><o:p></o:p></p><div><div><p class=MsoNormal><span style='font-family:"Arial","sans-serif"'>Hi Ana,<o:p></o:p></span></p></div><div><p class=MsoNormal><span style='font-family:"Arial","sans-serif"'><o:p> </o:p></span></p></div><div><p class=MsoNormal><span style='font-family:"Arial","sans-serif"'>Consider more about this optimization, and now I think the second patch I gave is incorrect.<o:p></o:p></span></p></div><div><p class=MsoNormal><span style='font-family:"Arial","sans-serif"'><o:p> </o:p></span></p></div><div><p class=MsoNormal><span style='font-family:"Arial","sans-serif"'>Basically we have the following three cases to cover,<o:p></o:p></span></p></div><div><p class=MsoNormal><span style='font-family:"Arial","sans-serif"'><o:p> </o:p></span></p></div><div><p class=MsoNormal><span style='font-family:"Arial","sans-serif"'>1) sext_inreg(v2i16, v2i8)<o:p></o:p></span></p></div><div><div><p class=MsoNormal><span style='font-family:"Arial","sans-serif"'>sshll v0.8h, v0.8b, #0</span><o:p></o:p></p></div><div><p class=MsoNormal><span style='font-family:"Arial","sans-serif"'>shuffle_vector(<8xi16>, <8xi16>, <i32, i32> (0, 4))</span><o:p></o:p></p></div><div><p class=MsoNormal><o:p> </o:p></p></div><div><p class=MsoNormal><span style='font-family:"Arial","sans-serif"'>2) sext_inreg(v4i16, v4i8)</span><o:p></o:p></p></div></div><div><div><p class=MsoNormal><span style='font-family:"Arial","sans-serif"'>sshll v0.8h, <a href="http://v0.bb" target="_blank">v0.bb</a>, #0<o:p></o:p></span></p></div><div><div><p class=MsoNormal><span style='font-family:"Arial","sans-serif"'>shuffle_vector(<8xi16>, <8xi16>, <i32, i32, i32, i32> (0, 2, 4, 6))<o:p></o:p></span></p></div></div><div><p class=MsoNormal><span style='font-family:"Arial","sans-serif"'><o:p> </o:p></span></p></div></div><div><p class=MsoNormal><span style='font-family:"Arial","sans-serif"'>3) sext_inreg(v2i32, v2i16)<o:p></o:p></span></p></div><div><div><p class=MsoNormal><span style='font-family:"Arial","sans-serif"'>sshll v0.4s, v0.4h, #0<o:p></o:p></span></p></div><div><div><div><p class=MsoNormal><span style='font-family:"Arial","sans-serif"'>shuffle_vector(<4xi32>, <4xi32>, <i32, i32> (0, 2))<o:p></o:p></span></p></div></div></div><div><p class=MsoNormal><span style='font-family:"Arial","sans-serif"'><o:p> </o:p></span></p></div><div><p class=MsoNormal><span style='font-family:"Arial","sans-serif"'>All other cases should have been covered by the 1st patch.<o:p></o:p></span></p></div><div><p class=MsoNormal><span style='font-family:"Arial","sans-serif"'><o:p> </o:p></span></p></div><div><p class=MsoNormal><span style='font-family:"Arial","sans-serif"'>Thanks,<o:p></o:p></span></p></div><div><p class=MsoNormal><span style='font-family:"Arial","sans-serif"'>-Jiangning<o:p></o:p></span></p></div><div><p class=MsoNormal><span style='font-family:"Arial","sans-serif"'><o:p> </o:p></span></p></div></div></div><div><div><div><p class=MsoNormal style='margin-bottom:12.0pt'><o:p> </o:p></p><div><p class=MsoNormal>2014/1/7 Jiangning Liu <<a href="mailto:liujiangning1@gmail.com" target="_blank">liujiangning1@gmail.com</a>><o:p></o:p></p><div><p class=MsoNormal>Ana,<br><br>I see your point now.<br><br>Actually <o:p></o:p></p><div><p class=MsoNormal><span style='font-family:"Arial","sans-serif"'>with my patch <o:p></o:p></span></p></div><p class=MsoNormal>sign_extend_inreg(v8i16, v8i8) can generate SXTL(8b->8h) as shown with my test case below,<o:p></o:p></p><div><p class=MsoNormal style='margin-bottom:12.0pt'><br><br>define <8 x i8> @test_sext_inreg_v8i8i16(<8 x i8> %v1, <8 x i8> %v2) nounwind readnone {<br>; CHECK-LABEL: test_sext_inreg_v8i8i16<br>; CHECK: sshll v0.8h, v0.8b, #0<br>; CHECK: sshll v1.8h, v1.8b, #0<br> %1 = sext <8 x i8> %v1 to <8 x i16><br> %2 = sext <8 x i8> %v2 to <8 x i16><br> %3 = shufflevector <8 x i16> %1, <8 x i16> %2, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14><br> %4 = trunc <8 x i16> %3 to <8 x i8><br> ret <8 x i8> %4<br>}<o:p></o:p></p></div><div><p class=MsoNormal><span style='font-family:"Arial","sans-serif"'>And <o:p></o:p></span></p></div><p class=MsoNormal>sign_extend_inreg(v2i64, v2i32) doesn't exist, because we always use sign_extend(v2i64, v2i32) to solve it as shown by test case below,<br><br>define <2 x i32> @test_sext_inreg_v2i32i64(<2 x i32> %v1, <2 x i32> %v2) nounwind readnone {<br>; CHECK-LABEL: test_sext_inreg_v2i32i64<br>; CHECK: sshll v0.2d, v0.2s, #0<br>; CHECK: sshll v1.2d, v1.2s, #0<br> %1 = sext <2 x i32> %v1 to <2 x i64><br> %2 = sext <2 x i32> %v2 to <2 x i64><br> %3 = shufflevector <2 x i64> %1, <2 x i64> %2, <2 x i32> <i32 0, i32 2><br> %4 = trunc <2 x i64> %3 to <2 x i32><br> ret <2 x i32> %4<br>}<br><br>However, yes<o:p></o:p></p><div><p class=MsoNormal><span style='font-family:"Arial","sans-serif"'>, <o:p></o:p></span></p></div><p class=MsoNormal>sign_extend_inreg(v2i32, v2i16) would be an issue, so I modified my patch as attached and changed the test test_sext_inreg_v2i16i32 to be like below by using sshll instruction.<o:p></o:p></p><div><p class=MsoNormal><br><br>define <2 x i16> @test_sext_inreg_v2i16i32(<2 x i16> %v1, <2 x i16> %v2) nounwind readnone {<br>; CHECK-LABEL: test_sext_inreg_v2i16i32<o:p></o:p></p></div><p class=MsoNormal>; CHECK: sshll v0.4s, v0.4h, #0<br>; CHECK: sshll v1.4s, v1.4h, #0<o:p></o:p></p><div><p class=MsoNormal style='margin-bottom:12.0pt'><br> %1 = sext <2 x i16> %v1 to <2 x i32><br> %2 = sext <2 x i16> %v2 to <2 x i32><br> %3 = shufflevector <2 x i32> %1, <2 x i32> %2, <2 x i32> <i32 0, i32 2><br> %4 = trunc <2 x i32> %3 to <2 x i16><br> ret <2 x i16> %4<br>}<o:p></o:p></p></div><div><p class=MsoNormal><span style='font-family:"Arial","sans-serif"'>The solution is by doing combine to capture this special sha/shl pair. Do we have more missing cases?<o:p></o:p></span></p></div><p class=MsoNormal><br>Thanks,<br>-Jiangning<o:p></o:p></p><div><div><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'><o:p> </o:p></span></p></div></div></div><div><div><div><p class=MsoNormal style='margin-bottom:12.0pt'><o:p> </o:p></p><div><p class=MsoNormal>2014/1/7 Ana Pazos <<a href="mailto:apazos@codeaurora.org" target="_blank">apazos@codeaurora.org</a>><o:p></o:p></p><div><div><p class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:auto'><span style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'>Hi Jiangning,</span><o:p></o:p></p><p class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:auto'><span style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'> </span><o:p></o:p></p><p class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:auto'><span style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'>The test cases I see failure are</span><o:p></o:p></p><p class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:auto'><span style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'>sign_extend_inreg(v2i32, v2i16) and </span><o:p></o:p></p><p class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:auto'><span style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'>sign_extend_inreg(v4i16, v4i8) - sorry I had a typo v8i8 but I meant v4i8 which confused you.</span><o:p></o:p></p><p class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:auto'><span style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'> </span><o:p></o:p></p><p class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:auto'><span style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'>So it seems your patch addresses both cases I was concerned about.</span><o:p></o:p></p><p class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:auto'><span style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'> </span><o:p></o:p></p><p class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:auto'><span style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'>But for such cases I think the SXTL instruction could be used instead of the combo shift right + shift left.</span><o:p></o:p></p><p class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:auto'><span style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'> </span><o:p></o:p></p><p class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:auto'><span style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'>For example sign_extend_inreg(v2i32, v2i16):</span><o:p></o:p></p><p><span style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'>-</span><span style='font-size:7.0pt;color:#1F497D'> </span><span style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'>Input are 16-bit values in a 2S register</span><o:p></o:p></p><p><span style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'>-</span><span style='font-size:7.0pt;color:#1F497D'> </span><span style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'>Reinterpret register as 4H register</span><o:p></o:p></p><p><span style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'>-</span><span style='font-size:7.0pt;color:#1F497D'> </span><span style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'>SXTL (4S <– 4H)</span><o:p></o:p></p><p><span style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'>-</span><span style='font-size:7.0pt;color:#1F497D'> </span><span style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'>Ins/uzp1 (to extract the vector indexes 0, 2 we need into a 2S register)</span><o:p></o:p></p><p class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:auto'><span style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'> </span><o:p></o:p></p><p class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:auto'><span style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'>The same can be done for sign_extend_inreg(v8i16, v8i8) and sign_extend_inreg(v2i64, v2i32).</span><o:p></o:p></p><p class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:auto'><span style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'> </span><o:p></o:p></p><p class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:auto'><span style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'>I think in some cases the extraction of vector indexes we are interested in will be a no-op and an instruction will be saved.</span><o:p></o:p></p><p class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:auto'><span style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'> </span><o:p></o:p></p><p class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:auto'><span style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'>I am just suggesting to use a hardware instruction that does the sign extension for those vector types it supports.</span><o:p></o:p></p><p class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:auto'><span style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'> </span><o:p></o:p></p><p class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:auto'><span style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'>Do you agree?</span><o:p></o:p></p><p class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:auto'><span style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'> </span><o:p></o:p></p><p class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:auto'><span style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'>Thanks,</span><o:p></o:p></p><p class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:auto'><span style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'>Ana.</span><o:p></o:p></p><p class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:auto'><span style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'> </span><o:p></o:p></p><p class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:auto'><b><span style='font-size:10.0pt;font-family:"Tahoma","sans-serif"'>From:</span></b><span style='font-size:10.0pt;font-family:"Tahoma","sans-serif"'> Jiangning Liu [mailto:<a href="mailto:liujiangning1@gmail.com" target="_blank">liujiangning1@gmail.com</a>] <br><b>Sent:</b> Sunday, January 05, 2014 10:44 PM<br><b>To:</b> Ana Pazos<br><b>Cc:</b> <a href="mailto:llvm-commits@cs.uiuc.edu" target="_blank">llvm-commits@cs.uiuc.edu</a> for LLVM; <a href="mailto:mcrosier@codeaurora.org" target="_blank">mcrosier@codeaurora.org</a><br><b>Subject:</b> Re: [PATCH] [AArch64] Support ISD::SIGN_EXTEND_INREG</span><o:p></o:p></p><div><div><p class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:auto'> <o:p></o:p></p><div><div><p class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:auto'><span style='font-family:"Arial","sans-serif"'>Hi </span><o:p></o:p></p></div><p class=MsoNormal style='mso-margin-top-alt:auto;margin-bottom:12.0pt'>Ana,<br><br>Sorry, I don't quite understand what you said. Do you have a small test to articulate what you mentioned?<br><br>For sign_extend_inreg(v2i32, v2i16), my test case below should show my patch work,<br><br>define <2 x i16> @test_sext_inreg_v2i16i32(<2 x i16> %v1, <2 x i16> %v2) nounwind readnone {<br>; CHECK-LABEL: test_sext_inreg_v2i16i32<br>; CHECK: shl v0.2s, v0.2s, #16<br>; CHECK: sshr v0.2s, v0.2s, #16<br>; CHECK: shl v1.2s, v1.2s, #16<br>; CHECK: sshr v1.2s, v1.2s, #16<br> %1 = sext <2 x i16> %v1 to <2 x i32><br> %2 = sext <2 x i16> %v2 to <2 x i32><br> %3 = shufflevector <2 x i32> %1, <2 x i32> %2, <2 x i32> <i32 0, i32 2><br> %4 = trunc <2 x i32> %3 to <2 x i16><br> ret <2 x i16> %4<br>}<br><br>For sign_extend_inreg(v4i16, v8i8), is this a valid? I thought it should be sign_extend_inreg(v8i16, v8i8). If this is the case, my test below should also show my patch work,<br><br>define <8 x i8> @test_sext_inreg_v8i8i16(<8 x i8> %v1, <8 x i8> %v2) nounwind readnone {<br>; CHECK-LABEL: test_sext_inreg_v8i8i16<br>; CHECK: sshll v0.8h, v0.8b, #0<br>; CHECK: sshll v1.8h, v1.8b, #0<br> %1 = sext <8 x i8> %v1 to <8 x i16><br> %2 = sext <8 x i8> %v2 to <8 x i16><br> %3 = shufflevector <8 x i16> %1, <8 x i16> %2, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14><br> %4 = trunc <8 x i16> %3 to <8 x i8><br> ret <8 x i8> %4<br>}<br><br>Thanks,<br>-Jiangning<o:p></o:p></p></div></div></div></div></div></div><p class=MsoNormal><br><br clear=all><o:p></o:p></p><div><p class=MsoNormal><o:p> </o:p></p></div></div></div><p class=MsoNormal><span style='color:#888888'>-- <o:p></o:p></span></p><div><p class=MsoNormal><span style='font-family:"Courier New";color:#888888'>Thanks,</span><span style='color:#888888'><o:p></o:p></span></p><div><p class=MsoNormal><span style='font-family:"Courier New";color:#888888'>-Jiangning</span><span style='color:#888888'><o:p></o:p></span></p></div></div></div></div><p class=MsoNormal><br><br clear=all><o:p></o:p></p><div><p class=MsoNormal><o:p> </o:p></p></div></div></div><p class=MsoNormal><span class=hoenzb><span style='color:#888888'>-- <o:p></o:p></span></span></p><div><p class=MsoNormal><span style='font-family:"Courier New";color:#888888'>Thanks,</span><o:p></o:p></p><div><p class=MsoNormal><span style='font-family:"Courier New";color:#888888'>-Jiangning</span><span style='color:#888888'><o:p></o:p></span></p></div></div></div></div><p class=MsoNormal><br><br clear=all><o:p></o:p></p><div><p class=MsoNormal><o:p> </o:p></p></div><p class=MsoNormal>-- <o:p></o:p></p><div><p class=MsoNormal><span style='font-family:"Courier New"'>Thanks,</span><o:p></o:p></p><div><p class=MsoNormal><span style='font-family:"Courier New"'>-Jiangning</span><o:p></o:p></p></div></div></div></div></body></html>