<div dir="ltr"><span style="font-family:arial,sans-serif;font-size:13px">+ assert(0 && "Not 16-bit, 32-bit or 64-bit mode!");</span><div><span style="font-family:arial,sans-serif;font-size:13px"><br></span></div>
<div><span style="font-family:arial,sans-serif;font-size:13px">This should be llvm_unreachable("</span><span style="font-family:arial,sans-serif;font-size:13px">Not 16-bit, 32-bit or 64-bit mode!");</span></div>
<div><span style="font-family:arial,sans-serif;font-size:13px"><br></span></div><div><span style="font-family:arial,sans-serif;font-size:13px">The optimizers get to have more fun with that.</span></div></div><div class="gmail_extra">
<br><br><div class="gmail_quote">On Sun, Jan 5, 2014 at 6:34 PM, David Woodhouse <span dir="ltr"><<a href="mailto:dwmw2@infradead.org" target="_blank">dwmw2@infradead.org</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">
<div class="im">On Sun, 2014-01-05 at 17:22 -0600, Craig Topper wrote:<br>
> Looking again, I think In16BitMode in the subtarget is also<br>
> unitialized. It needs to be set to false by the X86Subtarget<br>
> constructor.<br>
<br>
</div>Ah, right. How's this version? I think I captured everything you<br>
mentioned...?<br>
<br>
>From 9ea3cf8ed4e1d32d3b50d380715bac6087bf7e6d Mon Sep 17 00:00:00 2001<br>
From: David Woodhouse <<a href="mailto:David.Woodhouse@intel.com">David.Woodhouse@intel.com</a>><br>
Date: Fri, 13 Dec 2013 13:10:33 +0000<br>
Subject: [PATCH] Add basic support for .code16<br>
<br>
This is not really expected to work right yet. Mostly because we will<br>
still emit the OpSize (0x66) prefix in all the wrong places, along with<br>
a number of other corner cases. Those will all be fixed in the subsequent<br>
commits.<br>
<br>
Review feedback suggested that the best approach was to enable this<br>
incrementally with progressive test cases, rather than a series of<br>
preparatory work followed by flipping the switch to actually accept<br>
".code16" at the end.<br>
---<br>
lib/Target/X86/AsmParser/X86AsmParser.cpp | 42 +++-<br>
lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp | 12 +-<br>
lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp | 4 +-<br>
lib/Target/X86/X86.td | 4 +<br>
lib/Target/X86/X86InstrInfo.td | 6 +<br>
lib/Target/X86/X86Subtarget.cpp | 10 +-<br>
lib/Target/X86/X86Subtarget.h | 16 +-<br>
test/MC/X86/address-size.s | 8 +<br>
test/MC/X86/x86-16.s | 259 +++++++++++++++++++++++<br>
9 files changed, 344 insertions(+), 17 deletions(-)<br>
create mode 100644 test/MC/X86/x86-16.s<br>
<br>
diff --git a/lib/Target/X86/AsmParser/X86AsmParser.cpp b/lib/Target/X86/AsmParser/X86AsmParser.cpp<br>
index 0f8e9f7..d97ff75 100644<br>
--- a/lib/Target/X86/AsmParser/X86AsmParser.cpp<br>
+++ b/lib/Target/X86/AsmParser/X86AsmParser.cpp<br>
@@ -544,8 +544,18 @@ private:<br>
<div class="im"> // FIXME: Can tablegen auto-generate this?<br>
</div><div class="im"> return (STI.getFeatureBits() & X86::Mode64Bit) != 0;<br>
}<br>
</div>- void SwitchMode() {<br>
- unsigned FB = ComputeAvailableFeatures(STI.ToggleFeature(X86::Mode64Bit));<br>
+ bool is32BitMode() const {<br>
<div class="im">+ // FIXME: Can tablegen auto-generate this?<br>
</div>+ return (STI.getFeatureBits() & X86::Mode32Bit) != 0;<br>
+ }<br>
+ bool is16BitMode() const {<br>
<div class="im">+ // FIXME: Can tablegen auto-generate this?<br>
</div>+ return (STI.getFeatureBits() & X86::Mode16Bit) != 0;<br>
+ }<br>
+ void SwitchMode(uint64_t mode) {<br>
+ uint64_t oldMode = STI.getFeatureBits() &<br>
+ (X86::Mode64Bit | X86::Mode32Bit | X86::Mode16Bit);<br>
+ unsigned FB = ComputeAvailableFeatures(STI.ToggleFeature(oldMode | mode));<br>
setAvailableFeatures(FB);<br>
}<br>
<br>
@@ -1033,7 +1043,8 @@ struct X86Operand : public MCParsedAsmOperand {<br>
<div class="im"> } // end anonymous namespace.<br>
<br>
bool X86AsmParser::isSrcOp(X86Operand &Op) {<br>
- unsigned basereg = is64BitMode() ? X86::RSI : X86::ESI;<br>
+ unsigned basereg =<br>
</div>+ is64BitMode() ? X86::RSI : (is32BitMode() ? X86::ESI : X86::SI);<br>
<div class="im"><br>
return (Op.isMem() &&<br>
(Op.Mem.SegReg == 0 || Op.Mem.SegReg == X86::DS) &&<br>
</div>@@ -1043,7 +1054,8 @@ bool X86AsmParser::isSrcOp(X86Operand &Op) {<br>
<div class="im"> }<br>
<br>
bool X86AsmParser::isDstOp(X86Operand &Op) {<br>
- unsigned basereg = is64BitMode() ? X86::RDI : X86::EDI;<br>
+ unsigned basereg =<br>
</div>+ is64BitMode() ? X86::RDI : (is32BitMode() ? X86::EDI : X86::DI);<br>
<div class="im"><br>
return Op.isMem() &&<br>
(Op.Mem.SegReg == 0 || Op.Mem.SegReg == X86::ES) &&<br>
</div>@@ -1193,7 +1205,8 @@ X86AsmParser::CreateMemForInlineAsm(unsigned SegReg, const MCExpr *Disp,<br>
<div class="im"> // operand to ensure proper matching. Just pick a GPR based on the size of<br>
// a pointer.<br>
if (!Info.IsVarDecl) {<br>
- unsigned RegNo = is64BitMode() ? X86::RBX : X86::EBX;<br>
+ unsigned RegNo =<br>
</div>+ is64BitMode() ? X86::RBX : (is32BitMode() ? X86::EBX : X86::BX);<br>
<div class="im"> return X86Operand::CreateReg(RegNo, Start, End, /*AddressOf=*/true,<br>
SMLoc(), Identifier, Info.OpDecl);<br>
}<br>
</div>@@ -1612,7 +1625,8 @@ X86Operand *X86AsmParser::ParseIntelOffsetOfOperator() {<br>
<div class="im"> // The offset operator will have an 'r' constraint, thus we need to create<br>
// register operand to ensure proper matching. Just pick a GPR based on<br>
// the size of a pointer.<br>
- unsigned RegNo = is64BitMode() ? X86::RBX : X86::EBX;<br>
+ unsigned RegNo =<br>
</div>+ is64BitMode() ? X86::RBX : (is32BitMode() ? X86::EBX : X86::BX);<br>
<div class="im"> return X86Operand::CreateReg(RegNo, Start, End, /*GetAddress=*/true,<br>
OffsetOfLoc, Identifier, Info.OpDecl);<br>
}<br>
</div>@@ -2679,18 +2693,24 @@ bool X86AsmParser::ParseDirectiveWord(unsigned Size, SMLoc L) {<br>
}<br>
<br>
/// ParseDirectiveCode<br>
-/// ::= .code32 | .code64<br>
+/// ::= .code16 | .code32 | .code64<br>
<div class="im"> bool X86AsmParser::ParseDirectiveCode(StringRef IDVal, SMLoc L) {<br>
- if (IDVal == ".code32") {<br>
+ if (IDVal == ".code16") {<br>
+ Parser.Lex();<br>
+ if (!is16BitMode()) {<br>
</div>+ SwitchMode(X86::Mode16Bit);<br>
<div class="im">+ getParser().getStreamer().EmitAssemblerFlag(MCAF_Code16);<br>
+ }<br>
+ } else if (IDVal == ".code32") {<br>
Parser.Lex();<br>
</div>- if (is64BitMode()) {<br>
- SwitchMode();<br>
+ if (!is32BitMode()) {<br>
+ SwitchMode(X86::Mode32Bit);<br>
<div class="im"> getParser().getStreamer().EmitAssemblerFlag(MCAF_Code32);<br>
}<br>
} else if (IDVal == ".code64") {<br>
Parser.Lex();<br>
if (!is64BitMode()) {<br>
- SwitchMode();<br>
</div>+ SwitchMode(X86::Mode64Bit);<br>
<div class="im"> getParser().getStreamer().EmitAssemblerFlag(MCAF_Code64);<br>
}<br>
} else {<br>
diff --git a/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp b/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp<br>
</div>index 293541a..5b59cb6 100644<br>
--- a/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp<br>
+++ b/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp<br>
@@ -49,7 +49,12 @@ public:<br>
<br>
bool is32BitMode() const {<br>
<div class="im"> // FIXME: Can tablegen auto-generate this?<br>
- return (STI.getFeatureBits() & X86::Mode64Bit) == 0;<br>
</div>+ return (STI.getFeatureBits() & X86::Mode32Bit) != 0;<br>
+ }<br>
+<br>
+ bool is16BitMode() const {<br>
<div class="im">+ // FIXME: Can tablegen auto-generate this?<br>
</div><div class="im">+ return (STI.getFeatureBits() & X86::Mode16Bit) != 0;<br>
}<br>
<br>
unsigned GetX86RegNum(const MCOperand &MO) const {<br>
</div>@@ -1177,13 +1182,16 @@ void X86MCCodeEmitter::EmitOpcodePrefix(uint64_t TSFlags, unsigned &CurByte,<br>
<div class="im"> assert(!Is64BitMemOperand(MI, MemOperand));<br>
need_address_override = Is16BitMemOperand(MI, MemOperand);<br>
} else {<br>
</div>- need_address_override = false;<br>
+ assert(is16BitMode() && "Not 16-bit, 32-bit or 64-bit mode!");<br>
<div class="im">+ assert(!Is64BitMemOperand(MI, MemOperand));<br>
+ need_address_override = !Is16BitMemOperand(MI, MemOperand);<br>
}<br>
<br>
</div> if (need_address_override)<br>
<div class="im"> EmitByte(0x67, CurByte, OS);<br>
<br>
// Emit the operand size opcode prefix as needed.<br>
+ // FIXME for is16BitMode().<br>
if (TSFlags & X86II::OpSize)<br>
EmitByte(0x66, CurByte, OS);<br>
<br>
</div>diff --git a/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp b/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp<br>
index 403e50d..40b1be0 100644<br>
--- a/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp<br>
+++ b/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp<br>
<div class="im">@@ -47,9 +47,9 @@ std::string X86_MC::ParseX86Triple(StringRef TT) {<br>
Triple TheTriple(TT);<br>
std::string FS;<br>
if (TheTriple.getArch() == Triple::x86_64)<br>
- FS = "+64bit-mode";<br>
+ FS = "+64bit-mode,-32bit-mode";<br>
else<br>
- FS = "-64bit-mode";<br>
+ FS = "-64bit-mode,+32bit-mode";<br>
return FS;<br>
}<br>
<br>
</div>diff --git a/lib/Target/X86/X86.td b/lib/Target/X86/X86.td<br>
index d55178e..e755fae 100644<br>
--- a/lib/Target/X86/X86.td<br>
+++ b/lib/Target/X86/X86.td<br>
@@ -22,6 +22,10 @@ include "llvm/Target/Target.td"<br>
<div class="im"><br>
def Mode64Bit : SubtargetFeature<"64bit-mode", "In64BitMode", "true",<br>
"64-bit mode (x86_64)">;<br>
</div>+def Mode32Bit : SubtargetFeature<"32bit-mode", "In32BitMode", "true",<br>
+ "32-bit mode (80386)">;<br>
<div class="im">+def Mode16Bit : SubtargetFeature<"16bit-mode", "In16BitMode", "true",<br>
+ "16-bit mode (i8086)">;<br>
<br>
//===----------------------------------------------------------------------===//<br>
// X86 Subtarget features<br>
</div>diff --git a/lib/Target/X86/X86InstrInfo.td b/lib/Target/X86/X86InstrInfo.td<br>
index 707a313..9642a89 100644<br>
--- a/lib/Target/X86/X86InstrInfo.td<br>
+++ b/lib/Target/X86/X86InstrInfo.td<br>
@@ -700,6 +700,12 @@ def Not64BitMode : Predicate<"!Subtarget->is64Bit()">,<br>
AssemblerPredicate<"!Mode64Bit", "Not 64-bit mode">;<br>
def In64BitMode : Predicate<"Subtarget->is64Bit()">,<br>
AssemblerPredicate<"Mode64Bit", "64-bit mode">;<br>
+def In16BitMode : Predicate<"Subtarget->is16Bit()">,<br>
+ AssemblerPredicate<"Mode16Bit", "16-bit mode">;<br>
+def Not16BitMode : Predicate<"!Subtarget->is16Bit()">,<br>
+ AssemblerPredicate<"!Mode16Bit", "Not 16-bit mode">;<br>
+def In32BitMode : Predicate<"Subtarget->is32Bit()">,<br>
+ AssemblerPredicate<"Mode32Bit", "32-bit mode">;<br>
def IsWin64 : Predicate<"Subtarget->isTargetWin64()">;<br>
def IsNaCl : Predicate<"Subtarget->isTargetNaCl()">;<br>
def NotNaCl : Predicate<"!Subtarget->isTargetNaCl()">;<br>
diff --git a/lib/Target/X86/X86Subtarget.cpp b/lib/Target/X86/X86Subtarget.cpp<br>
index 597fccb..ea8bc25 100644<br>
--- a/lib/Target/X86/X86Subtarget.cpp<br>
+++ b/lib/Target/X86/X86Subtarget.cpp<br>
@@ -482,6 +482,12 @@ void X86Subtarget::resetSubtargetFeatures(StringRef CPU, StringRef FS) {<br>
// target data structure which is shared with MC code emitter, etc.<br>
if (In64BitMode)<br>
ToggleFeature(X86::Mode64Bit);<br>
+ else if (In32BitMode)<br>
+ ToggleFeature(X86::Mode32Bit);<br>
+ else if (In16BitMode)<br>
+ ToggleFeature(X86::Mode16Bit);<br>
+ else<br>
+ assert(0 && "Not 16-bit, 32-bit or 64-bit mode!");<br>
<br>
DEBUG(dbgs() << "Subtarget features: SSELevel " << X86SSELevel<br>
<< ", 3DNowLevel " << X863DNowLevel<br>
@@ -551,7 +557,9 @@ X86Subtarget::X86Subtarget(const std::string &TT, const std::string &CPU,<br>
, PICStyle(PICStyles::None)<br>
, TargetTriple(TT)<br>
, StackAlignOverride(StackAlignOverride)<br>
- , In64BitMode(is64Bit) {<br>
+ , In64BitMode(is64Bit)<br>
+ , In32BitMode(!is64Bit)<br>
+ , In16BitMode(false) {<br>
initializeEnvironment();<br>
resetSubtargetFeatures(CPU, FS);<br>
}<br>
diff --git a/lib/Target/X86/X86Subtarget.h b/lib/Target/X86/X86Subtarget.h<br>
index 93d251a..f39389e 100644<br>
--- a/lib/Target/X86/X86Subtarget.h<br>
+++ b/lib/Target/X86/X86Subtarget.h<br>
@@ -205,9 +205,15 @@ private:<br>
<div class="im"> /// StackAlignOverride - Override the stack alignment.<br>
unsigned StackAlignOverride;<br>
<br>
- /// In64BitMode - True if compiling for 64-bit, false for 32-bit.<br>
</div>+ /// In64BitMode - True if compiling for 64-bit, false for 16-bit or 32-bit.<br>
bool In64BitMode;<br>
<br>
+ /// In32BitMode - True if compiling for 32-bit, false for 16-bit or 64-bit.<br>
+ bool In32BitMode;<br>
+<br>
+ /// In16BitMode - True if compiling for 16-bit, false for 32-bit or 64-bit.<br>
<div class="im">+ bool In16BitMode;<br>
+<br>
public:<br>
/// This constructor initializes the data members to match that<br>
/// of the specified triple.<br>
</div>@@ -244,6 +250,14 @@ public:<br>
return In64BitMode;<br>
}<br>
<br>
+ bool is32Bit() const {<br>
+ return In32BitMode;<br>
+ }<br>
<div class="im">+<br>
+ bool is16Bit() const {<br>
+ return In16BitMode;<br>
+ }<br>
+<br>
/// Is this x86_64 with the ILP32 programming model (x32 ABI)?<br>
bool isTarget64BitILP32() const {<br>
return In64BitMode && (TargetTriple.getEnvironment() == Triple::GNUX32 ||<br>
</div>diff --git a/test/MC/X86/address-size.s b/test/MC/X86/address-size.s<br>
index 936cd57..c9d04c4 100644<br>
--- a/test/MC/X86/address-size.s<br>
+++ b/test/MC/X86/address-size.s<br>
@@ -17,3 +17,11 @@<br>
// CHECK: encoding: [0x67,0xc7,0x00,0x78,0x56,0x34,0x12]<br>
movw $0x1234, 0x5678(%bp)<br>
// CHECK: encoding: [0x67,0x66,0xc7,0x86,0x78,0x56,0x34,0x12]<br>
+<br>
+ .code16<br>
+ movb $0x0, (%si)<br>
+// CHECK: encoding: [0xc6,0x04,0x00]<br>
+ movb $0x0, (%esi)<br>
+// CHECK: encoding: [0x67,0xc6,0x06,0x00]<br>
+ movb $0x5a, (%di,%bp,1)<br>
+// CHECK: encoding: [0xc6,0x03,0x5a]<br>
diff --git a/test/MC/X86/x86-16.s b/test/MC/X86/x86-16.s<br>
new file mode 100644<br>
index 0000000..36f3b19<br>
--- /dev/null<br>
+++ b/test/MC/X86/x86-16.s<br>
@@ -0,0 +1,259 @@<br>
+// RUN: llvm-mc -triple i386-unknown-unknown --show-encoding %s | FileCheck %s<br>
+<br>
+ .code16<br>
+<br>
+ pause<br>
+// CHECK: pause<br>
+// CHECK: encoding: [0xf3,0x90]<br>
+ sfence<br>
+// CHECK: sfence<br>
+// CHECK: encoding: [0x0f,0xae,0xf8]<br>
+ lfence<br>
+// CHECK: lfence<br>
+// CHECK: encoding: [0x0f,0xae,0xe8]<br>
+ mfence<br>
+ stgi<br>
+// CHECK: stgi<br>
+// CHECK: encoding: [0x0f,0x01,0xdc]<br>
+ clgi<br>
+// CHECK: clgi<br>
+// CHECK: encoding: [0x0f,0x01,0xdd]<br>
+<br>
+ rdtscp<br>
+// CHECK: rdtscp<br>
+// CHECK: encoding: [0x0f,0x01,0xf9]<br>
+<br>
+<br>
+// CHECK: testb %bl, %cl # encoding: [0x84,0xcb]<br>
+ testb %bl, %cl<br>
+<br>
+into<br>
+// CHECK: into<br>
+// CHECK: encoding: [0xce]<br>
+int3<br>
+// CHECK: int3<br>
+// CHECK: encoding: [0xcc]<br>
+int $4<br>
+// CHECK: int $4<br>
+// CHECK: encoding: [0xcd,0x04]<br>
+int $255<br>
+// CHECK: int $255<br>
+// CHECK: encoding: [0xcd,0xff]<br>
+<br>
+// CHECK: fmul %st(0)<br>
+// CHECK: encoding: [0xd8,0xc8]<br>
+ fmul %st(0), %st<br>
+<br>
+// CHECK: fadd %st(0)<br>
+// CHECK: encoding: [0xd8,0xc0]<br>
+ fadd %st(0), %st<br>
+<br>
+// CHECK: fsub %st(0)<br>
+// CHECK: encoding: [0xd8,0xe0]<br>
+ fsub %st(0), %st<br>
+<br>
+// CHECK: fsubr %st(0)<br>
+// CHECK: encoding: [0xd8,0xe8]<br>
+ fsubr %st(0), %st<br>
+<br>
+// CHECK: fdivr %st(0)<br>
+// CHECK: encoding: [0xd8,0xf8]<br>
+ fdivr %st(0), %st<br>
+<br>
+// CHECK: fdiv %st(0)<br>
+// CHECK: encoding: [0xd8,0xf0]<br>
+ fdiv %st(0), %st<br>
+<br>
+// CHECK: wait<br>
+// CHECK: encoding: [0x9b]<br>
+ fwait<br>
+<br>
+<br>
+ setc %bl<br>
+ setnae %bl<br>
+ setnb %bl<br>
+ setnc %bl<br>
+ setna %bl<br>
+ setnbe %bl<br>
+ setpe %bl<br>
+ setpo %bl<br>
+ setnge %bl<br>
+ setnl %bl<br>
+ setng %bl<br>
+ setnle %bl<br>
+<br>
+ setneb %cl // CHECK: setne %cl<br>
+ setcb %bl // CHECK: setb %bl<br>
+ setnaeb %bl // CHECK: setb %bl<br>
+<br>
+<br>
+// CHECK: lcalll $31438, $31438<br>
+// CHECK: lcalll $31438, $31438<br>
+// CHECK: ljmpl $31438, $31438<br>
+// CHECK: ljmpl $31438, $31438<br>
+<br>
+calll $0x7ace,$0x7ace<br>
+lcalll $0x7ace,$0x7ace<br>
+jmpl $0x7ace,$0x7ace<br>
+ljmpl $0x7ace,$0x7ace<br>
+<br>
+// CHECK: calll a<br>
+ calll a<br>
+<br>
+// CHECK: incb %al # encoding: [0xfe,0xc0]<br>
+ incb %al<br>
+<br>
+// CHECK: decb %al # encoding: [0xfe,0xc8]<br>
+ decb %al<br>
+<br>
+// CHECK: pshufw $14, %mm4, %mm0 # encoding: [0x0f,0x70,0xc4,0x0e]<br>
+pshufw $14, %mm4, %mm0<br>
+<br>
+// CHECK: pshufw $90, %mm4, %mm0 # encoding: [0x0f,0x70,0xc4,0x5a]<br>
+pshufw $90, %mm4, %mm0<br>
+<br>
+// CHECK: aaa<br>
+// CHECK: encoding: [0x37]<br>
+ aaa<br>
+<br>
+// CHECK: aad $1<br>
+// CHECK: encoding: [0xd5,0x01]<br>
+ aad $1<br>
+<br>
+// CHECK: aad<br>
+// CHECK: encoding: [0xd5,0x0a]<br>
+ aad $0xA<br>
+<br>
+// CHECK: aad<br>
+// CHECK: encoding: [0xd5,0x0a]<br>
+ aad<br>
+<br>
+// CHECK: aam $2<br>
+// CHECK: encoding: [0xd4,0x02]<br>
+ aam $2<br>
+<br>
+// CHECK: aam<br>
+// CHECK: encoding: [0xd4,0x0a]<br>
+ aam $0xA<br>
+<br>
+// CHECK: aam<br>
+// CHECK: encoding: [0xd4,0x0a]<br>
+ aam<br>
+<br>
+// CHECK: aas<br>
+// CHECK: encoding: [0x3f]<br>
+ aas<br>
+<br>
+// CHECK: daa<br>
+// CHECK: encoding: [0x27]<br>
+ daa<br>
+<br>
+// CHECK: das<br>
+// CHECK: encoding: [0x2f]<br>
+ das<br>
+<br>
+// CHECK: arpl %bx, %bx<br>
+// CHECK: encoding: [0x63,0xdb]<br>
+ arpl %bx,%bx<br>
+<br>
+// CHECK: arpl %bx, 6(%ecx)<br>
+// CHECK: encoding: [0x67,0x63,0x59,0x06]<br>
+ arpl %bx,6(%ecx)<br>
+<br>
+// CHECK: fcompi %st(2)<br>
+// CHECK: encoding: [0xdf,0xf2]<br>
+ fcompi %st(2), %st<br>
+<br>
+// CHECK: fcompi %st(2)<br>
+// CHECK: encoding: [0xdf,0xf2]<br>
+ fcompi %st(2)<br>
+<br>
+// CHECK: fcompi<br>
+// CHECK: encoding: [0xdf,0xf1]<br>
+ fcompi<br>
+<br>
+// CHECK: fucompi %st(2)<br>
+// CHECK: encoding: [0xdf,0xea]<br>
+ fucompi %st(2),%st<br>
+<br>
+// CHECK: fucompi %st(2)<br>
+// CHECK: encoding: [0xdf,0xea]<br>
+ fucompi %st(2)<br>
+<br>
+// CHECK: fucompi<br>
+// CHECK: encoding: [0xdf,0xe9]<br>
+ fucompi<br>
+<br>
+// CHECK: wait<br>
+// CHECK: encoding: [0x9b]<br>
+ fclex<br>
+<br>
+// CHECK: fnclex<br>
+// CHECK: encoding: [0xdb,0xe2]<br>
+ fnclex<br>
+<br>
+// CHECK: ud2<br>
+// CHECK: encoding: [0x0f,0x0b]<br>
+ ud2<br>
+<br>
+// CHECK: ud2<br>
+// CHECK: encoding: [0x0f,0x0b]<br>
+ ud2a<br>
+<br>
+// CHECK: ud2b<br>
+// CHECK: encoding: [0x0f,0xb9]<br>
+ ud2b<br>
+<br>
+// CHECK: loope 0<br>
+// CHECK: encoding: [0xe1,A]<br>
+ loopz 0<br>
+<br>
+// CHECK: loopne 0<br>
+// CHECK: encoding: [0xe0,A]<br>
+ loopnz 0<br>
+<br>
+// CHECK: outsb # encoding: [0x6e]<br>
+// CHECK: outsb<br>
+// CHECK: outsb<br>
+ outsb<br>
+ outsb %ds:(%si), %dx<br>
+ outsb (%si), %dx<br>
+<br>
+// CHECK: insb # encoding: [0x6c]<br>
+// CHECK: insb<br>
+ insb<br>
+ insb %dx, %es:(%di)<br>
+<br>
+// CHECK: movsb # encoding: [0xa4]<br>
+// CHECK: movsb<br>
+// CHECK: movsb<br>
+ movsb<br>
+ movsb %ds:(%si), %es:(%di)<br>
+ movsb (%si), %es:(%di)<br>
+<br>
+// CHECK: lodsb # encoding: [0xac]<br>
+// CHECK: lodsb<br>
+// CHECK: lodsb<br>
+// CHECK: lodsb<br>
+// CHECK: lodsb<br>
+ lodsb<br>
+ lodsb %ds:(%si), %al<br>
+ lodsb (%si), %al<br>
+ lods %ds:(%si), %al<br>
+ lods (%si), %al<br>
+<br>
+// CHECK: stosb # encoding: [0xaa]<br>
+// CHECK: stosb<br>
+// CHECK: stosb<br>
+ stosb<br>
+ stosb %al, %es:(%di)<br>
+ stos %al, %es:(%di)<br>
+<br>
+// CHECK: fsubp<br>
+// CHECK: encoding: [0xde,0xe1]<br>
+fsubp %st,%st(1)<br>
+<br>
+// CHECK: fsubp %st(2)<br>
+// CHECK: encoding: [0xde,0xe2]<br>
+fsubp %st, %st(2)<br>
+<br>
<span class="HOEnZb"><font color="#888888">--<br>
1.8.3.1<br>
<br>
<br>
<br>
--<br>
dwmw2<br>
<br>
</font></span></blockquote></div><br><br clear="all"><div><br></div>-- <br>~Craig
</div>