<div dir="ltr">If we approached this from another direction and inverted the normal OpSize bit in 16-bit mode, how many instructions would break?</div><div class="gmail_extra"><br><br><div class="gmail_quote">On Fri, Dec 20, 2013 at 8:58 AM, David Woodhouse <span dir="ltr"><<a href="mailto:dwmw2@infradead.org" target="_blank">dwmw2@infradead.org</a>></span> wrote:<br>
<blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">From: David Woodhouse <<a href="mailto:David.Woodhouse@intel.com">David.Woodhouse@intel.com</a>><br>
<br>
This fixes the bulk of 16-bit output, and the corresponding test case<br>
x86-16.s now looks mostly like the x86-32.s test case that it was<br>
originally based on. A few irrelevant instructions have been dropped,<br>
and there are still some corner cases to be fixed in subsequent patches.<br>
---<br>
lib/Target/X86/X86InstrArithmetic.td | 71 +++++----<br>
lib/Target/X86/X86InstrCMovSetCC.td | 5 +-<br>
lib/Target/X86/X86InstrCompiler.td | 18 +--<br>
lib/Target/X86/X86InstrControl.td | 26 ++--<br>
lib/Target/X86/X86InstrInfo.td | 149 ++++++++++--------<br>
lib/Target/X86/X86InstrShiftRotate.td | 103 +++++++------<br>
lib/Target/X86/X86InstrSystem.td | 105 +++++++------<br>
test/MC/X86/x86-16.s | 277 ++++++++++++++++++++++++++++++++++<br>
8 files changed, 537 insertions(+), 217 deletions(-)<br>
<br>
diff --git a/lib/Target/X86/X86InstrArithmetic.td b/lib/Target/X86/X86InstrArithmetic.td<br>
index b8d7f9a..18a6192 100644<br>
--- a/lib/Target/X86/X86InstrArithmetic.td<br>
+++ b/lib/Target/X86/X86InstrArithmetic.td<br>
@@ -24,7 +24,7 @@ def LEA32r : I<0x8D, MRMSrcMem,<br>
(outs GR32:$dst), (ins i32mem:$src),<br>
"lea{l}\t{$src|$dst}, {$dst|$src}",<br>
[(set GR32:$dst, lea32addr:$src)], IIC_LEA>,<br>
- Requires<[Not64BitMode]>;<br>
+ OpSize16, Requires<[Not64BitMode]>;<br>
<br>
def LEA64_32r : I<0x8D, MRMSrcMem,<br>
(outs GR32:$dst), (ins lea64_32mem:$src),<br>
@@ -74,7 +74,7 @@ let Defs = [EAX,EDX,EFLAGS], Uses = [EAX], neverHasSideEffects = 1 in<br>
def MUL32r : I<0xF7, MRM4r, (outs), (ins GR32:$src),<br>
"mul{l}\t$src",<br>
[/*(set EAX, EDX, EFLAGS, (X86umul_flag EAX, GR32:$src))*/],<br>
- IIC_MUL32_REG>, Sched<[WriteIMul]>;<br>
+ IIC_MUL32_REG>, OpSize16, Sched<[WriteIMul]>;<br>
// RAX,RDX = RAX*GR64<br>
let Defs = [RAX,RDX,EFLAGS], Uses = [RAX], neverHasSideEffects = 1 in<br>
def MUL64r : RI<0xF7, MRM4r, (outs), (ins GR64:$src),<br>
@@ -100,7 +100,7 @@ def MUL16m : I<0xF7, MRM4m, (outs), (ins i16mem:$src),<br>
let Defs = [EAX,EDX,EFLAGS], Uses = [EAX] in<br>
def MUL32m : I<0xF7, MRM4m, (outs), (ins i32mem:$src),<br>
"mul{l}\t$src",<br>
- [], IIC_MUL32_MEM>, SchedLoadReg<WriteIMulLd>;<br>
+ [], IIC_MUL32_MEM>, OpSize16, SchedLoadReg<WriteIMulLd>;<br>
// RAX,RDX = RAX*[mem64]<br>
let Defs = [RAX,RDX,EFLAGS], Uses = [RAX] in<br>
def MUL64m : RI<0xF7, MRM4m, (outs), (ins i64mem:$src),<br>
@@ -119,7 +119,7 @@ def IMUL16r : I<0xF7, MRM5r, (outs), (ins GR16:$src), "imul{w}\t$src", [],<br>
// EAX,EDX = EAX*GR32<br>
let Defs = [EAX,EDX,EFLAGS], Uses = [EAX] in<br>
def IMUL32r : I<0xF7, MRM5r, (outs), (ins GR32:$src), "imul{l}\t$src", [],<br>
- IIC_IMUL32_RR>, Sched<[WriteIMul]>;<br>
+ IIC_IMUL32_RR>, OpSize16, Sched<[WriteIMul]>;<br>
// RAX,RDX = RAX*GR64<br>
let Defs = [RAX,RDX,EFLAGS], Uses = [RAX] in<br>
def IMUL64r : RI<0xF7, MRM5r, (outs), (ins GR64:$src), "imul{q}\t$src", [],<br>
@@ -138,7 +138,8 @@ def IMUL16m : I<0xF7, MRM5m, (outs), (ins i16mem:$src),<br>
// EAX,EDX = EAX*[mem32]<br>
let Defs = [EAX,EDX,EFLAGS], Uses = [EAX] in<br>
def IMUL32m : I<0xF7, MRM5m, (outs), (ins i32mem:$src),<br>
- "imul{l}\t$src", [], IIC_IMUL32_MEM>, SchedLoadReg<WriteIMulLd>;<br>
+ "imul{l}\t$src", [], IIC_IMUL32_MEM>, OpSize16,<br>
+ SchedLoadReg<WriteIMulLd>;<br>
// RAX,RDX = RAX*[mem64]<br>
let Defs = [RAX,RDX,EFLAGS], Uses = [RAX] in<br>
def IMUL64m : RI<0xF7, MRM5m, (outs), (ins i64mem:$src),<br>
@@ -162,7 +163,7 @@ def IMUL32rr : I<0xAF, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src1,GR32:$src2),<br>
"imul{l}\t{$src2, $dst|$dst, $src2}",<br>
[(set GR32:$dst, EFLAGS,<br>
(X86smul_flag GR32:$src1, GR32:$src2))], IIC_IMUL32_RR>,<br>
- TB;<br>
+ TB, OpSize16;<br>
def IMUL64rr : RI<0xAF, MRMSrcReg, (outs GR64:$dst),<br>
(ins GR64:$src1, GR64:$src2),<br>
"imul{q}\t{$src2, $dst|$dst, $src2}",<br>
@@ -186,7 +187,7 @@ def IMUL32rm : I<0xAF, MRMSrcMem, (outs GR32:$dst),<br>
[(set GR32:$dst, EFLAGS,<br>
(X86smul_flag GR32:$src1, (load addr:$src2)))],<br>
IIC_IMUL32_RM>,<br>
- TB;<br>
+ TB, OpSize16;<br>
def IMUL64rm : RI<0xAF, MRMSrcMem, (outs GR64:$dst),<br>
(ins GR64:$src1, i64mem:$src2),<br>
"imul{q}\t{$src2, $dst|$dst, $src2}",<br>
@@ -221,13 +222,13 @@ def IMUL32rri : Ii32<0x69, MRMSrcReg, // GR32 = GR32*I32<br>
"imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",<br>
[(set GR32:$dst, EFLAGS,<br>
(X86smul_flag GR32:$src1, imm:$src2))],<br>
- IIC_IMUL32_RRI>;<br>
+ IIC_IMUL32_RRI>, OpSize16;<br>
def IMUL32rri8 : Ii8<0x6B, MRMSrcReg, // GR32 = GR32*I8<br>
(outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),<br>
"imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",<br>
[(set GR32:$dst, EFLAGS,<br>
(X86smul_flag GR32:$src1, i32immSExt8:$src2))],<br>
- IIC_IMUL32_RRI>;<br>
+ IIC_IMUL32_RRI>, OpSize16;<br>
def IMUL64rri32 : RIi32<0x69, MRMSrcReg, // GR64 = GR64*I32<br>
(outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2),<br>
"imul{q}\t{$src2, $src1, $dst|$dst, $src1, $src2}",<br>
@@ -263,14 +264,14 @@ def IMUL32rmi : Ii32<0x69, MRMSrcMem, // GR32 = [mem32]*I32<br>
"imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",<br>
[(set GR32:$dst, EFLAGS,<br>
(X86smul_flag (load addr:$src1), imm:$src2))],<br>
- IIC_IMUL32_RMI>;<br>
+ IIC_IMUL32_RMI>, OpSize16;<br>
def IMUL32rmi8 : Ii8<0x6B, MRMSrcMem, // GR32 = [mem32]*I8<br>
(outs GR32:$dst), (ins i32mem:$src1, i32i8imm: $src2),<br>
"imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",<br>
[(set GR32:$dst, EFLAGS,<br>
(X86smul_flag (load addr:$src1),<br>
i32immSExt8:$src2))],<br>
- IIC_IMUL32_RMI>;<br>
+ IIC_IMUL32_RMI>, OpSize16;<br>
def IMUL64rmi32 : RIi32<0x69, MRMSrcMem, // GR64 = [mem64]*I32<br>
(outs GR64:$dst), (ins i64mem:$src1, i64i32imm:$src2),<br>
"imul{q}\t{$src2, $src1, $dst|$dst, $src1, $src2}",<br>
@@ -302,7 +303,7 @@ def DIV16r : I<0xF7, MRM6r, (outs), (ins GR16:$src), // DX:AX/r16 = AX,DX<br>
"div{w}\t$src", [], IIC_DIV16>, OpSize;<br>
let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in<br>
def DIV32r : I<0xF7, MRM6r, (outs), (ins GR32:$src), // EDX:EAX/r32 = EAX,EDX<br>
- "div{l}\t$src", [], IIC_DIV32>;<br>
+ "div{l}\t$src", [], IIC_DIV32>, OpSize16;<br>
// RDX:RAX/r64 = RAX,RDX<br>
let Defs = [RAX,RDX,EFLAGS], Uses = [RAX,RDX] in<br>
def DIV64r : RI<0xF7, MRM6r, (outs), (ins GR64:$src),<br>
@@ -321,7 +322,7 @@ def DIV16m : I<0xF7, MRM6m, (outs), (ins i16mem:$src), // DX:AX/[mem16] = AX,DX<br>
let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in // EDX:EAX/[mem32] = EAX,EDX<br>
def DIV32m : I<0xF7, MRM6m, (outs), (ins i32mem:$src),<br>
"div{l}\t$src", [], IIC_DIV32>,<br>
- SchedLoadReg<WriteIDivLd>;<br>
+ SchedLoadReg<WriteIDivLd>, OpSize16;<br>
// RDX:RAX/[mem64] = RAX,RDX<br>
let Defs = [RAX,RDX,EFLAGS], Uses = [RAX,RDX] in<br>
def DIV64m : RI<0xF7, MRM6m, (outs), (ins i64mem:$src),<br>
@@ -339,7 +340,7 @@ def IDIV16r: I<0xF7, MRM7r, (outs), (ins GR16:$src), // DX:AX/r16 = AX,DX<br>
"idiv{w}\t$src", [], IIC_IDIV16>, OpSize;<br>
let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in<br>
def IDIV32r: I<0xF7, MRM7r, (outs), (ins GR32:$src), // EDX:EAX/r32 = EAX,EDX<br>
- "idiv{l}\t$src", [], IIC_IDIV32>;<br>
+ "idiv{l}\t$src", [], IIC_IDIV32>, OpSize16;<br>
// RDX:RAX/r64 = RAX,RDX<br>
let Defs = [RAX,RDX,EFLAGS], Uses = [RAX,RDX] in<br>
def IDIV64r: RI<0xF7, MRM7r, (outs), (ins GR64:$src),<br>
@@ -357,7 +358,7 @@ def IDIV16m: I<0xF7, MRM7m, (outs), (ins i16mem:$src), // DX:AX/[mem16] = AX,DX<br>
SchedLoadReg<WriteIDivLd>;<br>
let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in // EDX:EAX/[mem32] = EAX,EDX<br>
def IDIV32m: I<0xF7, MRM7m, (outs), (ins i32mem:$src),<br>
- "idiv{l}\t$src", [], IIC_IDIV32>,<br>
+ "idiv{l}\t$src", [], IIC_IDIV32>, OpSize16,<br>
SchedLoadReg<WriteIDivLd>;<br>
let Defs = [RAX,RDX,EFLAGS], Uses = [RAX,RDX] in // RDX:RAX/[mem64] = RAX,RDX<br>
def IDIV64m: RI<0xF7, MRM7m, (outs), (ins i64mem:$src),<br>
@@ -385,7 +386,7 @@ def NEG16r : I<0xF7, MRM3r, (outs GR16:$dst), (ins GR16:$src1),<br>
def NEG32r : I<0xF7, MRM3r, (outs GR32:$dst), (ins GR32:$src1),<br>
"neg{l}\t$dst",<br>
[(set GR32:$dst, (ineg GR32:$src1)),<br>
- (implicit EFLAGS)], IIC_UNARY_REG>;<br>
+ (implicit EFLAGS)], IIC_UNARY_REG>, OpSize16;<br>
def NEG64r : RI<0xF7, MRM3r, (outs GR64:$dst), (ins GR64:$src1), "neg{q}\t$dst",<br>
[(set GR64:$dst, (ineg GR64:$src1)),<br>
(implicit EFLAGS)], IIC_UNARY_REG>;<br>
@@ -404,7 +405,7 @@ def NEG16m : I<0xF7, MRM3m, (outs), (ins i16mem:$dst),<br>
def NEG32m : I<0xF7, MRM3m, (outs), (ins i32mem:$dst),<br>
"neg{l}\t$dst",<br>
[(store (ineg (loadi32 addr:$dst)), addr:$dst),<br>
- (implicit EFLAGS)], IIC_UNARY_MEM>;<br>
+ (implicit EFLAGS)], IIC_UNARY_MEM>, OpSize16;<br>
def NEG64m : RI<0xF7, MRM3m, (outs), (ins i64mem:$dst), "neg{q}\t$dst",<br>
[(store (ineg (loadi64 addr:$dst)), addr:$dst),<br>
(implicit EFLAGS)], IIC_UNARY_MEM>;<br>
@@ -425,7 +426,7 @@ def NOT16r : I<0xF7, MRM2r, (outs GR16:$dst), (ins GR16:$src1),<br>
[(set GR16:$dst, (not GR16:$src1))], IIC_UNARY_REG>, OpSize;<br>
def NOT32r : I<0xF7, MRM2r, (outs GR32:$dst), (ins GR32:$src1),<br>
"not{l}\t$dst",<br>
- [(set GR32:$dst, (not GR32:$src1))], IIC_UNARY_REG>;<br>
+ [(set GR32:$dst, (not GR32:$src1))], IIC_UNARY_REG>, OpSize16;<br>
def NOT64r : RI<0xF7, MRM2r, (outs GR64:$dst), (ins GR64:$src1), "not{q}\t$dst",<br>
[(set GR64:$dst, (not GR64:$src1))], IIC_UNARY_REG>;<br>
}<br>
@@ -441,7 +442,8 @@ def NOT16m : I<0xF7, MRM2m, (outs), (ins i16mem:$dst),<br>
OpSize;<br>
def NOT32m : I<0xF7, MRM2m, (outs), (ins i32mem:$dst),<br>
"not{l}\t$dst",<br>
- [(store (not (loadi32 addr:$dst)), addr:$dst)], IIC_UNARY_MEM>;<br>
+ [(store (not (loadi32 addr:$dst)), addr:$dst)], IIC_UNARY_MEM>,<br>
+ OpSize16;<br>
def NOT64m : RI<0xF7, MRM2m, (outs), (ins i64mem:$dst), "not{q}\t$dst",<br>
[(store (not (loadi64 addr:$dst)), addr:$dst)], IIC_UNARY_MEM>;<br>
} // SchedRW<br>
@@ -465,7 +467,7 @@ def INC32r : I<0x40, AddRegFrm, (outs GR32:$dst), (ins GR32:$src1),<br>
"inc{l}\t$dst",<br>
[(set GR32:$dst, EFLAGS, (X86inc_flag GR32:$src1))],<br>
IIC_UNARY_REG>,<br>
- Requires<[Not64BitMode]>;<br>
+ OpSize16, Requires<[Not64BitMode]>;<br>
def INC64r : RI<0xFF, MRM0r, (outs GR64:$dst), (ins GR64:$src1), "inc{q}\t$dst",<br>
[(set GR64:$dst, EFLAGS, (X86inc_flag GR64:$src1))],<br>
IIC_UNARY_REG>;<br>
@@ -503,13 +505,13 @@ def INC32_16r : I<0xFF, MRM0r, (outs GR16:$dst), (ins GR16:$src1),<br>
OpSize, Requires<[Not64BitMode]>;<br>
def INC32_32r : I<0xFF, MRM0r, (outs GR32:$dst), (ins GR32:$src1),<br>
"inc{l}\t$dst", [], IIC_UNARY_REG>,<br>
- Requires<[Not64BitMode]>;<br>
+ OpSize16, Requires<[Not64BitMode]>;<br>
def DEC32_16r : I<0xFF, MRM1r, (outs GR16:$dst), (ins GR16:$src1),<br>
"dec{w}\t$dst", [], IIC_UNARY_REG>,<br>
OpSize, Requires<[Not64BitMode]>;<br>
def DEC32_32r : I<0xFF, MRM1r, (outs GR32:$dst), (ins GR32:$src1),<br>
"dec{l}\t$dst", [], IIC_UNARY_REG>,<br>
- Requires<[Not64BitMode]>;<br>
+ OpSize16, Requires<[Not64BitMode]>;<br>
} // isCodeGenOnly = 1, CodeSize = 2<br>
<br>
} // Constraints = "$src1 = $dst", SchedRW<br>
@@ -525,7 +527,7 @@ let CodeSize = 2, SchedRW = [WriteALULd, WriteRMW] in {<br>
def INC32m : I<0xFF, MRM0m, (outs), (ins i32mem:$dst), "inc{l}\t$dst",<br>
[(store (add (loadi32 addr:$dst), 1), addr:$dst),<br>
(implicit EFLAGS)], IIC_UNARY_MEM>,<br>
- Requires<[Not64BitMode]>;<br>
+ OpSize16, Requires<[Not64BitMode]>;<br>
def INC64m : RI<0xFF, MRM0m, (outs), (ins i64mem:$dst), "inc{q}\t$dst",<br>
[(store (add (loadi64 addr:$dst), 1), addr:$dst),<br>
(implicit EFLAGS)], IIC_UNARY_MEM>;<br>
@@ -567,7 +569,7 @@ def DEC32r : I<0x48, AddRegFrm, (outs GR32:$dst), (ins GR32:$src1),<br>
"dec{l}\t$dst",<br>
[(set GR32:$dst, EFLAGS, (X86dec_flag GR32:$src1))],<br>
IIC_UNARY_REG>,<br>
- Requires<[Not64BitMode]>;<br>
+ OpSize16, Requires<[Not64BitMode]>;<br>
def DEC64r : RI<0xFF, MRM1r, (outs GR64:$dst), (ins GR64:$src1), "dec{q}\t$dst",<br>
[(set GR64:$dst, EFLAGS, (X86dec_flag GR64:$src1))],<br>
IIC_UNARY_REG>;<br>
@@ -586,7 +588,7 @@ let CodeSize = 2, SchedRW = [WriteALULd, WriteRMW] in {<br>
def DEC32m : I<0xFF, MRM1m, (outs), (ins i32mem:$dst), "dec{l}\t$dst",<br>
[(store (add (loadi32 addr:$dst), -1), addr:$dst),<br>
(implicit EFLAGS)], IIC_UNARY_MEM>,<br>
- Requires<[Not64BitMode]>;<br>
+ OpSize16, Requires<[Not64BitMode]>;<br>
def DEC64m : RI<0xFF, MRM1m, (outs), (ins i64mem:$dst), "dec{q}\t$dst",<br>
[(store (add (loadi64 addr:$dst), -1), addr:$dst),<br>
(implicit EFLAGS)], IIC_UNARY_MEM>;<br>
@@ -600,7 +602,8 @@ class X86TypeInfo<ValueType vt, string instrsuffix, RegisterClass regclass,<br>
PatFrag loadnode, X86MemOperand memoperand, ImmType immkind,<br>
Operand immoperand, SDPatternOperator immoperator,<br>
Operand imm8operand, SDPatternOperator imm8operator,<br>
- bit hasOddOpcode, bit hasOpSizePrefix, bit hasREX_WPrefix> {<br>
+ bit hasOddOpcode, bit hasOpSizePrefix, bit hasOpSize16Prefix,<br>
+ bit hasREX_WPrefix> {<br>
/// VT - This is the value type itself.<br>
ValueType VT = vt;<br>
<br>
@@ -651,9 +654,14 @@ class X86TypeInfo<ValueType vt, string instrsuffix, RegisterClass regclass,<br>
bit HasOddOpcode = hasOddOpcode;<br>
<br>
/// HasOpSizePrefix - This bit is set to true if the instruction should have<br>
- /// the 0x66 operand size prefix. This is set for i16 types.<br>
+ /// the 0x66 operand size prefix in 32-bit or 64-bit modes. This is set for<br>
+ /// i16 types.<br>
bit HasOpSizePrefix = hasOpSizePrefix;<br>
<br>
+ /// HasOpSizePrefix - This bit is set to true if the instruction should have<br>
+ /// the 0x66 operand size prefix in 16-bit mode. This is set for i32 types.<br>
+ bit HasOpSize16Prefix = hasOpSize16Prefix;<br>
+<br>
/// HasREX_WPrefix - This bit is set to true if the instruction should have<br>
/// the 0x40 REX prefix. This is set for i64 types.<br>
bit HasREX_WPrefix = hasREX_WPrefix;<br>
@@ -664,16 +672,16 @@ def invalid_node : SDNode<"<<invalid_node>>", SDTIntLeaf,[],"<<invalid_node>>">;<br>
<br>
def Xi8 : X86TypeInfo<i8 , "b", GR8 , loadi8 , i8mem ,<br>
Imm8 , i8imm , imm, i8imm , invalid_node,<br>
- 0, 0, 0>;<br>
+ 0, 0, 0, 0>;<br>
def Xi16 : X86TypeInfo<i16, "w", GR16, loadi16, i16mem,<br>
Imm16, i16imm, imm, i16i8imm, i16immSExt8,<br>
- 1, 1, 0>;<br>
+ 1, 1, 0, 0>;<br>
def Xi32 : X86TypeInfo<i32, "l", GR32, loadi32, i32mem,<br>
Imm32, i32imm, imm, i32i8imm, i32immSExt8,<br>
- 1, 0, 0>;<br>
+ 1, 0, 1, 0>;<br>
def Xi64 : X86TypeInfo<i64, "q", GR64, loadi64, i64mem,<br>
Imm32, i64i32imm, i64immSExt32, i64i8imm, i64immSExt8,<br>
- 1, 0, 1>;<br>
+ 1, 0, 0, 1>;<br>
<br>
/// ITy - This instruction base class takes the type info for the instruction.<br>
/// Using this, it:<br>
@@ -694,6 +702,7 @@ class ITy<bits<8> opcode, Format f, X86TypeInfo typeinfo, dag outs, dag ins,<br>
<br>
// Infer instruction prefixes from type info.<br>
let hasOpSizePrefix = typeinfo.HasOpSizePrefix;<br>
+ let hasOpSize16Prefix = typeinfo.HasOpSize16Prefix;<br>
let hasREX_WPrefix = typeinfo.HasREX_WPrefix;<br>
}<br>
<br>
diff --git a/lib/Target/X86/X86InstrCMovSetCC.td b/lib/Target/X86/X86InstrCMovSetCC.td<br>
index a967a4d..6ea9c0e 100644<br>
--- a/lib/Target/X86/X86InstrCMovSetCC.td<br>
+++ b/lib/Target/X86/X86InstrCMovSetCC.td<br>
@@ -28,7 +28,7 @@ multiclass CMOV<bits<8> opc, string Mnemonic, PatLeaf CondNode> {<br>
!strconcat(Mnemonic, "{l}\t{$src2, $dst|$dst, $src2}"),<br>
[(set GR32:$dst,<br>
(X86cmov GR32:$src1, GR32:$src2, CondNode, EFLAGS))],<br>
- IIC_CMOV32_RR>, TB;<br>
+ IIC_CMOV32_RR>, TB, OpSize16;<br>
def NAME#64rr<br>
:RI<opc, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),<br>
!strconcat(Mnemonic, "{q}\t{$src2, $dst|$dst, $src2}"),<br>
@@ -49,7 +49,8 @@ multiclass CMOV<bits<8> opc, string Mnemonic, PatLeaf CondNode> {<br>
: I<opc, MRMSrcMem, (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),<br>
!strconcat(Mnemonic, "{l}\t{$src2, $dst|$dst, $src2}"),<br>
[(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),<br>
- CondNode, EFLAGS))], IIC_CMOV32_RM>, TB;<br>
+ CondNode, EFLAGS))], IIC_CMOV32_RM>,<br>
+ TB, OpSize16;<br>
def NAME#64rm<br>
:RI<opc, MRMSrcMem, (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),<br>
!strconcat(Mnemonic, "{q}\t{$src2, $dst|$dst, $src2}"),<br>
diff --git a/lib/Target/X86/X86InstrCompiler.td b/lib/Target/X86/X86InstrCompiler.td<br>
index 7bfcad0..6ba1099 100644<br>
--- a/lib/Target/X86/X86InstrCompiler.td<br>
+++ b/lib/Target/X86/X86InstrCompiler.td<br>
@@ -224,7 +224,7 @@ def MORESTACK_RET_RESTORE_R10 : I<0, Pseudo, (outs), (ins),<br>
let Defs = [EFLAGS], isReMaterializable = 1, isAsCheapAsAMove = 1,<br>
isCodeGenOnly = 1 in<br>
def MOV32r0 : I<0x31, MRMInitReg, (outs GR32:$dst), (ins), "",<br>
- [(set GR32:$dst, 0)], IIC_ALU_NONMEM>, Sched<[WriteZero]>;<br>
+ [(set GR32:$dst, 0)], IIC_ALU_NONMEM>, OpSize16, Sched<[WriteZero]>;<br>
<br>
// Other widths can also make use of the 32-bit xor, which may have a smaller<br>
// encoding and avoid partial register updates.<br>
@@ -324,7 +324,7 @@ def REP_MOVSW_32 : I<0xA5, RawFrm, (outs), (ins), "{rep;movsw|rep movsw}",<br>
[(X86rep_movs i16)], IIC_REP_MOVS>, REP, OpSize,<br>
Requires<[Not64BitMode]>;<br>
def REP_MOVSD_32 : I<0xA5, RawFrm, (outs), (ins), "{rep;movsl|rep movsd}",<br>
- [(X86rep_movs i32)], IIC_REP_MOVS>, REP,<br>
+ [(X86rep_movs i32)], IIC_REP_MOVS>, REP, OpSize16,<br>
Requires<[Not64BitMode]>;<br>
}<br>
<br>
@@ -355,7 +355,7 @@ let Defs = [ECX,EDI], isCodeGenOnly = 1 in {<br>
Requires<[Not64BitMode]>;<br>
let Uses = [EAX,ECX,EDI] in<br>
def REP_STOSD_32 : I<0xAB, RawFrm, (outs), (ins), "{rep;stosl|rep stosd}",<br>
- [(X86rep_stos i32)], IIC_REP_STOS>, REP,<br>
+ [(X86rep_stos i32)], IIC_REP_STOS>, REP, OpSize16,<br>
Requires<[Not64BitMode]>;<br>
}<br>
<br>
@@ -625,7 +625,7 @@ def NAME#32mr : I<{RegOpc{7}, RegOpc{6}, RegOpc{5}, RegOpc{4},<br>
MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),<br>
!strconcat(mnemonic, "{l}\t",<br>
"{$src2, $dst|$dst, $src2}"),<br>
- [], IIC_ALU_NONMEM>, LOCK;<br>
+ [], IIC_ALU_NONMEM>, OpSize16, LOCK;<br>
def NAME#64mr : RI<{RegOpc{7}, RegOpc{6}, RegOpc{5}, RegOpc{4},<br>
RegOpc{3}, RegOpc{2}, RegOpc{1}, 1 },<br>
MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),<br>
@@ -652,7 +652,7 @@ def NAME#32mi : Ii32<{ImmOpc{7}, ImmOpc{6}, ImmOpc{5}, ImmOpc{4},<br>
ImmMod, (outs), (ins i32mem :$dst, i32imm :$src2),<br>
!strconcat(mnemonic, "{l}\t",<br>
"{$src2, $dst|$dst, $src2}"),<br>
- [], IIC_ALU_MEM>, LOCK;<br>
+ [], IIC_ALU_MEM>, OpSize16, LOCK;<br>
<br>
def NAME#64mi32 : RIi32<{ImmOpc{7}, ImmOpc{6}, ImmOpc{5}, ImmOpc{4},<br>
ImmOpc{3}, ImmOpc{2}, ImmOpc{1}, 1 },<br>
@@ -672,7 +672,7 @@ def NAME#32mi8 : Ii8<{ImmOpc8{7}, ImmOpc8{6}, ImmOpc8{5}, ImmOpc8{4},<br>
ImmMod, (outs), (ins i32mem :$dst, i32i8imm :$src2),<br>
!strconcat(mnemonic, "{l}\t",<br>
"{$src2, $dst|$dst, $src2}"),<br>
- [], IIC_ALU_MEM>, LOCK;<br>
+ [], IIC_ALU_MEM>, OpSize16, LOCK;<br>
def NAME#64mi8 : RIi8<{ImmOpc8{7}, ImmOpc8{6}, ImmOpc8{5}, ImmOpc8{4},<br>
ImmOpc8{3}, ImmOpc8{2}, ImmOpc8{1}, 1 },<br>
ImmMod, (outs), (ins i64mem :$dst, i64i8imm :$src2),<br>
@@ -704,7 +704,7 @@ def NAME#16m : I<Opc, Form, (outs), (ins i16mem:$dst),<br>
[], IIC_UNARY_MEM>, OpSize, LOCK;<br>
def NAME#32m : I<Opc, Form, (outs), (ins i32mem:$dst),<br>
!strconcat(mnemonic, "{l}\t$dst"),<br>
- [], IIC_UNARY_MEM>, LOCK;<br>
+ [], IIC_UNARY_MEM>, OpSize16, LOCK;<br>
def NAME#64m : RI<Opc, Form, (outs), (ins i64mem:$dst),<br>
!strconcat(mnemonic, "{q}\t$dst"),<br>
[], IIC_UNARY_MEM>, LOCK;<br>
@@ -740,7 +740,7 @@ let isCodeGenOnly = 1, SchedRW = [WriteALULd, WriteRMW] in {<br>
let Defs = [EAX, EFLAGS], Uses = [EAX] in<br>
def NAME#32 : I<Opc, Form, (outs), (ins i32mem:$ptr, GR32:$swap),<br>
!strconcat(mnemonic, "{l}\t{$swap, $ptr|$ptr, $swap}"),<br>
- [(frag addr:$ptr, GR32:$swap, 4)], itin>, TB, LOCK;<br>
+ [(frag addr:$ptr, GR32:$swap, 4)], itin>, TB, OpSize16, LOCK;<br>
let Defs = [RAX, EFLAGS], Uses = [RAX] in<br>
def NAME#64 : RI<Opc, Form, (outs), (ins i64mem:$ptr, GR64:$swap),<br>
!strconcat(mnemonic, "{q}\t{$swap, $ptr|$ptr, $swap}"),<br>
@@ -790,7 +790,7 @@ multiclass ATOMIC_LOAD_BINOP<bits<8> opc8, bits<8> opc, string mnemonic,<br>
[(set<br>
GR32:$dst,<br>
(!cast<PatFrag>(frag # "_32") addr:$ptr, GR32:$val))],<br>
- itin>;<br>
+ itin>, OpSize16;<br>
def NAME#64 : RI<opc, MRMSrcMem, (outs GR64:$dst),<br>
(ins GR64:$val, i64mem:$ptr),<br>
!strconcat(mnemonic, "{q}\t{$val, $ptr|$ptr, $val}"),<br>
diff --git a/lib/Target/X86/X86InstrControl.td b/lib/Target/X86/X86InstrControl.td<br>
index 7d610e6..91f6123 100644<br>
--- a/lib/Target/X86/X86InstrControl.td<br>
+++ b/lib/Target/X86/X86InstrControl.td<br>
@@ -23,24 +23,24 @@ let isTerminator = 1, isReturn = 1, isBarrier = 1,<br>
hasCtrlDep = 1, FPForm = SpecialFP, SchedRW = [WriteJumpLd] in {<br>
def RET : I <0xC3, RawFrm, (outs), (ins variable_ops),<br>
"ret",<br>
- [(X86retflag 0)], IIC_RET>;<br>
+ [(X86retflag 0)], IIC_RET>, OpSize16;<br>
def RETW : I <0xC3, RawFrm, (outs), (ins),<br>
"ret{w}",<br>
[], IIC_RET>, OpSize;<br>
def RETI : Ii16<0xC2, RawFrm, (outs), (ins i16imm:$amt, variable_ops),<br>
"ret\t$amt",<br>
- [(X86retflag timm:$amt)], IIC_RET_IMM>;<br>
+ [(X86retflag timm:$amt)], IIC_RET_IMM>, OpSize16;<br>
def RETIW : Ii16<0xC2, RawFrm, (outs), (ins i16imm:$amt),<br>
"ret{w}\t$amt",<br>
[], IIC_RET_IMM>, OpSize;<br>
def LRETL : I <0xCB, RawFrm, (outs), (ins),<br>
- "{l}ret{l|f}", [], IIC_RET>;<br>
+ "{l}ret{l|f}", [], IIC_RET>, OpSize16;<br>
def LRETW : I <0xCB, RawFrm, (outs), (ins),<br>
"{l}ret{w|f}", [], IIC_RET>, OpSize;<br>
def LRETQ : RI <0xCB, RawFrm, (outs), (ins),<br>
"{l}ret{q|f}", [], IIC_RET>;<br>
def LRETI : Ii16<0xCA, RawFrm, (outs), (ins i16imm:$amt),<br>
- "{l}ret{l|f}\t$amt", [], IIC_RET>;<br>
+ "{l}ret{l|f}\t$amt", [], IIC_RET>, OpSize16;<br>
def LRETIW : Ii16<0xCA, RawFrm, (outs), (ins i16imm:$amt),<br>
"{l}ret{w|f}\t$amt", [], IIC_RET>, OpSize;<br>
}<br>
@@ -114,10 +114,10 @@ let isBranch = 1, isTerminator = 1, hasSideEffects = 0, SchedRW = [WriteJump] in<br>
let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {<br>
def JMP32r : I<0xFF, MRM4r, (outs), (ins GR32:$dst), "jmp{l}\t{*}$dst",<br>
[(brind GR32:$dst)], IIC_JMP_REG>, Requires<[Not64BitMode]>,<br>
- Sched<[WriteJump]>;<br>
+ OpSize16, Sched<[WriteJump]>;<br>
def JMP32m : I<0xFF, MRM4m, (outs), (ins i32mem:$dst), "jmp{l}\t{*}$dst",<br>
[(brind (loadi32 addr:$dst))], IIC_JMP_MEM>,<br>
- Requires<[Not64BitMode]>, Sched<[WriteJumpLd]>;<br>
+ Requires<[Not64BitMode]>, OpSize16, Sched<[WriteJumpLd]>;<br>
<br>
def JMP64r : I<0xFF, MRM4r, (outs), (ins GR64:$dst), "jmp{q}\t{*}$dst",<br>
[(brind GR64:$dst)], IIC_JMP_REG>, Requires<[In64BitMode]>,<br>
@@ -133,7 +133,7 @@ let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {<br>
def FARJMP32i : Iseg32<0xEA, RawFrmImm16, (outs),<br>
(ins i32imm:$off, i16imm:$seg),<br>
"ljmp{l}\t{$seg, $off|$off, $seg}", [],<br>
- IIC_JMP_FAR_PTR>, Sched<[WriteJump]>;<br>
+ IIC_JMP_FAR_PTR>, OpSize16, Sched<[WriteJump]>;<br>
def FARJMP64 : RI<0xFF, MRM5m, (outs), (ins opaque80mem:$dst),<br>
"ljmp{q}\t{*}$dst", [], IIC_JMP_FAR_MEM>,<br>
Sched<[WriteJump]>;<br>
@@ -142,7 +142,7 @@ let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {<br>
"ljmp{w}\t{*}$dst", [], IIC_JMP_FAR_MEM>, OpSize,<br>
Sched<[WriteJumpLd]>;<br>
def FARJMP32m : I<0xFF, MRM5m, (outs), (ins opaque48mem:$dst),<br>
- "ljmp{l}\t{*}$dst", [], IIC_JMP_FAR_MEM>,<br>
+ "ljmp{l}\t{*}$dst", [], IIC_JMP_FAR_MEM>, OpSize16,<br>
Sched<[WriteJumpLd]>;<br>
}<br>
<br>
@@ -165,14 +165,14 @@ let isCall = 1 in<br>
let Uses = [ESP] in {<br>
def CALLpcrel32 : Ii32PCRel<0xE8, RawFrm,<br>
(outs), (ins i32imm_pcrel:$dst),<br>
- "call{l}\t$dst", [], IIC_CALL_RI>,<br>
+ "call{l}\t$dst", [], IIC_CALL_RI>, OpSize16,<br>
Requires<[Not64BitMode]>, Sched<[WriteJump]>;<br>
def CALL32r : I<0xFF, MRM2r, (outs), (ins GR32:$dst),<br>
"call{l}\t{*}$dst", [(X86call GR32:$dst)], IIC_CALL_RI>,<br>
- Requires<[Not64BitMode]>, Sched<[WriteJump]>;<br>
+ OpSize16, Requires<[Not64BitMode]>, Sched<[WriteJump]>;<br>
def CALL32m : I<0xFF, MRM2m, (outs), (ins i32mem:$dst),<br>
"call{l}\t{*}$dst", [(X86call (loadi32 addr:$dst))],<br>
- IIC_CALL_MEM>,<br>
+ IIC_CALL_MEM>, OpSize16,<br>
Requires<[Not64BitMode,FavorMemIndirectCall]>,<br>
Sched<[WriteJumpLd]>;<br>
<br>
@@ -183,13 +183,13 @@ let isCall = 1 in<br>
def FARCALL32i : Iseg32<0x9A, RawFrmImm16, (outs),<br>
(ins i32imm:$off, i16imm:$seg),<br>
"lcall{l}\t{$seg, $off|$off, $seg}", [],<br>
- IIC_CALL_FAR_PTR>, Sched<[WriteJump]>;<br>
+ IIC_CALL_FAR_PTR>, OpSize16, Sched<[WriteJump]>;<br>
<br>
def FARCALL16m : I<0xFF, MRM3m, (outs), (ins opaque32mem:$dst),<br>
"lcall{w}\t{*}$dst", [], IIC_CALL_FAR_MEM>, OpSize,<br>
Sched<[WriteJumpLd]>;<br>
def FARCALL32m : I<0xFF, MRM3m, (outs), (ins opaque48mem:$dst),<br>
- "lcall{l}\t{*}$dst", [], IIC_CALL_FAR_MEM>,<br>
+ "lcall{l}\t{*}$dst", [], IIC_CALL_FAR_MEM>, OpSize16,<br>
Sched<[WriteJumpLd]>;<br>
<br>
// callw for 16 bit code for the assembler.<br>
diff --git a/lib/Target/X86/X86InstrInfo.td b/lib/Target/X86/X86InstrInfo.td<br>
index 4fee939..2a4c8f3 100644<br>
--- a/lib/Target/X86/X86InstrInfo.td<br>
+++ b/lib/Target/X86/X86InstrInfo.td<br>
@@ -885,47 +885,46 @@ let mayLoad = 1, SchedRW = [WriteLoad] in {<br>
def POP16r : I<0x58, AddRegFrm, (outs GR16:$reg), (ins), "pop{w}\t$reg", [],<br>
IIC_POP_REG16>, OpSize;<br>
def POP32r : I<0x58, AddRegFrm, (outs GR32:$reg), (ins), "pop{l}\t$reg", [],<br>
- IIC_POP_REG>;<br>
+ IIC_POP_REG>, OpSize16;<br>
def POP16rmr: I<0x8F, MRM0r, (outs GR16:$reg), (ins), "pop{w}\t$reg", [],<br>
IIC_POP_REG>, OpSize;<br>
def POP16rmm: I<0x8F, MRM0m, (outs), (ins i16mem:$dst), "pop{w}\t$dst", [],<br>
IIC_POP_MEM>, OpSize;<br>
def POP32rmr: I<0x8F, MRM0r, (outs GR32:$reg), (ins), "pop{l}\t$reg", [],<br>
- IIC_POP_REG>;<br>
+ IIC_POP_REG>, OpSize16;<br>
def POP32rmm: I<0x8F, MRM0m, (outs), (ins i32mem:$dst), "pop{l}\t$dst", [],<br>
- IIC_POP_MEM>;<br>
+ IIC_POP_MEM>, OpSize16;<br>
<br>
def POPF16 : I<0x9D, RawFrm, (outs), (ins), "popf{w}", [], IIC_POP_F>, OpSize;<br>
def POPF32 : I<0x9D, RawFrm, (outs), (ins), "popf{l|d}", [], IIC_POP_FD>,<br>
- Requires<[Not64BitMode]>;<br>
+ OpSize16, Requires<[Not64BitMode]>;<br>
} // mayLoad, SchedRW<br>
<br>
let mayStore = 1, SchedRW = [WriteStore] in {<br>
def PUSH16r : I<0x50, AddRegFrm, (outs), (ins GR16:$reg), "push{w}\t$reg",[],<br>
IIC_PUSH_REG>, OpSize;<br>
def PUSH32r : I<0x50, AddRegFrm, (outs), (ins GR32:$reg), "push{l}\t$reg",[],<br>
- IIC_PUSH_REG>;<br>
+ IIC_PUSH_REG>, OpSize16;<br>
def PUSH16rmr: I<0xFF, MRM6r, (outs), (ins GR16:$reg), "push{w}\t$reg",[],<br>
IIC_PUSH_REG>, OpSize;<br>
def PUSH16rmm: I<0xFF, MRM6m, (outs), (ins i16mem:$src), "push{w}\t$src",[],<br>
- IIC_PUSH_MEM>,<br>
- OpSize;<br>
+ IIC_PUSH_MEM>, OpSize;<br>
def PUSH32rmr: I<0xFF, MRM6r, (outs), (ins GR32:$reg), "push{l}\t$reg",[],<br>
- IIC_PUSH_REG>;<br>
+ IIC_PUSH_REG>, OpSize16;<br>
def PUSH32rmm: I<0xFF, MRM6m, (outs), (ins i32mem:$src), "push{l}\t$src",[],<br>
- IIC_PUSH_MEM>;<br>
+ IIC_PUSH_MEM>, OpSize16;<br>
<br>
def PUSHi8 : Ii8<0x6a, RawFrm, (outs), (ins i32i8imm:$imm),<br>
- "push{l}\t$imm", [], IIC_PUSH_IMM>;<br>
+ "push{l}\t$imm", [], IIC_PUSH_IMM>, OpSize16;<br>
def PUSHi16 : Ii16<0x68, RawFrm, (outs), (ins i16imm:$imm),<br>
"push{w}\t$imm", [], IIC_PUSH_IMM>, OpSize;<br>
def PUSHi32 : Ii32<0x68, RawFrm, (outs), (ins i32imm:$imm),<br>
- "push{l}\t$imm", [], IIC_PUSH_IMM>;<br>
+ "push{l}\t$imm", [], IIC_PUSH_IMM>, OpSize16;<br>
<br>
def PUSHF16 : I<0x9C, RawFrm, (outs), (ins), "pushf{w}", [], IIC_PUSH_F>,<br>
OpSize;<br>
def PUSHF32 : I<0x9C, RawFrm, (outs), (ins), "pushf{l|d}", [], IIC_PUSH_F>,<br>
- Requires<[Not64BitMode]>;<br>
+ OpSize16, Requires<[Not64BitMode]>;<br>
<br>
} // mayStore, SchedRW<br>
}<br>
@@ -969,12 +968,12 @@ def PUSHF64 : I<0x9C, RawFrm, (outs), (ins), "pushfq", [], IIC_PUSH_F>,<br>
let Defs = [EDI, ESI, EBP, EBX, EDX, ECX, EAX, ESP], Uses = [ESP],<br>
mayLoad = 1, neverHasSideEffects = 1, SchedRW = [WriteLoad] in {<br>
def POPA32 : I<0x61, RawFrm, (outs), (ins), "popa{l}", [], IIC_POP_A>,<br>
- Requires<[Not64BitMode]>;<br>
+ OpSize16, Requires<[Not64BitMode]>;<br>
}<br>
let Defs = [ESP], Uses = [EDI, ESI, EBP, EBX, EDX, ECX, EAX, ESP],<br>
mayStore = 1, neverHasSideEffects = 1, SchedRW = [WriteStore] in {<br>
def PUSHA32 : I<0x60, RawFrm, (outs), (ins), "pusha{l}", [], IIC_PUSH_A>,<br>
- Requires<[Not64BitMode]>;<br>
+ OpSize16, Requires<[Not64BitMode]>;<br>
}<br>
<br>
let Constraints = "$src = $dst", SchedRW = [WriteALU] in {<br>
@@ -982,7 +981,7 @@ let Constraints = "$src = $dst", SchedRW = [WriteALU] in {<br>
def BSWAP32r : I<0xC8, AddRegFrm,<br>
(outs GR32:$dst), (ins GR32:$src),<br>
"bswap{l}\t$dst",<br>
- [(set GR32:$dst, (bswap GR32:$src))], IIC_BSWAP>, TB;<br>
+ [(set GR32:$dst, (bswap GR32:$src))], IIC_BSWAP>, OpSize16, TB;<br>
<br>
def BSWAP64r : RI<0xC8, AddRegFrm, (outs GR64:$dst), (ins GR64:$src),<br>
"bswap{q}\t$dst",<br>
@@ -1002,12 +1001,12 @@ def BSF16rm : I<0xBC, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),<br>
def BSF32rr : I<0xBC, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),<br>
"bsf{l}\t{$src, $dst|$dst, $src}",<br>
[(set GR32:$dst, EFLAGS, (X86bsf GR32:$src))],<br>
- IIC_BIT_SCAN_REG>, TB,<br>
+ IIC_BIT_SCAN_REG>, TB, OpSize16,<br>
Sched<[WriteShift]>;<br>
def BSF32rm : I<0xBC, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),<br>
"bsf{l}\t{$src, $dst|$dst, $src}",<br>
[(set GR32:$dst, EFLAGS, (X86bsf (loadi32 addr:$src)))],<br>
- IIC_BIT_SCAN_MEM>, TB, Sched<[WriteShiftLd]>;<br>
+ IIC_BIT_SCAN_MEM>, TB, OpSize16, Sched<[WriteShiftLd]>;<br>
def BSF64rr : RI<0xBC, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),<br>
"bsf{q}\t{$src, $dst|$dst, $src}",<br>
[(set GR64:$dst, EFLAGS, (X86bsf GR64:$src))],<br>
@@ -1030,12 +1029,12 @@ def BSR16rm : I<0xBD, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),<br>
def BSR32rr : I<0xBD, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),<br>
"bsr{l}\t{$src, $dst|$dst, $src}",<br>
[(set GR32:$dst, EFLAGS, (X86bsr GR32:$src))],<br>
- IIC_BIT_SCAN_REG>, TB,<br>
+ IIC_BIT_SCAN_REG>, TB, OpSize16,<br>
Sched<[WriteShift]>;<br>
def BSR32rm : I<0xBD, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),<br>
"bsr{l}\t{$src, $dst|$dst, $src}",<br>
[(set GR32:$dst, EFLAGS, (X86bsr (loadi32 addr:$src)))],<br>
- IIC_BIT_SCAN_MEM>, TB, Sched<[WriteShiftLd]>;<br>
+ IIC_BIT_SCAN_MEM>, TB, OpSize16, Sched<[WriteShiftLd]>;<br>
def BSR64rr : RI<0xBD, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),<br>
"bsr{q}\t{$src, $dst|$dst, $src}",<br>
[(set GR64:$dst, EFLAGS, (X86bsr GR64:$src))], IIC_BIT_SCAN_REG>, TB,<br>
@@ -1051,7 +1050,7 @@ let SchedRW = [WriteMicrocoded] in {<br>
let Defs = [EDI,ESI], Uses = [EDI,ESI,EFLAGS] in {<br>
def MOVSB : I<0xA4, RawFrm, (outs), (ins), "movsb", [], IIC_MOVS>;<br>
def MOVSW : I<0xA5, RawFrm, (outs), (ins), "movsw", [], IIC_MOVS>, OpSize;<br>
-def MOVSD : I<0xA5, RawFrm, (outs), (ins), "movs{l|d}", [], IIC_MOVS>;<br>
+def MOVSD : I<0xA5, RawFrm, (outs), (ins), "movs{l|d}", [], IIC_MOVS>, OpSize16;<br>
def MOVSQ : RI<0xA5, RawFrm, (outs), (ins), "movsq", [], IIC_MOVS>;<br>
}<br>
<br>
@@ -1061,18 +1060,20 @@ def STOSB : I<0xAA, RawFrm, (outs), (ins), "stosb", [], IIC_STOS>;<br>
let Defs = [EDI], Uses = [AX,EDI,EFLAGS] in<br>
def STOSW : I<0xAB, RawFrm, (outs), (ins), "stosw", [], IIC_STOS>, OpSize;<br>
let Defs = [EDI], Uses = [EAX,EDI,EFLAGS] in<br>
-def STOSD : I<0xAB, RawFrm, (outs), (ins), "stos{l|d}", [], IIC_STOS>;<br>
+def STOSD : I<0xAB, RawFrm, (outs), (ins), "stos{l|d}", [], IIC_STOS>, OpSize16;<br>
let Defs = [RCX,RDI], Uses = [RAX,RCX,RDI,EFLAGS] in<br>
def STOSQ : RI<0xAB, RawFrm, (outs), (ins), "stosq", [], IIC_STOS>;<br>
<br>
def SCAS8 : I<0xAE, RawFrm, (outs), (ins), "scasb", [], IIC_SCAS>;<br>
def SCAS16 : I<0xAF, RawFrm, (outs), (ins), "scasw", [], IIC_SCAS>, OpSize;<br>
-def SCAS32 : I<0xAF, RawFrm, (outs), (ins), "scas{l|d}", [], IIC_SCAS>;<br>
+def SCAS32 : I<0xAF, RawFrm, (outs), (ins), "scas{l|d}", [], IIC_SCAS>,<br>
+ OpSize16;<br>
def SCAS64 : RI<0xAF, RawFrm, (outs), (ins), "scasq", [], IIC_SCAS>;<br>
<br>
def CMPS8 : I<0xA6, RawFrm, (outs), (ins), "cmpsb", [], IIC_CMPS>;<br>
def CMPS16 : I<0xA7, RawFrm, (outs), (ins), "cmpsw", [], IIC_CMPS>, OpSize;<br>
-def CMPS32 : I<0xA7, RawFrm, (outs), (ins), "cmps{l|d}", [], IIC_CMPS>;<br>
+def CMPS32 : I<0xA7, RawFrm, (outs), (ins), "cmps{l|d}", [], IIC_CMPS>,<br>
+ OpSize16;<br>
def CMPS64 : RI<0xA7, RawFrm, (outs), (ins), "cmpsq", [], IIC_CMPS>;<br>
} // SchedRW<br>
<br>
@@ -1086,7 +1087,7 @@ def MOV8rr : I<0x88, MRMDestReg, (outs GR8 :$dst), (ins GR8 :$src),<br>
def MOV16rr : I<0x89, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),<br>
"mov{w}\t{$src, $dst|$dst, $src}", [], IIC_MOV>, OpSize;<br>
def MOV32rr : I<0x89, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),<br>
- "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV>;<br>
+ "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV>, OpSize16;<br>
def MOV64rr : RI<0x89, MRMDestReg, (outs GR64:$dst), (ins GR64:$src),<br>
"mov{q}\t{$src, $dst|$dst, $src}", [], IIC_MOV>;<br>
}<br>
@@ -1100,7 +1101,7 @@ def MOV16ri : Ii16<0xB8, AddRegFrm, (outs GR16:$dst), (ins i16imm:$src),<br>
[(set GR16:$dst, imm:$src)], IIC_MOV>, OpSize;<br>
def MOV32ri : Ii32<0xB8, AddRegFrm, (outs GR32:$dst), (ins i32imm:$src),<br>
"mov{l}\t{$src, $dst|$dst, $src}",<br>
- [(set GR32:$dst, imm:$src)], IIC_MOV>;<br>
+ [(set GR32:$dst, imm:$src)], IIC_MOV>, OpSize16;<br>
def MOV64ri : RIi64<0xB8, AddRegFrm, (outs GR64:$dst), (ins i64imm:$src),<br>
"movabs{q}\t{$src, $dst|$dst, $src}",<br>
[(set GR64:$dst, imm:$src)], IIC_MOV>;<br>
@@ -1119,7 +1120,7 @@ def MOV16mi : Ii16<0xC7, MRM0m, (outs), (ins i16mem:$dst, i16imm:$src),<br>
[(store (i16 imm:$src), addr:$dst)], IIC_MOV_MEM>, OpSize;<br>
def MOV32mi : Ii32<0xC7, MRM0m, (outs), (ins i32mem:$dst, i32imm:$src),<br>
"mov{l}\t{$src, $dst|$dst, $src}",<br>
- [(store (i32 imm:$src), addr:$dst)], IIC_MOV_MEM>;<br>
+ [(store (i32 imm:$src), addr:$dst)], IIC_MOV_MEM>, OpSize16;<br>
def MOV64mi32 : RIi32<0xC7, MRM0m, (outs), (ins i64mem:$dst, i64i32imm:$src),<br>
"mov{q}\t{$src, $dst|$dst, $src}",<br>
[(store i64immSExt32:$src, addr:$dst)], IIC_MOV_MEM>;<br>
@@ -1139,7 +1140,7 @@ def MOV16o16a : Ii32 <0xA1, RawFrm, (outs), (ins offset16:$src),<br>
Requires<[Not64BitMode]>;<br>
def MOV32o32a : Ii32 <0xA1, RawFrm, (outs), (ins offset32:$src),<br>
"mov{l}\t{$src, %eax|eax, $src}", [], IIC_MOV_MEM>,<br>
- Requires<[Not64BitMode]>;<br>
+ OpSize16, Requires<[Not64BitMode]>;<br>
}<br>
let mayStore = 1 in {<br>
def MOV8ao8 : Ii32 <0xA2, RawFrm, (outs offset8:$dst), (ins),<br>
@@ -1150,7 +1151,7 @@ def MOV16ao16 : Ii32 <0xA3, RawFrm, (outs offset16:$dst), (ins),<br>
Requires<[Not64BitMode]>;<br>
def MOV32ao32 : Ii32 <0xA3, RawFrm, (outs offset32:$dst), (ins),<br>
"mov{l}\t{%eax, $dst|$dst, eax}", [], IIC_MOV_MEM>,<br>
- Requires<[Not64BitMode]>;<br>
+ OpSize16, Requires<[Not64BitMode]>;<br>
}<br>
}<br>
<br>
@@ -1193,7 +1194,7 @@ def MOV8rr_REV : I<0x8A, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src),<br>
def MOV16rr_REV : I<0x8B, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),<br>
"mov{w}\t{$src, $dst|$dst, $src}", [], IIC_MOV>, OpSize;<br>
def MOV32rr_REV : I<0x8B, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),<br>
- "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV>;<br>
+ "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV>, OpSize16;<br>
def MOV64rr_REV : RI<0x8B, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),<br>
"mov{q}\t{$src, $dst|$dst, $src}", [], IIC_MOV>;<br>
}<br>
@@ -1207,7 +1208,7 @@ def MOV16rm : I<0x8B, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),<br>
[(set GR16:$dst, (loadi16 addr:$src))], IIC_MOV_MEM>, OpSize;<br>
def MOV32rm : I<0x8B, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),<br>
"mov{l}\t{$src, $dst|$dst, $src}",<br>
- [(set GR32:$dst, (loadi32 addr:$src))], IIC_MOV_MEM>;<br>
+ [(set GR32:$dst, (loadi32 addr:$src))], IIC_MOV_MEM>, OpSize16;<br>
def MOV64rm : RI<0x8B, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),<br>
"mov{q}\t{$src, $dst|$dst, $src}",<br>
[(set GR64:$dst, (load addr:$src))], IIC_MOV_MEM>;<br>
@@ -1222,7 +1223,7 @@ def MOV16mr : I<0x89, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),<br>
[(store GR16:$src, addr:$dst)], IIC_MOV_MEM>, OpSize;<br>
def MOV32mr : I<0x89, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),<br>
"mov{l}\t{$src, $dst|$dst, $src}",<br>
- [(store GR32:$src, addr:$dst)], IIC_MOV_MEM>;<br>
+ [(store GR32:$src, addr:$dst)], IIC_MOV_MEM>, OpSize16;<br>
def MOV64mr : RI<0x89, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),<br>
"mov{q}\t{$src, $dst|$dst, $src}",<br>
[(store GR64:$src, addr:$dst)], IIC_MOV_MEM>;<br>
@@ -1272,7 +1273,8 @@ def BT16rr : I<0xA3, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),<br>
OpSize, TB;<br>
def BT32rr : I<0xA3, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),<br>
"bt{l}\t{$src2, $src1|$src1, $src2}",<br>
- [(set EFLAGS, (X86bt GR32:$src1, GR32:$src2))], IIC_BT_RR>, TB;<br>
+ [(set EFLAGS, (X86bt GR32:$src1, GR32:$src2))], IIC_BT_RR>,<br>
+ OpSize16, TB;<br>
def BT64rr : RI<0xA3, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),<br>
"bt{q}\t{$src2, $src1|$src1, $src2}",<br>
[(set EFLAGS, (X86bt GR64:$src1, GR64:$src2))], IIC_BT_RR>, TB;<br>
@@ -1295,7 +1297,7 @@ let mayLoad = 1, hasSideEffects = 0, SchedRW = [WriteALULd] in {<br>
// [(X86bt (loadi32 addr:$src1), GR32:$src2),<br>
// (implicit EFLAGS)]<br>
[], IIC_BT_MR<br>
- >, TB, Requires<[FastBTMem]>;<br>
+ >, OpSize16, TB, Requires<[FastBTMem]>;<br>
def BT64mr : RI<0xA3, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),<br>
"bt{q}\t{$src2, $src1|$src1, $src2}",<br>
// [(X86bt (loadi64 addr:$src1), GR64:$src2),<br>
@@ -1312,7 +1314,7 @@ def BT16ri8 : Ii8<0xBA, MRM4r, (outs), (ins GR16:$src1, i16i8imm:$src2),<br>
def BT32ri8 : Ii8<0xBA, MRM4r, (outs), (ins GR32:$src1, i32i8imm:$src2),<br>
"bt{l}\t{$src2, $src1|$src1, $src2}",<br>
[(set EFLAGS, (X86bt GR32:$src1, i32immSExt8:$src2))],<br>
- IIC_BT_RI>, TB;<br>
+ IIC_BT_RI>, OpSize16, TB;<br>
def BT64ri8 : RIi8<0xBA, MRM4r, (outs), (ins GR64:$src1, i64i8imm:$src2),<br>
"bt{q}\t{$src2, $src1|$src1, $src2}",<br>
[(set EFLAGS, (X86bt GR64:$src1, i64immSExt8:$src2))],<br>
@@ -1330,7 +1332,7 @@ def BT16mi8 : Ii8<0xBA, MRM4m, (outs), (ins i16mem:$src1, i16i8imm:$src2),<br>
def BT32mi8 : Ii8<0xBA, MRM4m, (outs), (ins i32mem:$src1, i32i8imm:$src2),<br>
"bt{l}\t{$src2, $src1|$src1, $src2}",<br>
[(set EFLAGS, (X86bt (loadi32 addr:$src1), i32immSExt8:$src2))<br>
- ], IIC_BT_MI>, TB;<br>
+ ], IIC_BT_MI>, OpSize16, TB;<br>
def BT64mi8 : RIi8<0xBA, MRM4m, (outs), (ins i64mem:$src1, i64i8imm:$src2),<br>
"bt{q}\t{$src2, $src1|$src1, $src2}",<br>
[(set EFLAGS, (X86bt (loadi64 addr:$src1),<br>
@@ -1343,7 +1345,8 @@ def BTC16rr : I<0xBB, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),<br>
"btc{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>,<br>
OpSize, TB;<br>
def BTC32rr : I<0xBB, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),<br>
- "btc{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>, TB;<br>
+ "btc{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>,<br>
+ OpSize16, TB;<br>
def BTC64rr : RI<0xBB, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),<br>
"btc{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>, TB;<br>
} // SchedRW<br>
@@ -1353,7 +1356,8 @@ def BTC16mr : I<0xBB, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),<br>
"btc{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>,<br>
OpSize, TB;<br>
def BTC32mr : I<0xBB, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),<br>
- "btc{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>, TB;<br>
+ "btc{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>,<br>
+ OpSize16, TB;<br>
def BTC64mr : RI<0xBB, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),<br>
"btc{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>, TB;<br>
}<br>
@@ -1363,7 +1367,8 @@ def BTC16ri8 : Ii8<0xBA, MRM7r, (outs), (ins GR16:$src1, i16i8imm:$src2),<br>
"btc{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>,<br>
OpSize, TB;<br>
def BTC32ri8 : Ii8<0xBA, MRM7r, (outs), (ins GR32:$src1, i32i8imm:$src2),<br>
- "btc{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>, TB;<br>
+ "btc{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>,<br>
+ OpSize16, TB;<br>
def BTC64ri8 : RIi8<0xBA, MRM7r, (outs), (ins GR64:$src1, i64i8imm:$src2),<br>
"btc{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>, TB;<br>
} // SchedRW<br>
@@ -1373,7 +1378,8 @@ def BTC16mi8 : Ii8<0xBA, MRM7m, (outs), (ins i16mem:$src1, i16i8imm:$src2),<br>
"btc{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>,<br>
OpSize, TB;<br>
def BTC32mi8 : Ii8<0xBA, MRM7m, (outs), (ins i32mem:$src1, i32i8imm:$src2),<br>
- "btc{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>, TB;<br>
+ "btc{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>,<br>
+ OpSize16, TB;<br>
def BTC64mi8 : RIi8<0xBA, MRM7m, (outs), (ins i64mem:$src1, i64i8imm:$src2),<br>
"btc{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>, TB;<br>
}<br>
@@ -1383,7 +1389,8 @@ def BTR16rr : I<0xB3, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),<br>
"btr{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>,<br>
OpSize, TB;<br>
def BTR32rr : I<0xB3, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),<br>
- "btr{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>, TB;<br>
+ "btr{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>,<br>
+ OpSize16, TB;<br>
def BTR64rr : RI<0xB3, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),<br>
"btr{q}\t{$src2, $src1|$src1, $src2}", []>, TB;<br>
} // SchedRW<br>
@@ -1393,7 +1400,8 @@ def BTR16mr : I<0xB3, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),<br>
"btr{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>,<br>
OpSize, TB;<br>
def BTR32mr : I<0xB3, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),<br>
- "btr{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>, TB;<br>
+ "btr{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>,<br>
+ OpSize16, TB;<br>
def BTR64mr : RI<0xB3, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),<br>
"btr{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>, TB;<br>
}<br>
@@ -1403,7 +1411,8 @@ def BTR16ri8 : Ii8<0xBA, MRM6r, (outs), (ins GR16:$src1, i16i8imm:$src2),<br>
"btr{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>,<br>
OpSize, TB;<br>
def BTR32ri8 : Ii8<0xBA, MRM6r, (outs), (ins GR32:$src1, i32i8imm:$src2),<br>
- "btr{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>, TB;<br>
+ "btr{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>,<br>
+ OpSize16, TB;<br>
def BTR64ri8 : RIi8<0xBA, MRM6r, (outs), (ins GR64:$src1, i64i8imm:$src2),<br>
"btr{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>, TB;<br>
} // SchedRW<br>
@@ -1413,7 +1422,8 @@ def BTR16mi8 : Ii8<0xBA, MRM6m, (outs), (ins i16mem:$src1, i16i8imm:$src2),<br>
"btr{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>,<br>
OpSize, TB;<br>
def BTR32mi8 : Ii8<0xBA, MRM6m, (outs), (ins i32mem:$src1, i32i8imm:$src2),<br>
- "btr{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>, TB;<br>
+ "btr{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>,<br>
+ OpSize16, TB;<br>
def BTR64mi8 : RIi8<0xBA, MRM6m, (outs), (ins i64mem:$src1, i64i8imm:$src2),<br>
"btr{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>, TB;<br>
}<br>
@@ -1423,7 +1433,8 @@ def BTS16rr : I<0xAB, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),<br>
"bts{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>,<br>
OpSize, TB;<br>
def BTS32rr : I<0xAB, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),<br>
- "bts{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>, TB;<br>
+ "bts{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>,<br>
+ OpSize16, TB;<br>
def BTS64rr : RI<0xAB, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),<br>
"bts{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>, TB;<br>
} // SchedRW<br>
@@ -1433,7 +1444,8 @@ def BTS16mr : I<0xAB, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),<br>
"bts{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>,<br>
OpSize, TB;<br>
def BTS32mr : I<0xAB, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),<br>
- "bts{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>, TB;<br>
+ "bts{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>,<br>
+ OpSize16, TB;<br>
def BTS64mr : RI<0xAB, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),<br>
"bts{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>, TB;<br>
}<br>
@@ -1443,7 +1455,8 @@ def BTS16ri8 : Ii8<0xBA, MRM5r, (outs), (ins GR16:$src1, i16i8imm:$src2),<br>
"bts{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>,<br>
OpSize, TB;<br>
def BTS32ri8 : Ii8<0xBA, MRM5r, (outs), (ins GR32:$src1, i32i8imm:$src2),<br>
- "bts{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>, TB;<br>
+ "bts{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>,<br>
+ OpSize16, TB;<br>
def BTS64ri8 : RIi8<0xBA, MRM5r, (outs), (ins GR64:$src1, i64i8imm:$src2),<br>
"bts{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>, TB;<br>
} // SchedRW<br>
@@ -1453,7 +1466,8 @@ def BTS16mi8 : Ii8<0xBA, MRM5m, (outs), (ins i16mem:$src1, i16i8imm:$src2),<br>
"bts{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>,<br>
OpSize, TB;<br>
def BTS32mi8 : Ii8<0xBA, MRM5m, (outs), (ins i32mem:$src1, i32i8imm:$src2),<br>
- "bts{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>, TB;<br>
+ "bts{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>,<br>
+ OpSize16, TB;<br>
def BTS64mi8 : RIi8<0xBA, MRM5m, (outs), (ins i64mem:$src1, i64i8imm:$src2),<br>
"bts{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>, TB;<br>
}<br>
@@ -1490,7 +1504,7 @@ multiclass ATOMIC_SWAP<bits<8> opc8, bits<8> opc, string mnemonic, string frag,<br>
[(set<br>
GR32:$dst,<br>
(!cast<PatFrag>(frag # "_32") addr:$ptr, GR32:$val))],<br>
- itin>;<br>
+ itin>, OpSize16;<br>
def NAME#64rm : RI<opc, MRMSrcMem, (outs GR64:$dst),<br>
(ins GR64:$val, i64mem:$ptr),<br>
!strconcat(mnemonic, "{q}\t{$val, $ptr|$ptr, $val}"),<br>
@@ -1511,7 +1525,8 @@ def XCHG8rr : I<0x86, MRMSrcReg, (outs GR8:$dst), (ins GR8:$val, GR8:$src),<br>
def XCHG16rr : I<0x87, MRMSrcReg, (outs GR16:$dst), (ins GR16:$val, GR16:$src),<br>
"xchg{w}\t{$val, $src|$src, $val}", [], IIC_XCHG_REG>, OpSize;<br>
def XCHG32rr : I<0x87, MRMSrcReg, (outs GR32:$dst), (ins GR32:$val, GR32:$src),<br>
- "xchg{l}\t{$val, $src|$src, $val}", [], IIC_XCHG_REG>;<br>
+ "xchg{l}\t{$val, $src|$src, $val}", [], IIC_XCHG_REG>,<br>
+ OpSize16;<br>
def XCHG64rr : RI<0x87, MRMSrcReg, (outs GR64:$dst), (ins GR64:$val,GR64:$src),<br>
"xchg{q}\t{$val, $src|$src, $val}", [], IIC_XCHG_REG>;<br>
}<br>
@@ -1521,7 +1536,7 @@ def XCHG16ar : I<0x90, AddRegFrm, (outs), (ins GR16:$src),<br>
"xchg{w}\t{$src, %ax|ax, $src}", [], IIC_XCHG_REG>, OpSize;<br>
def XCHG32ar : I<0x90, AddRegFrm, (outs), (ins GR32:$src),<br>
"xchg{l}\t{$src, %eax|eax, $src}", [], IIC_XCHG_REG>,<br>
- Requires<[Not64BitMode]>;<br>
+ OpSize16, Requires<[Not64BitMode]>;<br>
// Uses GR32_NOAX in 64-bit mode to prevent encoding using the 0x90 NOP encoding.<br>
// xchg %eax, %eax needs to clear upper 32-bits of RAX so is not a NOP.<br>
def XCHG32ar64 : I<0x90, AddRegFrm, (outs), (ins GR32_NOAX:$src),<br>
@@ -1538,7 +1553,8 @@ def XADD16rr : I<0xC1, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),<br>
"xadd{w}\t{$src, $dst|$dst, $src}", [], IIC_XADD_REG>, TB,<br>
OpSize;<br>
def XADD32rr : I<0xC1, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),<br>
- "xadd{l}\t{$src, $dst|$dst, $src}", [], IIC_XADD_REG>, TB;<br>
+ "xadd{l}\t{$src, $dst|$dst, $src}", [], IIC_XADD_REG>, TB,<br>
+ OpSize16;<br>
def XADD64rr : RI<0xC1, MRMDestReg, (outs GR64:$dst), (ins GR64:$src),<br>
"xadd{q}\t{$src, $dst|$dst, $src}", [], IIC_XADD_REG>, TB;<br>
} // SchedRW<br>
@@ -1550,7 +1566,8 @@ def XADD16rm : I<0xC1, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),<br>
"xadd{w}\t{$src, $dst|$dst, $src}", [], IIC_XADD_MEM>, TB,<br>
OpSize;<br>
def XADD32rm : I<0xC1, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),<br>
- "xadd{l}\t{$src, $dst|$dst, $src}", [], IIC_XADD_MEM>, TB;<br>
+ "xadd{l}\t{$src, $dst|$dst, $src}", [], IIC_XADD_MEM>, TB,<br>
+ OpSize16;<br>
def XADD64rm : RI<0xC1, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),<br>
"xadd{q}\t{$src, $dst|$dst, $src}", [], IIC_XADD_MEM>, TB;<br>
<br>
@@ -1565,7 +1582,7 @@ def CMPXCHG16rr : I<0xB1, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),<br>
IIC_CMPXCHG_REG>, TB, OpSize;<br>
def CMPXCHG32rr : I<0xB1, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),<br>
"cmpxchg{l}\t{$src, $dst|$dst, $src}", [],<br>
- IIC_CMPXCHG_REG>, TB;<br>
+ IIC_CMPXCHG_REG>, TB, OpSize16;<br>
def CMPXCHG64rr : RI<0xB1, MRMDestReg, (outs GR64:$dst), (ins GR64:$src),<br>
"cmpxchg{q}\t{$src, $dst|$dst, $src}", [],<br>
IIC_CMPXCHG_REG>, TB;<br>
@@ -1581,7 +1598,7 @@ def CMPXCHG16rm : I<0xB1, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),<br>
IIC_CMPXCHG_MEM>, TB, OpSize;<br>
def CMPXCHG32rm : I<0xB1, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),<br>
"cmpxchg{l}\t{$src, $dst|$dst, $src}", [],<br>
- IIC_CMPXCHG_MEM>, TB;<br>
+ IIC_CMPXCHG_MEM>, TB, OpSize16;<br>
def CMPXCHG64rm : RI<0xB1, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),<br>
"cmpxchg{q}\t{$src, $dst|$dst, $src}", [],<br>
IIC_CMPXCHG_MEM>, TB;<br>
@@ -1621,14 +1638,14 @@ def REPNE_PREFIX : I<0xF2, RawFrm, (outs), (ins), "repne", []>;<br>
let SchedRW = [WriteMicrocoded] in {<br>
def LODSB : I<0xAC, RawFrm, (outs), (ins), "lodsb", [], IIC_LODS>;<br>
def LODSW : I<0xAD, RawFrm, (outs), (ins), "lodsw", [], IIC_LODS>, OpSize;<br>
-def LODSD : I<0xAD, RawFrm, (outs), (ins), "lods{l|d}", [], IIC_LODS>;<br>
+def LODSD : I<0xAD, RawFrm, (outs), (ins), "lods{l|d}", [], IIC_LODS>, OpSize16;<br>
def LODSQ : RI<0xAD, RawFrm, (outs), (ins), "lodsq", [], IIC_LODS>;<br>
}<br>
<br>
let SchedRW = [WriteSystem] in {<br>
def OUTSB : I<0x6E, RawFrm, (outs), (ins), "outsb", [], IIC_OUTS>;<br>
def OUTSW : I<0x6F, RawFrm, (outs), (ins), "outsw", [], IIC_OUTS>, OpSize;<br>
-def OUTSD : I<0x6F, RawFrm, (outs), (ins), "outs{l|d}", [], IIC_OUTS>;<br>
+def OUTSD : I<0x6F, RawFrm, (outs), (ins), "outs{l|d}", [], IIC_OUTS>, OpSize16;<br>
}<br>
<br>
// Flag instructions<br>
@@ -1686,7 +1703,7 @@ def BOUNDS16rm : I<0x62, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),<br>
"bound\t{$src, $dst|$dst, $src}", [], IIC_BOUND>, OpSize,<br>
Requires<[Not64BitMode]>;<br>
def BOUNDS32rm : I<0x62, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),<br>
- "bound\t{$src, $dst|$dst, $src}", [], IIC_BOUND>,<br>
+ "bound\t{$src, $dst|$dst, $src}", [], IIC_BOUND>, OpSize16,<br>
Requires<[Not64BitMode]>;<br>
<br>
// Adjust RPL Field of Segment Selector<br>
@@ -1710,7 +1727,7 @@ let Predicates = [HasMOVBE] in {<br>
def MOVBE32rm : I<0xF0, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),<br>
"movbe{l}\t{$src, $dst|$dst, $src}",<br>
[(set GR32:$dst, (bswap (loadi32 addr:$src)))], IIC_MOVBE>,<br>
- T8;<br>
+ OpSize16, T8;<br>
def MOVBE64rm : RI<0xF0, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),<br>
"movbe{q}\t{$src, $dst|$dst, $src}",<br>
[(set GR64:$dst, (bswap (loadi64 addr:$src)))], IIC_MOVBE>,<br>
@@ -1724,7 +1741,7 @@ let Predicates = [HasMOVBE] in {<br>
def MOVBE32mr : I<0xF1, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),<br>
"movbe{l}\t{$src, $dst|$dst, $src}",<br>
[(store (bswap GR32:$src), addr:$dst)], IIC_MOVBE>,<br>
- T8;<br>
+ OpSize16, T8;<br>
def MOVBE64mr : RI<0xF1, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),<br>
"movbe{q}\t{$src, $dst|$dst, $src}",<br>
[(store (bswap GR64:$src), addr:$dst)], IIC_MOVBE>,<br>
@@ -1741,7 +1758,7 @@ let Predicates = [HasRDRAND], Defs = [EFLAGS] in {<br>
[(set GR16:$dst, EFLAGS, (X86rdrand))]>, OpSize, TB;<br>
def RDRAND32r : I<0xC7, MRM6r, (outs GR32:$dst), (ins),<br>
"rdrand{l}\t$dst",<br>
- [(set GR32:$dst, EFLAGS, (X86rdrand))]>, TB;<br>
+ [(set GR32:$dst, EFLAGS, (X86rdrand))]>, OpSize16, TB;<br>
def RDRAND64r : RI<0xC7, MRM6r, (outs GR64:$dst), (ins),<br>
"rdrand{q}\t$dst",<br>
[(set GR64:$dst, EFLAGS, (X86rdrand))]>, TB;<br>
@@ -1756,7 +1773,7 @@ let Predicates = [HasRDSEED], Defs = [EFLAGS] in {<br>
[(set GR16:$dst, EFLAGS, (X86rdseed))]>, OpSize, TB;<br>
def RDSEED32r : I<0xC7, MRM7r, (outs GR32:$dst), (ins),<br>
"rdseed{l}\t$dst",<br>
- [(set GR32:$dst, EFLAGS, (X86rdseed))]>, TB;<br>
+ [(set GR32:$dst, EFLAGS, (X86rdseed))]>, OpSize16, TB;<br>
def RDSEED64r : RI<0xC7, MRM7r, (outs GR64:$dst), (ins),<br>
"rdseed{q}\t$dst",<br>
[(set GR64:$dst, EFLAGS, (X86rdseed))]>, TB;<br>
@@ -1777,11 +1794,12 @@ let Predicates = [HasLZCNT], Defs = [EFLAGS] in {<br>
<br>
def LZCNT32rr : I<0xBD, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),<br>
"lzcnt{l}\t{$src, $dst|$dst, $src}",<br>
- [(set GR32:$dst, (ctlz GR32:$src)), (implicit EFLAGS)]>, XS;<br>
+ [(set GR32:$dst, (ctlz GR32:$src)), (implicit EFLAGS)]>, XS,<br>
+ OpSize16;<br>
def LZCNT32rm : I<0xBD, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),<br>
"lzcnt{l}\t{$src, $dst|$dst, $src}",<br>
[(set GR32:$dst, (ctlz (loadi32 addr:$src))),<br>
- (implicit EFLAGS)]>, XS;<br>
+ (implicit EFLAGS)]>, XS, OpSize16;<br>
<br>
def LZCNT64rr : RI<0xBD, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),<br>
"lzcnt{q}\t{$src, $dst|$dst, $src}",<br>
@@ -1808,11 +1826,12 @@ let Predicates = [HasBMI], Defs = [EFLAGS] in {<br>
<br>
def TZCNT32rr : I<0xBC, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),<br>
"tzcnt{l}\t{$src, $dst|$dst, $src}",<br>
- [(set GR32:$dst, (cttz GR32:$src)), (implicit EFLAGS)]>, XS;<br>
+ [(set GR32:$dst, (cttz GR32:$src)), (implicit EFLAGS)]>, XS,<br>
+ OpSize16;<br>
def TZCNT32rm : I<0xBC, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),<br>
"tzcnt{l}\t{$src, $dst|$dst, $src}",<br>
[(set GR32:$dst, (cttz (loadi32 addr:$src))),<br>
- (implicit EFLAGS)]>, XS;<br>
+ (implicit EFLAGS)]>, XS, OpSize16;<br>
<br>
def TZCNT64rr : RI<0xBC, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),<br>
"tzcnt{q}\t{$src, $dst|$dst, $src}",<br>
diff --git a/lib/Target/X86/X86InstrShiftRotate.td b/lib/Target/X86/X86InstrShiftRotate.td<br>
index 1937770..3be1129 100644<br>
--- a/lib/Target/X86/X86InstrShiftRotate.td<br>
+++ b/lib/Target/X86/X86InstrShiftRotate.td<br>
@@ -25,7 +25,7 @@ def SHL16rCL : I<0xD3, MRM4r, (outs GR16:$dst), (ins GR16:$src1),<br>
[(set GR16:$dst, (shl GR16:$src1, CL))], IIC_SR>, OpSize;<br>
def SHL32rCL : I<0xD3, MRM4r, (outs GR32:$dst), (ins GR32:$src1),<br>
"shl{l}\t{%cl, $dst|$dst, cl}",<br>
- [(set GR32:$dst, (shl GR32:$src1, CL))], IIC_SR>;<br>
+ [(set GR32:$dst, (shl GR32:$src1, CL))], IIC_SR>, OpSize16;<br>
def SHL64rCL : RI<0xD3, MRM4r, (outs GR64:$dst), (ins GR64:$src1),<br>
"shl{q}\t{%cl, $dst|$dst, cl}",<br>
[(set GR64:$dst, (shl GR64:$src1, CL))], IIC_SR>;<br>
@@ -42,7 +42,8 @@ def SHL16ri : Ii8<0xC1, MRM4r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),<br>
OpSize;<br>
def SHL32ri : Ii8<0xC1, MRM4r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),<br>
"shl{l}\t{$src2, $dst|$dst, $src2}",<br>
- [(set GR32:$dst, (shl GR32:$src1, (i8 imm:$src2)))], IIC_SR>;<br>
+ [(set GR32:$dst, (shl GR32:$src1, (i8 imm:$src2)))], IIC_SR>,<br>
+ OpSize16;<br>
def SHL64ri : RIi8<0xC1, MRM4r, (outs GR64:$dst),<br>
(ins GR64:$src1, i8imm:$src2),<br>
"shl{q}\t{$src2, $dst|$dst, $src2}",<br>
@@ -57,7 +58,7 @@ def SHL8r1 : I<0xD0, MRM4r, (outs GR8:$dst), (ins GR8:$src1),<br>
def SHL16r1 : I<0xD1, MRM4r, (outs GR16:$dst), (ins GR16:$src1),<br>
"shl{w}\t$dst", [], IIC_SR>, OpSize;<br>
def SHL32r1 : I<0xD1, MRM4r, (outs GR32:$dst), (ins GR32:$src1),<br>
- "shl{l}\t$dst", [], IIC_SR>;<br>
+ "shl{l}\t$dst", [], IIC_SR>, OpSize16;<br>
def SHL64r1 : RI<0xD1, MRM4r, (outs GR64:$dst), (ins GR64:$src1),<br>
"shl{q}\t$dst", [], IIC_SR>;<br>
} // hasSideEffects = 0<br>
@@ -78,7 +79,8 @@ def SHL16mCL : I<0xD3, MRM4m, (outs), (ins i16mem:$dst),<br>
OpSize;<br>
def SHL32mCL : I<0xD3, MRM4m, (outs), (ins i32mem:$dst),<br>
"shl{l}\t{%cl, $dst|$dst, cl}",<br>
- [(store (shl (loadi32 addr:$dst), CL), addr:$dst)], IIC_SR>;<br>
+ [(store (shl (loadi32 addr:$dst), CL), addr:$dst)], IIC_SR>,<br>
+ OpSize16;<br>
def SHL64mCL : RI<0xD3, MRM4m, (outs), (ins i64mem:$dst),<br>
"shl{q}\t{%cl, $dst|$dst, cl}",<br>
[(store (shl (loadi64 addr:$dst), CL), addr:$dst)], IIC_SR>;<br>
@@ -95,7 +97,7 @@ def SHL16mi : Ii8<0xC1, MRM4m, (outs), (ins i16mem:$dst, i8imm:$src),<br>
def SHL32mi : Ii8<0xC1, MRM4m, (outs), (ins i32mem:$dst, i8imm:$src),<br>
"shl{l}\t{$src, $dst|$dst, $src}",<br>
[(store (shl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)],<br>
- IIC_SR>;<br>
+ IIC_SR>, OpSize16;<br>
def SHL64mi : RIi8<0xC1, MRM4m, (outs), (ins i64mem:$dst, i8imm:$src),<br>
"shl{q}\t{$src, $dst|$dst, $src}",<br>
[(store (shl (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)],<br>
@@ -114,7 +116,7 @@ def SHL16m1 : I<0xD1, MRM4m, (outs), (ins i16mem:$dst),<br>
def SHL32m1 : I<0xD1, MRM4m, (outs), (ins i32mem:$dst),<br>
"shl{l}\t$dst",<br>
[(store (shl (loadi32 addr:$dst), (i8 1)), addr:$dst)],<br>
- IIC_SR>;<br>
+ IIC_SR>, OpSize16;<br>
def SHL64m1 : RI<0xD1, MRM4m, (outs), (ins i64mem:$dst),<br>
"shl{q}\t$dst",<br>
[(store (shl (loadi64 addr:$dst), (i8 1)), addr:$dst)],<br>
@@ -131,7 +133,7 @@ def SHR16rCL : I<0xD3, MRM5r, (outs GR16:$dst), (ins GR16:$src1),<br>
[(set GR16:$dst, (srl GR16:$src1, CL))], IIC_SR>, OpSize;<br>
def SHR32rCL : I<0xD3, MRM5r, (outs GR32:$dst), (ins GR32:$src1),<br>
"shr{l}\t{%cl, $dst|$dst, cl}",<br>
- [(set GR32:$dst, (srl GR32:$src1, CL))], IIC_SR>;<br>
+ [(set GR32:$dst, (srl GR32:$src1, CL))], IIC_SR>, OpSize16;<br>
def SHR64rCL : RI<0xD3, MRM5r, (outs GR64:$dst), (ins GR64:$src1),<br>
"shr{q}\t{%cl, $dst|$dst, cl}",<br>
[(set GR64:$dst, (srl GR64:$src1, CL))], IIC_SR>;<br>
@@ -147,7 +149,7 @@ def SHR16ri : Ii8<0xC1, MRM5r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),<br>
def SHR32ri : Ii8<0xC1, MRM5r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),<br>
"shr{l}\t{$src2, $dst|$dst, $src2}",<br>
[(set GR32:$dst, (srl GR32:$src1, (i8 imm:$src2)))],<br>
- IIC_SR>;<br>
+ IIC_SR>, OpSize16;<br>
def SHR64ri : RIi8<0xC1, MRM5r, (outs GR64:$dst), (ins GR64:$src1, i8imm:$src2),<br>
"shr{q}\t{$src2, $dst|$dst, $src2}",<br>
[(set GR64:$dst, (srl GR64:$src1, (i8 imm:$src2)))], IIC_SR>;<br>
@@ -161,7 +163,7 @@ def SHR16r1 : I<0xD1, MRM5r, (outs GR16:$dst), (ins GR16:$src1),<br>
[(set GR16:$dst, (srl GR16:$src1, (i8 1)))], IIC_SR>, OpSize;<br>
def SHR32r1 : I<0xD1, MRM5r, (outs GR32:$dst), (ins GR32:$src1),<br>
"shr{l}\t$dst",<br>
- [(set GR32:$dst, (srl GR32:$src1, (i8 1)))], IIC_SR>;<br>
+ [(set GR32:$dst, (srl GR32:$src1, (i8 1)))], IIC_SR>, OpSize16;<br>
def SHR64r1 : RI<0xD1, MRM5r, (outs GR64:$dst), (ins GR64:$src1),<br>
"shr{q}\t$dst",<br>
[(set GR64:$dst, (srl GR64:$src1, (i8 1)))], IIC_SR>;<br>
@@ -179,7 +181,8 @@ def SHR16mCL : I<0xD3, MRM5m, (outs), (ins i16mem:$dst),<br>
OpSize;<br>
def SHR32mCL : I<0xD3, MRM5m, (outs), (ins i32mem:$dst),<br>
"shr{l}\t{%cl, $dst|$dst, cl}",<br>
- [(store (srl (loadi32 addr:$dst), CL), addr:$dst)], IIC_SR>;<br>
+ [(store (srl (loadi32 addr:$dst), CL), addr:$dst)], IIC_SR>,<br>
+ OpSize16;<br>
def SHR64mCL : RI<0xD3, MRM5m, (outs), (ins i64mem:$dst),<br>
"shr{q}\t{%cl, $dst|$dst, cl}",<br>
[(store (srl (loadi64 addr:$dst), CL), addr:$dst)], IIC_SR>;<br>
@@ -196,7 +199,7 @@ def SHR16mi : Ii8<0xC1, MRM5m, (outs), (ins i16mem:$dst, i8imm:$src),<br>
def SHR32mi : Ii8<0xC1, MRM5m, (outs), (ins i32mem:$dst, i8imm:$src),<br>
"shr{l}\t{$src, $dst|$dst, $src}",<br>
[(store (srl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)],<br>
- IIC_SR>;<br>
+ IIC_SR>, OpSize16;<br>
def SHR64mi : RIi8<0xC1, MRM5m, (outs), (ins i64mem:$dst, i8imm:$src),<br>
"shr{q}\t{$src, $dst|$dst, $src}",<br>
[(store (srl (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)],<br>
@@ -214,7 +217,7 @@ def SHR16m1 : I<0xD1, MRM5m, (outs), (ins i16mem:$dst),<br>
def SHR32m1 : I<0xD1, MRM5m, (outs), (ins i32mem:$dst),<br>
"shr{l}\t$dst",<br>
[(store (srl (loadi32 addr:$dst), (i8 1)), addr:$dst)],<br>
- IIC_SR>;<br>
+ IIC_SR>, OpSize16;<br>
def SHR64m1 : RI<0xD1, MRM5m, (outs), (ins i64mem:$dst),<br>
"shr{q}\t$dst",<br>
[(store (srl (loadi64 addr:$dst), (i8 1)), addr:$dst)],<br>
@@ -234,7 +237,7 @@ def SAR16rCL : I<0xD3, MRM7r, (outs GR16:$dst), (ins GR16:$src1),<br>
def SAR32rCL : I<0xD3, MRM7r, (outs GR32:$dst), (ins GR32:$src1),<br>
"sar{l}\t{%cl, $dst|$dst, cl}",<br>
[(set GR32:$dst, (sra GR32:$src1, CL))],<br>
- IIC_SR>;<br>
+ IIC_SR>, OpSize16;<br>
def SAR64rCL : RI<0xD3, MRM7r, (outs GR64:$dst), (ins GR64:$src1),<br>
"sar{q}\t{%cl, $dst|$dst, cl}",<br>
[(set GR64:$dst, (sra GR64:$src1, CL))],<br>
@@ -253,7 +256,7 @@ def SAR16ri : Ii8<0xC1, MRM7r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),<br>
def SAR32ri : Ii8<0xC1, MRM7r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),<br>
"sar{l}\t{$src2, $dst|$dst, $src2}",<br>
[(set GR32:$dst, (sra GR32:$src1, (i8 imm:$src2)))],<br>
- IIC_SR>;<br>
+ IIC_SR>, OpSize16;<br>
def SAR64ri : RIi8<0xC1, MRM7r, (outs GR64:$dst),<br>
(ins GR64:$src1, i8imm:$src2),<br>
"sar{q}\t{$src2, $dst|$dst, $src2}",<br>
@@ -272,7 +275,7 @@ def SAR16r1 : I<0xD1, MRM7r, (outs GR16:$dst), (ins GR16:$src1),<br>
def SAR32r1 : I<0xD1, MRM7r, (outs GR32:$dst), (ins GR32:$src1),<br>
"sar{l}\t$dst",<br>
[(set GR32:$dst, (sra GR32:$src1, (i8 1)))],<br>
- IIC_SR>;<br>
+ IIC_SR>, OpSize16;<br>
def SAR64r1 : RI<0xD1, MRM7r, (outs GR64:$dst), (ins GR64:$src1),<br>
"sar{q}\t$dst",<br>
[(set GR64:$dst, (sra GR64:$src1, (i8 1)))],<br>
@@ -293,7 +296,7 @@ def SAR16mCL : I<0xD3, MRM7m, (outs), (ins i16mem:$dst),<br>
def SAR32mCL : I<0xD3, MRM7m, (outs), (ins i32mem:$dst),<br>
"sar{l}\t{%cl, $dst|$dst, cl}",<br>
[(store (sra (loadi32 addr:$dst), CL), addr:$dst)],<br>
- IIC_SR>;<br>
+ IIC_SR>, OpSize16;<br>
def SAR64mCL : RI<0xD3, MRM7m, (outs), (ins i64mem:$dst),<br>
"sar{q}\t{%cl, $dst|$dst, cl}",<br>
[(store (sra (loadi64 addr:$dst), CL), addr:$dst)],<br>
@@ -311,7 +314,7 @@ def SAR16mi : Ii8<0xC1, MRM7m, (outs), (ins i16mem:$dst, i8imm:$src),<br>
def SAR32mi : Ii8<0xC1, MRM7m, (outs), (ins i32mem:$dst, i8imm:$src),<br>
"sar{l}\t{$src, $dst|$dst, $src}",<br>
[(store (sra (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)],<br>
- IIC_SR>;<br>
+ IIC_SR>, OpSize16;<br>
def SAR64mi : RIi8<0xC1, MRM7m, (outs), (ins i64mem:$dst, i8imm:$src),<br>
"sar{q}\t{$src, $dst|$dst, $src}",<br>
[(store (sra (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)],<br>
@@ -330,7 +333,7 @@ def SAR16m1 : I<0xD1, MRM7m, (outs), (ins i16mem:$dst),<br>
def SAR32m1 : I<0xD1, MRM7m, (outs), (ins i32mem:$dst),<br>
"sar{l}\t$dst",<br>
[(store (sra (loadi32 addr:$dst), (i8 1)), addr:$dst)],<br>
- IIC_SR>;<br>
+ IIC_SR>, OpSize16;<br>
def SAR64m1 : RI<0xD1, MRM7m, (outs), (ins i64mem:$dst),<br>
"sar{q}\t$dst",<br>
[(store (sra (loadi64 addr:$dst), (i8 1)), addr:$dst)],<br>
@@ -360,12 +363,12 @@ def RCL16rCL : I<0xD3, MRM2r, (outs GR16:$dst), (ins GR16:$src1),<br>
"rcl{w}\t{%cl, $dst|$dst, cl}", [], IIC_SR>, OpSize;<br>
<br>
def RCL32r1 : I<0xD1, MRM2r, (outs GR32:$dst), (ins GR32:$src1),<br>
- "rcl{l}\t$dst", [], IIC_SR>;<br>
+ "rcl{l}\t$dst", [], IIC_SR>, OpSize16;<br>
def RCL32ri : Ii8<0xC1, MRM2r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$cnt),<br>
- "rcl{l}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>;<br>
+ "rcl{l}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>, OpSize16;<br>
let Uses = [CL] in<br>
def RCL32rCL : I<0xD3, MRM2r, (outs GR32:$dst), (ins GR32:$src1),<br>
- "rcl{l}\t{%cl, $dst|$dst, cl}", [], IIC_SR>;<br>
+ "rcl{l}\t{%cl, $dst|$dst, cl}", [], IIC_SR>, OpSize16;<br>
<br>
<br>
def RCL64r1 : RI<0xD1, MRM2r, (outs GR64:$dst), (ins GR64:$src1),<br>
@@ -394,12 +397,12 @@ def RCR16rCL : I<0xD3, MRM3r, (outs GR16:$dst), (ins GR16:$src1),<br>
"rcr{w}\t{%cl, $dst|$dst, cl}", [], IIC_SR>, OpSize;<br>
<br>
def RCR32r1 : I<0xD1, MRM3r, (outs GR32:$dst), (ins GR32:$src1),<br>
- "rcr{l}\t$dst", [], IIC_SR>;<br>
+ "rcr{l}\t$dst", [], IIC_SR>, OpSize16;<br>
def RCR32ri : Ii8<0xC1, MRM3r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$cnt),<br>
- "rcr{l}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>;<br>
+ "rcr{l}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>, OpSize16;<br>
let Uses = [CL] in<br>
def RCR32rCL : I<0xD3, MRM3r, (outs GR32:$dst), (ins GR32:$src1),<br>
- "rcr{l}\t{%cl, $dst|$dst, cl}", [], IIC_SR>;<br>
+ "rcr{l}\t{%cl, $dst|$dst, cl}", [], IIC_SR>, OpSize16;<br>
<br>
def RCR64r1 : RI<0xD1, MRM3r, (outs GR64:$dst), (ins GR64:$src1),<br>
"rcr{q}\t$dst", [], IIC_SR>;<br>
@@ -421,9 +424,9 @@ def RCL16m1 : I<0xD1, MRM2m, (outs), (ins i16mem:$dst),<br>
def RCL16mi : Ii8<0xC1, MRM2m, (outs), (ins i16mem:$dst, i8imm:$cnt),<br>
"rcl{w}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>, OpSize;<br>
def RCL32m1 : I<0xD1, MRM2m, (outs), (ins i32mem:$dst),<br>
- "rcl{l}\t$dst", [], IIC_SR>;<br>
+ "rcl{l}\t$dst", [], IIC_SR>, OpSize16;<br>
def RCL32mi : Ii8<0xC1, MRM2m, (outs), (ins i32mem:$dst, i8imm:$cnt),<br>
- "rcl{l}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>;<br>
+ "rcl{l}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>, OpSize16;<br>
def RCL64m1 : RI<0xD1, MRM2m, (outs), (ins i64mem:$dst),<br>
"rcl{q}\t$dst", [], IIC_SR>;<br>
def RCL64mi : RIi8<0xC1, MRM2m, (outs), (ins i64mem:$dst, i8imm:$cnt),<br>
@@ -438,9 +441,9 @@ def RCR16m1 : I<0xD1, MRM3m, (outs), (ins i16mem:$dst),<br>
def RCR16mi : Ii8<0xC1, MRM3m, (outs), (ins i16mem:$dst, i8imm:$cnt),<br>
"rcr{w}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>, OpSize;<br>
def RCR32m1 : I<0xD1, MRM3m, (outs), (ins i32mem:$dst),<br>
- "rcr{l}\t$dst", [], IIC_SR>;<br>
+ "rcr{l}\t$dst", [], IIC_SR>, OpSize16;<br>
def RCR32mi : Ii8<0xC1, MRM3m, (outs), (ins i32mem:$dst, i8imm:$cnt),<br>
- "rcr{l}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>;<br>
+ "rcr{l}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>, OpSize16;<br>
def RCR64m1 : RI<0xD1, MRM3m, (outs), (ins i64mem:$dst),<br>
"rcr{q}\t$dst", [], IIC_SR>;<br>
def RCR64mi : RIi8<0xC1, MRM3m, (outs), (ins i64mem:$dst, i8imm:$cnt),<br>
@@ -452,7 +455,7 @@ def RCL8mCL : I<0xD2, MRM2m, (outs), (ins i8mem:$dst),<br>
def RCL16mCL : I<0xD3, MRM2m, (outs), (ins i16mem:$dst),<br>
"rcl{w}\t{%cl, $dst|$dst, cl}", [], IIC_SR>, OpSize;<br>
def RCL32mCL : I<0xD3, MRM2m, (outs), (ins i32mem:$dst),<br>
- "rcl{l}\t{%cl, $dst|$dst, cl}", [], IIC_SR>;<br>
+ "rcl{l}\t{%cl, $dst|$dst, cl}", [], IIC_SR>, OpSize16;<br>
def RCL64mCL : RI<0xD3, MRM2m, (outs), (ins i64mem:$dst),<br>
"rcl{q}\t{%cl, $dst|$dst, cl}", [], IIC_SR>;<br>
<br>
@@ -461,7 +464,7 @@ def RCR8mCL : I<0xD2, MRM3m, (outs), (ins i8mem:$dst),<br>
def RCR16mCL : I<0xD3, MRM3m, (outs), (ins i16mem:$dst),<br>
"rcr{w}\t{%cl, $dst|$dst, cl}", [], IIC_SR>, OpSize;<br>
def RCR32mCL : I<0xD3, MRM3m, (outs), (ins i32mem:$dst),<br>
- "rcr{l}\t{%cl, $dst|$dst, cl}", [], IIC_SR>;<br>
+ "rcr{l}\t{%cl, $dst|$dst, cl}", [], IIC_SR>, OpSize16;<br>
def RCR64mCL : RI<0xD3, MRM3m, (outs), (ins i64mem:$dst),<br>
"rcr{q}\t{%cl, $dst|$dst, cl}", [], IIC_SR>;<br>
}<br>
@@ -479,7 +482,7 @@ def ROL16rCL : I<0xD3, MRM0r, (outs GR16:$dst), (ins GR16:$src1),<br>
[(set GR16:$dst, (rotl GR16:$src1, CL))], IIC_SR>, OpSize;<br>
def ROL32rCL : I<0xD3, MRM0r, (outs GR32:$dst), (ins GR32:$src1),<br>
"rol{l}\t{%cl, $dst|$dst, cl}",<br>
- [(set GR32:$dst, (rotl GR32:$src1, CL))], IIC_SR>;<br>
+ [(set GR32:$dst, (rotl GR32:$src1, CL))], IIC_SR>, OpSize16;<br>
def ROL64rCL : RI<0xD3, MRM0r, (outs GR64:$dst), (ins GR64:$src1),<br>
"rol{q}\t{%cl, $dst|$dst, cl}",<br>
[(set GR64:$dst, (rotl GR64:$src1, CL))], IIC_SR>;<br>
@@ -496,7 +499,7 @@ def ROL16ri : Ii8<0xC1, MRM0r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),<br>
def ROL32ri : Ii8<0xC1, MRM0r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),<br>
"rol{l}\t{$src2, $dst|$dst, $src2}",<br>
[(set GR32:$dst, (rotl GR32:$src1, (i8 imm:$src2)))],<br>
- IIC_SR>;<br>
+ IIC_SR>, OpSize16;<br>
def ROL64ri : RIi8<0xC1, MRM0r, (outs GR64:$dst),<br>
(ins GR64:$src1, i8imm:$src2),<br>
"rol{q}\t{$src2, $dst|$dst, $src2}",<br>
@@ -515,7 +518,7 @@ def ROL16r1 : I<0xD1, MRM0r, (outs GR16:$dst), (ins GR16:$src1),<br>
def ROL32r1 : I<0xD1, MRM0r, (outs GR32:$dst), (ins GR32:$src1),<br>
"rol{l}\t$dst",<br>
[(set GR32:$dst, (rotl GR32:$src1, (i8 1)))],<br>
- IIC_SR>;<br>
+ IIC_SR>, OpSize16;<br>
def ROL64r1 : RI<0xD1, MRM0r, (outs GR64:$dst), (ins GR64:$src1),<br>
"rol{q}\t$dst",<br>
[(set GR64:$dst, (rotl GR64:$src1, (i8 1)))],<br>
@@ -535,7 +538,7 @@ def ROL16mCL : I<0xD3, MRM0m, (outs), (ins i16mem:$dst),<br>
def ROL32mCL : I<0xD3, MRM0m, (outs), (ins i32mem:$dst),<br>
"rol{l}\t{%cl, $dst|$dst, cl}",<br>
[(store (rotl (loadi32 addr:$dst), CL), addr:$dst)],<br>
- IIC_SR>;<br>
+ IIC_SR>, OpSize16;<br>
def ROL64mCL : RI<0xD3, MRM0m, (outs), (ins i64mem:$dst),<br>
"rol{q}\t{%cl, $dst|$dst, cl}",<br>
[(store (rotl (loadi64 addr:$dst), CL), addr:$dst)],<br>
@@ -553,7 +556,7 @@ def ROL16mi : Ii8<0xC1, MRM0m, (outs), (ins i16mem:$dst, i8imm:$src1),<br>
def ROL32mi : Ii8<0xC1, MRM0m, (outs), (ins i32mem:$dst, i8imm:$src1),<br>
"rol{l}\t{$src1, $dst|$dst, $src1}",<br>
[(store (rotl (loadi32 addr:$dst), (i8 imm:$src1)), addr:$dst)],<br>
- IIC_SR>;<br>
+ IIC_SR>, OpSize16;<br>
def ROL64mi : RIi8<0xC1, MRM0m, (outs), (ins i64mem:$dst, i8imm:$src1),<br>
"rol{q}\t{$src1, $dst|$dst, $src1}",<br>
[(store (rotl (loadi64 addr:$dst), (i8 imm:$src1)), addr:$dst)],<br>
@@ -572,7 +575,7 @@ def ROL16m1 : I<0xD1, MRM0m, (outs), (ins i16mem:$dst),<br>
def ROL32m1 : I<0xD1, MRM0m, (outs), (ins i32mem:$dst),<br>
"rol{l}\t$dst",<br>
[(store (rotl (loadi32 addr:$dst), (i8 1)), addr:$dst)],<br>
- IIC_SR>;<br>
+ IIC_SR>, OpSize16;<br>
def ROL64m1 : RI<0xD1, MRM0m, (outs), (ins i64mem:$dst),<br>
"rol{q}\t$dst",<br>
[(store (rotl (loadi64 addr:$dst), (i8 1)), addr:$dst)],<br>
@@ -589,7 +592,7 @@ def ROR16rCL : I<0xD3, MRM1r, (outs GR16:$dst), (ins GR16:$src1),<br>
[(set GR16:$dst, (rotr GR16:$src1, CL))], IIC_SR>, OpSize;<br>
def ROR32rCL : I<0xD3, MRM1r, (outs GR32:$dst), (ins GR32:$src1),<br>
"ror{l}\t{%cl, $dst|$dst, cl}",<br>
- [(set GR32:$dst, (rotr GR32:$src1, CL))], IIC_SR>;<br>
+ [(set GR32:$dst, (rotr GR32:$src1, CL))], IIC_SR>, OpSize16;<br>
def ROR64rCL : RI<0xD3, MRM1r, (outs GR64:$dst), (ins GR64:$src1),<br>
"ror{q}\t{%cl, $dst|$dst, cl}",<br>
[(set GR64:$dst, (rotr GR64:$src1, CL))], IIC_SR>;<br>
@@ -606,7 +609,7 @@ def ROR16ri : Ii8<0xC1, MRM1r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),<br>
def ROR32ri : Ii8<0xC1, MRM1r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),<br>
"ror{l}\t{$src2, $dst|$dst, $src2}",<br>
[(set GR32:$dst, (rotr GR32:$src1, (i8 imm:$src2)))],<br>
- IIC_SR>;<br>
+ IIC_SR>, OpSize16;<br>
def ROR64ri : RIi8<0xC1, MRM1r, (outs GR64:$dst),<br>
(ins GR64:$src1, i8imm:$src2),<br>
"ror{q}\t{$src2, $dst|$dst, $src2}",<br>
@@ -625,7 +628,7 @@ def ROR16r1 : I<0xD1, MRM1r, (outs GR16:$dst), (ins GR16:$src1),<br>
def ROR32r1 : I<0xD1, MRM1r, (outs GR32:$dst), (ins GR32:$src1),<br>
"ror{l}\t$dst",<br>
[(set GR32:$dst, (rotr GR32:$src1, (i8 1)))],<br>
- IIC_SR>;<br>
+ IIC_SR>, OpSize16;<br>
def ROR64r1 : RI<0xD1, MRM1r, (outs GR64:$dst), (ins GR64:$src1),<br>
"ror{q}\t$dst",<br>
[(set GR64:$dst, (rotr GR64:$src1, (i8 1)))],<br>
@@ -645,7 +648,7 @@ def ROR16mCL : I<0xD3, MRM1m, (outs), (ins i16mem:$dst),<br>
def ROR32mCL : I<0xD3, MRM1m, (outs), (ins i32mem:$dst),<br>
"ror{l}\t{%cl, $dst|$dst, cl}",<br>
[(store (rotr (loadi32 addr:$dst), CL), addr:$dst)],<br>
- IIC_SR>;<br>
+ IIC_SR>, OpSize16;<br>
def ROR64mCL : RI<0xD3, MRM1m, (outs), (ins i64mem:$dst),<br>
"ror{q}\t{%cl, $dst|$dst, cl}",<br>
[(store (rotr (loadi64 addr:$dst), CL), addr:$dst)],<br>
@@ -663,7 +666,7 @@ def ROR16mi : Ii8<0xC1, MRM1m, (outs), (ins i16mem:$dst, i8imm:$src),<br>
def ROR32mi : Ii8<0xC1, MRM1m, (outs), (ins i32mem:$dst, i8imm:$src),<br>
"ror{l}\t{$src, $dst|$dst, $src}",<br>
[(store (rotr (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)],<br>
- IIC_SR>;<br>
+ IIC_SR>, OpSize16;<br>
def ROR64mi : RIi8<0xC1, MRM1m, (outs), (ins i64mem:$dst, i8imm:$src),<br>
"ror{q}\t{$src, $dst|$dst, $src}",<br>
[(store (rotr (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)],<br>
@@ -682,7 +685,7 @@ def ROR16m1 : I<0xD1, MRM1m, (outs), (ins i16mem:$dst),<br>
def ROR32m1 : I<0xD1, MRM1m, (outs), (ins i32mem:$dst),<br>
"ror{l}\t$dst",<br>
[(store (rotr (loadi32 addr:$dst), (i8 1)), addr:$dst)],<br>
- IIC_SR>;<br>
+ IIC_SR>, OpSize16;<br>
def ROR64m1 : RI<0xD1, MRM1m, (outs), (ins i64mem:$dst),<br>
"ror{q}\t$dst",<br>
[(store (rotr (loadi64 addr:$dst), (i8 1)), addr:$dst)],<br>
@@ -713,12 +716,12 @@ def SHLD32rrCL : I<0xA5, MRMDestReg, (outs GR32:$dst),<br>
(ins GR32:$src1, GR32:$src2),<br>
"shld{l}\t{%cl, $src2, $dst|$dst, $src2, cl}",<br>
[(set GR32:$dst, (X86shld GR32:$src1, GR32:$src2, CL))],<br>
- IIC_SHD32_REG_CL>, TB;<br>
+ IIC_SHD32_REG_CL>, TB, OpSize16;<br>
def SHRD32rrCL : I<0xAD, MRMDestReg, (outs GR32:$dst),<br>
(ins GR32:$src1, GR32:$src2),<br>
"shrd{l}\t{%cl, $src2, $dst|$dst, $src2, cl}",<br>
[(set GR32:$dst, (X86shrd GR32:$src1, GR32:$src2, CL))],<br>
- IIC_SHD32_REG_CL>, TB;<br>
+ IIC_SHD32_REG_CL>, TB, OpSize16;<br>
def SHLD64rrCL : RI<0xA5, MRMDestReg, (outs GR64:$dst),<br>
(ins GR64:$src1, GR64:$src2),<br>
"shld{q}\t{%cl, $src2, $dst|$dst, $src2, cl}",<br>
@@ -754,14 +757,14 @@ def SHLD32rri8 : Ii8<0xA4, MRMDestReg,<br>
"shld{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",<br>
[(set GR32:$dst, (X86shld GR32:$src1, GR32:$src2,<br>
(i8 imm:$src3)))], IIC_SHD32_REG_IM>,<br>
- TB;<br>
+ TB, OpSize16;<br>
def SHRD32rri8 : Ii8<0xAC, MRMDestReg,<br>
(outs GR32:$dst),<br>
(ins GR32:$src1, GR32:$src2, i8imm:$src3),<br>
"shrd{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",<br>
[(set GR32:$dst, (X86shrd GR32:$src1, GR32:$src2,<br>
(i8 imm:$src3)))], IIC_SHD32_REG_IM>,<br>
- TB;<br>
+ TB, OpSize16;<br>
def SHLD64rri8 : RIi8<0xA4, MRMDestReg,<br>
(outs GR64:$dst),<br>
(ins GR64:$src1, GR64:$src2, i8imm:$src3),<br>
@@ -793,11 +796,11 @@ def SHRD16mrCL : I<0xAD, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),<br>
def SHLD32mrCL : I<0xA5, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),<br>
"shld{l}\t{%cl, $src2, $dst|$dst, $src2, cl}",<br>
[(store (X86shld (loadi32 addr:$dst), GR32:$src2, CL),<br>
- addr:$dst)], IIC_SHD32_MEM_CL>, TB;<br>
+ addr:$dst)], IIC_SHD32_MEM_CL>, TB, OpSize16;<br>
def SHRD32mrCL : I<0xAD, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),<br>
"shrd{l}\t{%cl, $src2, $dst|$dst, $src2, cl}",<br>
[(store (X86shrd (loadi32 addr:$dst), GR32:$src2, CL),<br>
- addr:$dst)], IIC_SHD32_MEM_CL>, TB;<br>
+ addr:$dst)], IIC_SHD32_MEM_CL>, TB, OpSize16;<br>
<br>
def SHLD64mrCL : RI<0xA5, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),<br>
"shld{q}\t{%cl, $src2, $dst|$dst, $src2, cl}",<br>
@@ -830,14 +833,14 @@ def SHLD32mri8 : Ii8<0xA4, MRMDestMem,<br>
[(store (X86shld (loadi32 addr:$dst), GR32:$src2,<br>
(i8 imm:$src3)), addr:$dst)],<br>
IIC_SHD32_MEM_IM>,<br>
- TB;<br>
+ TB, OpSize16;<br>
def SHRD32mri8 : Ii8<0xAC, MRMDestMem,<br>
(outs), (ins i32mem:$dst, GR32:$src2, i8imm:$src3),<br>
"shrd{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",<br>
[(store (X86shrd (loadi32 addr:$dst), GR32:$src2,<br>
(i8 imm:$src3)), addr:$dst)],<br>
IIC_SHD32_MEM_IM>,<br>
- TB;<br>
+ TB, OpSize16;<br>
<br>
def SHLD64mri8 : RIi8<0xA4, MRMDestMem,<br>
(outs), (ins i64mem:$dst, GR64:$src2, i8imm:$src3),<br>
diff --git a/lib/Target/X86/X86InstrSystem.td b/lib/Target/X86/X86InstrSystem.td<br>
index 27f753d..90a51c8 100644<br>
--- a/lib/Target/X86/X86InstrSystem.td<br>
+++ b/lib/Target/X86/X86InstrSystem.td<br>
@@ -65,7 +65,8 @@ def SYSEXIT64 :RI<0x35, RawFrm, (outs), (ins), "sysexit{q}", []>, TB,<br>
Requires<[In64BitMode]>;<br>
<br>
def IRET16 : I<0xcf, RawFrm, (outs), (ins), "iret{w}", [], IIC_IRET>, OpSize;<br>
-def IRET32 : I<0xcf, RawFrm, (outs), (ins), "iret{l|d}", [], IIC_IRET>;<br>
+def IRET32 : I<0xcf, RawFrm, (outs), (ins), "iret{l|d}", [], IIC_IRET>,<br>
+ OpSize16;<br>
def IRET64 : RI<0xcf, RawFrm, (outs), (ins), "iretq", [], IIC_IRET>,<br>
Requires<[In64BitMode]>;<br>
} // SchedRW<br>
@@ -83,7 +84,7 @@ def IN16rr : I<0xED, RawFrm, (outs), (ins),<br>
"in{w}\t{%dx, %ax|ax, dx}", [], IIC_IN_RR>, OpSize;<br>
let Defs = [EAX], Uses = [DX] in<br>
def IN32rr : I<0xED, RawFrm, (outs), (ins),<br>
- "in{l}\t{%dx, %eax|eax, dx}", [], IIC_IN_RR>;<br>
+ "in{l}\t{%dx, %eax|eax, dx}", [], IIC_IN_RR>, OpSize16;<br>
<br>
let Defs = [AL] in<br>
def IN8ri : Ii8<0xE4, RawFrm, (outs), (ins i8imm:$port),<br>
@@ -93,7 +94,7 @@ def IN16ri : Ii8<0xE5, RawFrm, (outs), (ins i8imm:$port),<br>
"in{w}\t{$port, %ax|ax, $port}", [], IIC_IN_RI>, OpSize;<br>
let Defs = [EAX] in<br>
def IN32ri : Ii8<0xE5, RawFrm, (outs), (ins i8imm:$port),<br>
- "in{l}\t{$port, %eax|eax, $port}", [], IIC_IN_RI>;<br>
+ "in{l}\t{$port, %eax|eax, $port}", [], IIC_IN_RI>, OpSize16;<br>
<br>
let Uses = [DX, AL] in<br>
def OUT8rr : I<0xEE, RawFrm, (outs), (ins),<br>
@@ -103,7 +104,7 @@ def OUT16rr : I<0xEF, RawFrm, (outs), (ins),<br>
"out{w}\t{%ax, %dx|dx, ax}", [], IIC_OUT_RR>, OpSize;<br>
let Uses = [DX, EAX] in<br>
def OUT32rr : I<0xEF, RawFrm, (outs), (ins),<br>
- "out{l}\t{%eax, %dx|dx, eax}", [], IIC_OUT_RR>;<br>
+ "out{l}\t{%eax, %dx|dx, eax}", [], IIC_OUT_RR>, OpSize16;<br>
<br>
let Uses = [AL] in<br>
def OUT8ir : Ii8<0xE6, RawFrm, (outs), (ins i8imm:$port),<br>
@@ -113,11 +114,11 @@ def OUT16ir : Ii8<0xE7, RawFrm, (outs), (ins i8imm:$port),<br>
"out{w}\t{%ax, $port|$port, ax}", [], IIC_OUT_IR>, OpSize;<br>
let Uses = [EAX] in<br>
def OUT32ir : Ii8<0xE7, RawFrm, (outs), (ins i8imm:$port),<br>
- "out{l}\t{%eax, $port|$port, eax}", [], IIC_OUT_IR>;<br>
+ "out{l}\t{%eax, $port|$port, eax}", [], IIC_OUT_IR>, OpSize16;<br>
<br>
def IN8 : I<0x6C, RawFrm, (outs), (ins), "ins{b}", [], IIC_INS>;<br>
def IN16 : I<0x6D, RawFrm, (outs), (ins), "ins{w}", [], IIC_INS>, OpSize;<br>
-def IN32 : I<0x6D, RawFrm, (outs), (ins), "ins{l}", [], IIC_INS>;<br>
+def IN32 : I<0x6D, RawFrm, (outs), (ins), "ins{l}", [], IIC_INS>, OpSize16;<br>
} // SchedRW<br>
<br>
//===----------------------------------------------------------------------===//<br>
@@ -169,28 +170,28 @@ let SchedRW = [WriteMove] in {<br>
def MOV16rs : I<0x8C, MRMDestReg, (outs GR16:$dst), (ins SEGMENT_REG:$src),<br>
"mov{w}\t{$src, $dst|$dst, $src}", [], IIC_MOV_REG_SR>, OpSize;<br>
def MOV32rs : I<0x8C, MRMDestReg, (outs GR32:$dst), (ins SEGMENT_REG:$src),<br>
- "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV_REG_SR>;<br>
+ "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV_REG_SR>, OpSize16;<br>
def MOV64rs : RI<0x8C, MRMDestReg, (outs GR64:$dst), (ins SEGMENT_REG:$src),<br>
"mov{q}\t{$src, $dst|$dst, $src}", [], IIC_MOV_REG_SR>;<br>
<br>
def MOV16ms : I<0x8C, MRMDestMem, (outs i16mem:$dst), (ins SEGMENT_REG:$src),<br>
"mov{w}\t{$src, $dst|$dst, $src}", [], IIC_MOV_MEM_SR>, OpSize;<br>
def MOV32ms : I<0x8C, MRMDestMem, (outs i32mem:$dst), (ins SEGMENT_REG:$src),<br>
- "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV_MEM_SR>;<br>
+ "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV_MEM_SR>, OpSize16;<br>
def MOV64ms : RI<0x8C, MRMDestMem, (outs i64mem:$dst), (ins SEGMENT_REG:$src),<br>
"mov{q}\t{$src, $dst|$dst, $src}", [], IIC_MOV_MEM_SR>;<br>
<br>
def MOV16sr : I<0x8E, MRMSrcReg, (outs SEGMENT_REG:$dst), (ins GR16:$src),<br>
"mov{w}\t{$src, $dst|$dst, $src}", [], IIC_MOV_SR_REG>, OpSize;<br>
def MOV32sr : I<0x8E, MRMSrcReg, (outs SEGMENT_REG:$dst), (ins GR32:$src),<br>
- "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV_SR_REG>;<br>
+ "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV_SR_REG>, OpSize16;<br>
def MOV64sr : RI<0x8E, MRMSrcReg, (outs SEGMENT_REG:$dst), (ins GR64:$src),<br>
"mov{q}\t{$src, $dst|$dst, $src}", [], IIC_MOV_SR_REG>;<br>
<br>
def MOV16sm : I<0x8E, MRMSrcMem, (outs SEGMENT_REG:$dst), (ins i16mem:$src),<br>
"mov{w}\t{$src, $dst|$dst, $src}", [], IIC_MOV_SR_MEM>, OpSize;<br>
def MOV32sm : I<0x8E, MRMSrcMem, (outs SEGMENT_REG:$dst), (ins i32mem:$src),<br>
- "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV_SR_MEM>;<br>
+ "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV_SR_MEM>, OpSize16;<br>
def MOV64sm : RI<0x8E, MRMSrcMem, (outs SEGMENT_REG:$dst), (ins i64mem:$src),<br>
"mov{q}\t{$src, $dst|$dst, $src}", [], IIC_MOV_SR_MEM>;<br>
} // SchedRW<br>
@@ -208,9 +209,11 @@ def LAR16rr : I<0x02, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),<br>
<br>
// i16mem operand in LAR32rm and GR32 operand in LAR32rr is not a typo.<br>
def LAR32rm : I<0x02, MRMSrcMem, (outs GR32:$dst), (ins i16mem:$src),<br>
- "lar{l}\t{$src, $dst|$dst, $src}", [], IIC_LAR_RM>, TB;<br>
+ "lar{l}\t{$src, $dst|$dst, $src}", [], IIC_LAR_RM>, TB,<br>
+ OpSize16;<br>
def LAR32rr : I<0x02, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),<br>
- "lar{l}\t{$src, $dst|$dst, $src}", [], IIC_LAR_RR>, TB;<br>
+ "lar{l}\t{$src, $dst|$dst, $src}", [], IIC_LAR_RR>, TB,<br>
+ OpSize16;<br>
// i16mem operand in LAR64rm and GR32 operand in LAR32rr is not a typo.<br>
def LAR64rm : RI<0x02, MRMSrcMem, (outs GR64:$dst), (ins i16mem:$src),<br>
"lar{q}\t{$src, $dst|$dst, $src}", [], IIC_LAR_RM>, TB;<br>
@@ -222,9 +225,11 @@ def LSL16rm : I<0x03, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),<br>
def LSL16rr : I<0x03, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),<br>
"lsl{w}\t{$src, $dst|$dst, $src}", [], IIC_LSL_RR>, TB, OpSize;<br>
def LSL32rm : I<0x03, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),<br>
- "lsl{l}\t{$src, $dst|$dst, $src}", [], IIC_LSL_RM>, TB;<br>
+ "lsl{l}\t{$src, $dst|$dst, $src}", [], IIC_LSL_RM>, TB,<br>
+ OpSize16;<br>
def LSL32rr : I<0x03, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),<br>
- "lsl{l}\t{$src, $dst|$dst, $src}", [], IIC_LSL_RR>, TB;<br>
+ "lsl{l}\t{$src, $dst|$dst, $src}", [], IIC_LSL_RR>, TB,<br>
+ OpSize16;<br>
def LSL64rm : RI<0x03, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),<br>
"lsl{q}\t{$src, $dst|$dst, $src}", [], IIC_LSL_RM>, TB;<br>
def LSL64rr : RI<0x03, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),<br>
@@ -236,7 +241,7 @@ def INVLPG : I<0x01, MRM7m, (outs), (ins i8mem:$addr), "invlpg\t$addr",<br>
def STR16r : I<0x00, MRM1r, (outs GR16:$dst), (ins),<br>
"str{w}\t$dst", [], IIC_STR>, TB, OpSize;<br>
def STR32r : I<0x00, MRM1r, (outs GR32:$dst), (ins),<br>
- "str{l}\t$dst", [], IIC_STR>, TB;<br>
+ "str{l}\t$dst", [], IIC_STR>, TB, OpSize16;<br>
def STR64r : RI<0x00, MRM1r, (outs GR64:$dst), (ins),<br>
"str{q}\t$dst", [], IIC_STR>, TB;<br>
def STRm : I<0x00, MRM1m, (outs i16mem:$dst), (ins),<br>
@@ -248,35 +253,39 @@ def LTRm : I<0x00, MRM3m, (outs), (ins i16mem:$src),<br>
"ltr{w}\t$src", [], IIC_LTR>, TB;<br>
<br>
def PUSHCS16 : I<0x0E, RawFrm, (outs), (ins),<br>
- "push{w}\t{%cs|cs}", [], IIC_PUSH_SR>, Requires<[Not64BitMode]>,<br>
- OpSize;<br>
+ "push{w}\t{%cs|cs}", [], IIC_PUSH_SR>,<br>
+ OpSize, Requires<[Not64BitMode]>;<br>
def PUSHCS32 : I<0x0E, RawFrm, (outs), (ins),<br>
- "push{l}\t{%cs|cs}", [], IIC_PUSH_CS>, Requires<[Not64BitMode]>;<br>
+ "push{l}\t{%cs|cs}", [], IIC_PUSH_CS>,<br>
+ OpSize16, Requires<[Not64BitMode]>;<br>
def PUSHSS16 : I<0x16, RawFrm, (outs), (ins),<br>
- "push{w}\t{%ss|ss}", [], IIC_PUSH_SR>, Requires<[Not64BitMode]>,<br>
- OpSize;<br>
+ "push{w}\t{%ss|ss}", [], IIC_PUSH_SR>,<br>
+ OpSize, Requires<[Not64BitMode]>;<br>
def PUSHSS32 : I<0x16, RawFrm, (outs), (ins),<br>
- "push{l}\t{%ss|ss}", [], IIC_PUSH_SR>, Requires<[Not64BitMode]>;<br>
+ "push{l}\t{%ss|ss}", [], IIC_PUSH_SR>,<br>
+ OpSize16, Requires<[Not64BitMode]>;<br>
def PUSHDS16 : I<0x1E, RawFrm, (outs), (ins),<br>
- "push{w}\t{%ds|ds}", [], IIC_PUSH_SR>, Requires<[Not64BitMode]>,<br>
- OpSize;<br>
+ "push{w}\t{%ds|ds}", [], IIC_PUSH_SR>,<br>
+ OpSize, Requires<[Not64BitMode]>;<br>
def PUSHDS32 : I<0x1E, RawFrm, (outs), (ins),<br>
- "push{l}\t{%ds|ds}", [], IIC_PUSH_SR>, Requires<[Not64BitMode]>;<br>
+ "push{l}\t{%ds|ds}", [], IIC_PUSH_SR>,<br>
+ OpSize16, Requires<[Not64BitMode]>;<br>
def PUSHES16 : I<0x06, RawFrm, (outs), (ins),<br>
- "push{w}\t{%es|es}", [], IIC_PUSH_SR>, Requires<[Not64BitMode]>,<br>
- OpSize;<br>
+ "push{w}\t{%es|es}", [], IIC_PUSH_SR>,<br>
+ OpSize, Requires<[Not64BitMode]>;<br>
def PUSHES32 : I<0x06, RawFrm, (outs), (ins),<br>
- "push{l}\t{%es|es}", [], IIC_PUSH_SR>, Requires<[Not64BitMode]>;<br>
-<br>
+ "push{l}\t{%es|es}", [], IIC_PUSH_SR>,<br>
+ OpSize16, Requires<[Not64BitMode]>;<br>
def PUSHFS16 : I<0xa0, RawFrm, (outs), (ins),<br>
"push{w}\t{%fs|fs}", [], IIC_PUSH_SR>, OpSize, TB;<br>
def PUSHFS32 : I<0xa0, RawFrm, (outs), (ins),<br>
- "push{l}\t{%fs|fs}", [], IIC_PUSH_SR>, TB, Requires<[Not64BitMode]>;<br>
+ "push{l}\t{%fs|fs}", [], IIC_PUSH_SR>, TB,<br>
+ OpSize16, Requires<[Not64BitMode]>;<br>
def PUSHGS16 : I<0xa8, RawFrm, (outs), (ins),<br>
"push{w}\t{%gs|gs}", [], IIC_PUSH_SR>, OpSize, TB;<br>
def PUSHGS32 : I<0xa8, RawFrm, (outs), (ins),<br>
- "push{l}\t{%gs|gs}", [], IIC_PUSH_SR>, TB, Requires<[Not64BitMode]>;<br>
-<br>
+ "push{l}\t{%gs|gs}", [], IIC_PUSH_SR>, TB,<br>
+ OpSize16, Requires<[Not64BitMode]>;<br>
def PUSHFS64 : I<0xa0, RawFrm, (outs), (ins),<br>
"push{q}\t{%fs|fs}", [], IIC_PUSH_SR>, TB;<br>
def PUSHGS64 : I<0xa8, RawFrm, (outs), (ins),<br>
@@ -288,33 +297,35 @@ def POPSS16 : I<0x17, RawFrm, (outs), (ins),<br>
OpSize, Requires<[Not64BitMode]>;<br>
def POPSS32 : I<0x17, RawFrm, (outs), (ins),<br>
"pop{l}\t{%ss|ss}", [], IIC_POP_SR_SS>,<br>
- Requires<[Not64BitMode]>;<br>
+ OpSize16, Requires<[Not64BitMode]>;<br>
<br>
def POPDS16 : I<0x1F, RawFrm, (outs), (ins),<br>
"pop{w}\t{%ds|ds}", [], IIC_POP_SR>,<br>
OpSize, Requires<[Not64BitMode]>;<br>
def POPDS32 : I<0x1F, RawFrm, (outs), (ins),<br>
"pop{l}\t{%ds|ds}", [], IIC_POP_SR>,<br>
- Requires<[Not64BitMode]>;<br>
+ OpSize16, Requires<[Not64BitMode]>;<br>
<br>
def POPES16 : I<0x07, RawFrm, (outs), (ins),<br>
"pop{w}\t{%es|es}", [], IIC_POP_SR>,<br>
OpSize, Requires<[Not64BitMode]>;<br>
def POPES32 : I<0x07, RawFrm, (outs), (ins),<br>
"pop{l}\t{%es|es}", [], IIC_POP_SR>,<br>
- Requires<[Not64BitMode]>;<br>
+ OpSize16, Requires<[Not64BitMode]>;<br>
<br>
def POPFS16 : I<0xa1, RawFrm, (outs), (ins),<br>
"pop{w}\t{%fs|fs}", [], IIC_POP_SR>, OpSize, TB;<br>
def POPFS32 : I<0xa1, RawFrm, (outs), (ins),<br>
- "pop{l}\t{%fs|fs}", [], IIC_POP_SR>, TB, Requires<[Not64BitMode]>;<br>
+ "pop{l}\t{%fs|fs}", [], IIC_POP_SR>, TB,<br>
+ OpSize16, Requires<[Not64BitMode]>;<br>
def POPFS64 : I<0xa1, RawFrm, (outs), (ins),<br>
"pop{q}\t{%fs|fs}", [], IIC_POP_SR>, TB;<br>
<br>
def POPGS16 : I<0xa9, RawFrm, (outs), (ins),<br>
"pop{w}\t{%gs|gs}", [], IIC_POP_SR>, OpSize, TB;<br>
def POPGS32 : I<0xa9, RawFrm, (outs), (ins),<br>
- "pop{l}\t{%gs|gs}", [], IIC_POP_SR>, TB, Requires<[Not64BitMode]>;<br>
+ "pop{l}\t{%gs|gs}", [], IIC_POP_SR>, TB,<br>
+ OpSize16, Requires<[Not64BitMode]>;<br>
def POPGS64 : I<0xa9, RawFrm, (outs), (ins),<br>
"pop{q}\t{%gs|gs}", [], IIC_POP_SR>, TB;<br>
<br>
@@ -322,31 +333,31 @@ def POPGS64 : I<0xa9, RawFrm, (outs), (ins),<br>
def LDS16rm : I<0xc5, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),<br>
"lds{w}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, OpSize;<br>
def LDS32rm : I<0xc5, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),<br>
- "lds{l}\t{$src, $dst|$dst, $src}", [], IIC_LXS>;<br>
+ "lds{l}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, OpSize16;<br>
<br>
def LSS16rm : I<0xb2, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),<br>
"lss{w}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, TB, OpSize;<br>
def LSS32rm : I<0xb2, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),<br>
- "lss{l}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, TB;<br>
+ "lss{l}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, TB, OpSize16;<br>
def LSS64rm : RI<0xb2, MRMSrcMem, (outs GR64:$dst), (ins opaque80mem:$src),<br>
"lss{q}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, TB;<br>
<br>
def LES16rm : I<0xc4, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),<br>
"les{w}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, OpSize;<br>
def LES32rm : I<0xc4, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),<br>
- "les{l}\t{$src, $dst|$dst, $src}", [], IIC_LXS>;<br>
+ "les{l}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, OpSize16;<br>
<br>
def LFS16rm : I<0xb4, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),<br>
"lfs{w}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, TB, OpSize;<br>
def LFS32rm : I<0xb4, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),<br>
- "lfs{l}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, TB;<br>
+ "lfs{l}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, TB, OpSize16;<br>
def LFS64rm : RI<0xb4, MRMSrcMem, (outs GR64:$dst), (ins opaque80mem:$src),<br>
"lfs{q}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, TB;<br>
<br>
def LGS16rm : I<0xb5, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),<br>
"lgs{w}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, TB, OpSize;<br>
def LGS32rm : I<0xb5, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),<br>
- "lgs{l}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, TB;<br>
+ "lgs{l}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, TB, OpSize16;<br>
<br>
def LGS64rm : RI<0xb5, MRMSrcMem, (outs GR64:$dst), (ins opaque80mem:$src),<br>
"lgs{q}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, TB;<br>
@@ -369,17 +380,17 @@ let SchedRW = [WriteSystem] in {<br>
def SGDT16m : I<0x01, MRM0m, (outs opaque48mem:$dst), (ins),<br>
"sgdt{w}\t$dst", [], IIC_SGDT>, TB, OpSize, Requires<[Not64BitMode]>;<br>
def SGDTm : I<0x01, MRM0m, (outs opaque48mem:$dst), (ins),<br>
- "sgdt\t$dst", [], IIC_SGDT>, TB;<br>
+ "sgdt\t$dst", [], IIC_SGDT>, OpSize16, TB;<br>
def SIDT16m : I<0x01, MRM1m, (outs opaque48mem:$dst), (ins),<br>
"sidt{w}\t$dst", [], IIC_SIDT>, TB, OpSize, Requires<[Not64BitMode]>;<br>
def SIDTm : I<0x01, MRM1m, (outs opaque48mem:$dst), (ins),<br>
- "sidt\t$dst", []>, TB;<br>
+ "sidt\t$dst", []>, OpSize16, TB;<br>
def SLDT16r : I<0x00, MRM0r, (outs GR16:$dst), (ins),<br>
"sldt{w}\t$dst", [], IIC_SLDT>, TB, OpSize;<br>
def SLDT16m : I<0x00, MRM0m, (outs i16mem:$dst), (ins),<br>
"sldt{w}\t$dst", [], IIC_SLDT>, TB;<br>
def SLDT32r : I<0x00, MRM0r, (outs GR32:$dst), (ins),<br>
- "sldt{l}\t$dst", [], IIC_SLDT>, TB;<br>
+ "sldt{l}\t$dst", [], IIC_SLDT>, OpSize16, TB;<br>
<br>
// LLDT is not interpreted specially in 64-bit mode because there is no sign<br>
// extension.<br>
@@ -391,11 +402,11 @@ def SLDT64m : RI<0x00, MRM0m, (outs i16mem:$dst), (ins),<br>
def LGDT16m : I<0x01, MRM2m, (outs), (ins opaque48mem:$src),<br>
"lgdt{w}\t$src", [], IIC_LGDT>, TB, OpSize, Requires<[Not64BitMode]>;<br>
def LGDTm : I<0x01, MRM2m, (outs), (ins opaque48mem:$src),<br>
- "lgdt\t$src", [], IIC_LGDT>, TB;<br>
+ "lgdt\t$src", [], IIC_LGDT>, OpSize16, TB;<br>
def LIDT16m : I<0x01, MRM3m, (outs), (ins opaque48mem:$src),<br>
"lidt{w}\t$src", [], IIC_LIDT>, TB, OpSize, Requires<[Not64BitMode]>;<br>
def LIDTm : I<0x01, MRM3m, (outs), (ins opaque48mem:$src),<br>
- "lidt\t$src", [], IIC_LIDT>, TB;<br>
+ "lidt\t$src", [], IIC_LIDT>, OpSize16, TB;<br>
def LLDT16r : I<0x00, MRM2r, (outs), (ins GR16:$src),<br>
"lldt{w}\t$src", [], IIC_LLDT_REG>, TB;<br>
def LLDT16m : I<0x00, MRM2m, (outs), (ins i16mem:$src),<br>
@@ -412,7 +423,7 @@ def RDPMC : I<0x33, RawFrm, (outs), (ins), "rdpmc", [], IIC_RDPMC>, TB;<br>
def SMSW16r : I<0x01, MRM4r, (outs GR16:$dst), (ins),<br>
"smsw{w}\t$dst", [], IIC_SMSW>, OpSize, TB;<br>
def SMSW32r : I<0x01, MRM4r, (outs GR32:$dst), (ins),<br>
- "smsw{l}\t$dst", [], IIC_SMSW>, TB;<br>
+ "smsw{l}\t$dst", [], IIC_SMSW>, OpSize16, TB;<br>
// no m form encodable; use SMSW16m<br>
def SMSW64r : RI<0x01, MRM4r, (outs GR64:$dst), (ins),<br>
"smsw{q}\t$dst", [], IIC_SMSW>, TB;<br>
diff --git a/test/MC/X86/x86-16.s b/test/MC/X86/x86-16.s<br>
index 115132d..d160d46 100644<br>
--- a/test/MC/X86/x86-16.s<br>
+++ b/test/MC/X86/x86-16.s<br>
@@ -2,6 +2,9 @@<br>
<br>
.code16<br>
<br>
+ movl $0x12345678, %ebx<br>
+// CHECK: movl<br>
+// CHECK: encoding: [0x66,0xbb,0x78,0x56,0x34,0x12]<br>
pause<br>
// CHECK: pause<br>
// CHECK: encoding: [0xf3,0x90]<br>
@@ -24,12 +27,28 @@<br>
// CHECK: encoding: [0x0f,0x01,0xf9]<br>
<br>
<br>
+// CHECK: movl %eax, 16(%ebp) # encoding: [0x67,0x66,0x89,0x45,0x10]<br>
+ movl %eax, 16(%ebp)<br>
+// CHECK: movl %eax, -16(%ebp) # encoding: [0x67,0x66,0x89,0x45,0xf0]<br>
+ movl %eax, -16(%ebp)<br>
+<br>
// CHECK: testb %bl, %cl # encoding: [0x84,0xcb]<br>
testb %bl, %cl<br>
<br>
+// CHECK: cmpl %eax, %ebx # encoding: [0x66,0x39,0xc3]<br>
+ cmpl %eax, %ebx<br>
+<br>
// CHECK: addw %ax, %ax # encoding: [0x01,0xc0]<br>
addw %ax, %ax<br>
<br>
+// CHECK: shrl %eax # encoding: [0x66,0xd1,0xe8]<br>
+ shrl $1, %eax<br>
+<br>
+// CHECK: shll %eax # encoding: [0x66,0xd1,0xe0]<br>
+ sall $1, %eax<br>
+// CHECK: shll %eax # encoding: [0x66,0xd1,0xe0]<br>
+ sal $1, %eax<br>
+<br>
into<br>
// CHECK: into<br>
// CHECK: encoding: [0xce]<br>
@@ -43,10 +62,143 @@ int $255<br>
// CHECK: int $255<br>
// CHECK: encoding: [0xcd,0xff]<br>
<br>
+// CHECK: pushfl # encoding: [0x66,0x9c]<br>
+ pushfl<br>
+// CHECK: popfl # encoding: [0x66,0x9d]<br>
+ popfl<br>
+<br>
+// CHECK: cmoval %eax, %edx<br>
+// CHECK: encoding: [0x66,0x0f,0x47,0xd0]<br>
+ cmoval %eax,%edx<br>
+<br>
+// CHECK: cmovael %eax, %edx<br>
+// CHECK: encoding: [0x66,0x0f,0x43,0xd0]<br>
+ cmovael %eax,%edx<br>
+<br>
+// CHECK: cmovbel %eax, %edx<br>
+// CHECK: encoding: [0x66,0x0f,0x46,0xd0]<br>
+ cmovbel %eax,%edx<br>
+<br>
+// CHECK: cmovbl %eax, %edx<br>
+// CHECK: encoding: [0x66,0x0f,0x42,0xd0]<br>
+ cmovbl %eax,%edx<br>
+<br>
// CHECK: cmovbw %bx, %bx<br>
cmovnae %bx,%bx<br>
<br>
<br>
+// CHECK: cmovbel %eax, %edx<br>
+// CHECK: encoding: [0x66,0x0f,0x46,0xd0]<br>
+ cmovbel %eax,%edx<br>
+<br>
+// CHECK: cmovbl %eax, %edx<br>
+// CHECK: encoding: [0x66,0x0f,0x42,0xd0]<br>
+ cmovcl %eax,%edx<br>
+<br>
+// CHECK: cmovel %eax, %edx<br>
+// CHECK: encoding: [0x66,0x0f,0x44,0xd0]<br>
+ cmovel %eax,%edx<br>
+<br>
+// CHECK: cmovgl %eax, %edx<br>
+// CHECK: encoding: [0x66,0x0f,0x4f,0xd0]<br>
+ cmovgl %eax,%edx<br>
+<br>
+// CHECK: cmovgel %eax, %edx<br>
+// CHECK: encoding: [0x66,0x0f,0x4d,0xd0]<br>
+ cmovgel %eax,%edx<br>
+<br>
+// CHECK: cmovll %eax, %edx<br>
+// CHECK: encoding: [0x66,0x0f,0x4c,0xd0]<br>
+ cmovll %eax,%edx<br>
+<br>
+// CHECK: cmovlel %eax, %edx<br>
+// CHECK: encoding: [0x66,0x0f,0x4e,0xd0]<br>
+ cmovlel %eax,%edx<br>
+<br>
+// CHECK: cmovbel %eax, %edx<br>
+// CHECK: encoding: [0x66,0x0f,0x46,0xd0]<br>
+ cmovnal %eax,%edx<br>
+<br>
+// CHECK: cmovnel %eax, %edx<br>
+// CHECK: encoding: [0x66,0x0f,0x45,0xd0]<br>
+ cmovnel %eax,%edx<br>
+<br>
+// CHECK: cmovael %eax, %edx<br>
+// CHECK: encoding: [0x66,0x0f,0x43,0xd0]<br>
+ cmovnbl %eax,%edx<br>
+<br>
+// CHECK: cmoval %eax, %edx<br>
+// CHECK: encoding: [0x66,0x0f,0x47,0xd0]<br>
+ cmovnbel %eax,%edx<br>
+<br>
+// CHECK: cmovael %eax, %edx<br>
+// CHECK: encoding: [0x66,0x0f,0x43,0xd0]<br>
+ cmovncl %eax,%edx<br>
+<br>
+// CHECK: cmovnel %eax, %edx<br>
+// CHECK: encoding: [0x66,0x0f,0x45,0xd0]<br>
+ cmovnel %eax,%edx<br>
+<br>
+// CHECK: cmovlel %eax, %edx<br>
+// CHECK: encoding: [0x66,0x0f,0x4e,0xd0]<br>
+ cmovngl %eax,%edx<br>
+<br>
+// CHECK: cmovgel %eax, %edx<br>
+// CHECK: encoding: [0x66,0x0f,0x4d,0xd0]<br>
+ cmovnl %eax,%edx<br>
+<br>
+// CHECK: cmovnel %eax, %edx<br>
+// CHECK: encoding: [0x66,0x0f,0x45,0xd0]<br>
+ cmovnel %eax,%edx<br>
+<br>
+// CHECK: cmovlel %eax, %edx<br>
+// CHECK: encoding: [0x66,0x0f,0x4e,0xd0]<br>
+ cmovngl %eax,%edx<br>
+<br>
+// CHECK: cmovll %eax, %edx<br>
+// CHECK: encoding: [0x66,0x0f,0x4c,0xd0]<br>
+ cmovngel %eax,%edx<br>
+<br>
+// CHECK: cmovgel %eax, %edx<br>
+// CHECK: encoding: [0x66,0x0f,0x4d,0xd0]<br>
+ cmovnll %eax,%edx<br>
+<br>
+// CHECK: cmovgl %eax, %edx<br>
+// CHECK: encoding: [0x66,0x0f,0x4f,0xd0]<br>
+ cmovnlel %eax,%edx<br>
+<br>
+// CHECK: cmovnol %eax, %edx<br>
+// CHECK: encoding: [0x66,0x0f,0x41,0xd0]<br>
+ cmovnol %eax,%edx<br>
+<br>
+// CHECK: cmovnpl %eax, %edx<br>
+// CHECK: encoding: [0x66,0x0f,0x4b,0xd0]<br>
+ cmovnpl %eax,%edx<br>
+<br>
+// CHECK: cmovnsl %eax, %edx<br>
+// CHECK: encoding: [0x66,0x0f,0x49,0xd0]<br>
+ cmovnsl %eax,%edx<br>
+<br>
+// CHECK: cmovnel %eax, %edx<br>
+// CHECK: encoding: [0x66,0x0f,0x45,0xd0]<br>
+ cmovnzl %eax,%edx<br>
+<br>
+// CHECK: cmovol %eax, %edx<br>
+// CHECK: encoding: [0x66,0x0f,0x40,0xd0]<br>
+ cmovol %eax,%edx<br>
+<br>
+// CHECK: cmovpl %eax, %edx<br>
+// CHECK: encoding: [0x66,0x0f,0x4a,0xd0]<br>
+ cmovpl %eax,%edx<br>
+<br>
+// CHECK: cmovsl %eax, %edx<br>
+// CHECK: encoding: [0x66,0x0f,0x48,0xd0]<br>
+ cmovsl %eax,%edx<br>
+<br>
+// CHECK: cmovel %eax, %edx<br>
+// CHECK: encoding: [0x66,0x0f,0x44,0xd0]<br>
+ cmovzl %eax,%edx<br>
+<br>
// CHECK: fmul %st(0)<br>
// CHECK: encoding: [0xd8,0xc8]<br>
fmul %st(0), %st<br>
@@ -71,14 +223,30 @@ cmovnae %bx,%bx<br>
// CHECK: encoding: [0xd8,0xf0]<br>
fdiv %st(0), %st<br>
<br>
+// CHECK: movl %cs, %eax<br>
+// CHECK: encoding: [0x66,0x8c,0xc8]<br>
+ movl %cs, %eax<br>
+<br>
// CHECK: movw %cs, %ax<br>
// CHECK: encoding: [0x8c,0xc8]<br>
movw %cs, %ax<br>
<br>
+// CHECK: movl %cs, (%eax)<br>
+// CHECK: encoding: [0x67,0x66,0x8c,0x08]<br>
+ movl %cs, (%eax)<br>
+<br>
// CHECK: movw %cs, (%eax)<br>
// CHECK: encoding: [0x67,0x8c,0x08]<br>
movw %cs, (%eax)<br>
<br>
+// CHECK: movl %eax, %cs<br>
+// CHECK: encoding: [0x66,0x8e,0xc8]<br>
+ movl %eax, %cs<br>
+<br>
+// CHECK: movl (%eax), %cs<br>
+// CHECK: encoding: [0x67,0x66,0x8e,0x08]<br>
+ movl (%eax), %cs<br>
+<br>
// CHECK: movw (%eax), %cs<br>
// CHECK: encoding: [0x67,0x8e,0x08]<br>
movw (%eax), %cs<br>
@@ -143,6 +311,23 @@ cmovnae %bx,%bx<br>
// CHECK: encoding: [0x9b]<br>
fwait<br>
<br>
+// CHECK: pushal<br>
+// CHECK: encoding: [0x66,0x60]<br>
+ pushal<br>
+<br>
+// CHECK: popal<br>
+// CHECK: encoding: [0x66,0x61]<br>
+ popal<br>
+<br>
+// CHECK: jmpl *8(%eax)<br>
+// CHECK: encoding: [0x67,0x66,0xff,0x60,0x08]<br>
+ jmpl *8(%eax)<br>
+<br>
+// CHECK: lcalll $2, $4660<br>
+// CHECK: encoding: [0x66,0x9a,0x34,0x12,0x00,0x00,0x02,0x00]<br>
+lcalll $0x2, $0x1234<br>
+<br>
+<br>
sysret<br>
// CHECK: sysretl<br>
// CHECK: encoding: [0x0f,0x07]<br>
@@ -175,6 +360,35 @@ pushw %gs<br>
// CHECK: pushw %gs<br>
// CHECK: encoding: [0x0f,0xa8]<br>
<br>
+pushl %cs<br>
+// CHECK: pushl %cs<br>
+// CHECK: encoding: [0x66,0x0e]<br>
+pushl %ds<br>
+// CHECK: pushl %ds<br>
+// CHECK: encoding: [0x66,0x1e]<br>
+pushl %ss<br>
+// CHECK: pushl %ss<br>
+// CHECK: encoding: [0x66,0x16]<br>
+pushl %es<br>
+// CHECK: pushl %es<br>
+// CHECK: encoding: [0x66,0x06]<br>
+pushl %fs<br>
+// CHECK: pushl %fs<br>
+// CHECK: encoding: [0x66,0x0f,0xa0]<br>
+pushl %gs<br>
+// CHECK: pushl %gs<br>
+// CHECK: encoding: [0x66,0x0f,0xa8]<br>
+<br>
+popl %ss<br>
+// CHECK: popl %ss<br>
+// CHECK: encoding: [0x66,0x17]<br>
+popl %ds<br>
+// CHECK: popl %ds<br>
+// CHECK: encoding: [0x66,0x1f]<br>
+popl %es<br>
+// CHECK: popl %es<br>
+// CHECK: encoding: [0x66,0x07]<br>
+<br>
pushfd<br>
// CHECK: pushfl<br>
popfd<br>
@@ -222,12 +436,18 @@ ljmpl $0x7ace,$0x7ace<br>
// CHECK: incw %ax # encoding: [0x40]<br>
incw %ax<br>
<br>
+// CHECK: incl %eax # encoding: [0x66,0x40]<br>
+ incl %eax<br>
+<br>
// CHECK: decb %al # encoding: [0xfe,0xc8]<br>
decb %al<br>
<br>
// CHECK: decw %ax # encoding: [0x48]<br>
decw %ax<br>
<br>
+// CHECK: decl %eax # encoding: [0x66,0x48]<br>
+ decl %eax<br>
+<br>
// CHECK: pshufw $14, %mm4, %mm0 # encoding: [0x0f,0x70,0xc4,0x0e]<br>
pshufw $14, %mm4, %mm0<br>
<br>
@@ -278,6 +498,10 @@ pshufw $90, %mm4, %mm0<br>
// CHECK: encoding: [0x67,0x62,0x58,0x02]<br>
bound 2(%eax),%bx<br>
<br>
+// CHECK: bound 4(%ebx), %ecx<br>
+// CHECK: encoding: [0x67,0x66,0x62,0x4b,0x04]<br>
+ bound 4(%ebx),%ecx<br>
+<br>
// CHECK: arpl %bx, %bx<br>
// CHECK: encoding: [0x63,0xdb]<br>
arpl %bx,%bx<br>
@@ -352,6 +576,12 @@ pshufw $90, %mm4, %mm0<br>
outsw %ds:(%si), %dx<br>
outsw (%si), %dx<br>
<br>
+// CHECK: outsl # encoding: [0x66,0x6f]<br>
+// CHECK: outsl<br>
+ outsl<br>
+ outsl %ds:(%si), %dx<br>
+ outsl (%si), %dx<br>
+<br>
// CHECK: insb # encoding: [0x6c]<br>
// CHECK: insb<br>
insb<br>
@@ -362,6 +592,11 @@ pshufw $90, %mm4, %mm0<br>
insw<br>
insw %dx, %es:(%di)<br>
<br>
+// CHECK: insl # encoding: [0x66,0x6d]<br>
+// CHECK: insl<br>
+ insl<br>
+ insl %dx, %es:(%di)<br>
+<br>
// CHECK: movsb # encoding: [0xa4]<br>
// CHECK: movsb<br>
// CHECK: movsb<br>
@@ -376,6 +611,13 @@ pshufw $90, %mm4, %mm0<br>
movsw %ds:(%si), %es:(%di)<br>
movsw (%si), %es:(%di)<br>
<br>
+// CHECK: movsl # encoding: [0x66,0xa5]<br>
+// CHECK: movsl<br>
+// CHECK: movsl<br>
+ movsl<br>
+ movsl %ds:(%si), %es:(%di)<br>
+ movsl (%si), %es:(%di)<br>
+<br>
// CHECK: lodsb # encoding: [0xac]<br>
// CHECK: lodsb<br>
// CHECK: lodsb<br>
@@ -398,6 +640,17 @@ pshufw $90, %mm4, %mm0<br>
lods %ds:(%si), %ax<br>
lods (%si), %ax<br>
<br>
+// CHECK: lodsl # encoding: [0x66,0xad]<br>
+// CHECK: lodsl<br>
+// CHECK: lodsl<br>
+// CHECK: lodsl<br>
+// CHECK: lodsl<br>
+ lodsl<br>
+ lodsl %ds:(%si), %eax<br>
+ lodsl (%si), %eax<br>
+ lods %ds:(%si), %eax<br>
+ lods (%si), %eax<br>
+<br>
// CHECK: stosb # encoding: [0xaa]<br>
// CHECK: stosb<br>
// CHECK: stosb<br>
@@ -412,10 +665,22 @@ pshufw $90, %mm4, %mm0<br>
stosw %ax, %es:(%di)<br>
stos %ax, %es:(%di)<br>
<br>
+// CHECK: stosl # encoding: [0x66,0xab]<br>
+// CHECK: stosl<br>
+// CHECK: stosl<br>
+ stosl<br>
+ stosl %eax, %es:(%di)<br>
+ stos %eax, %es:(%di)<br>
+<br>
// CHECK: strw<br>
// CHECK: encoding: [0x0f,0x00,0xc8]<br>
str %ax<br>
<br>
+// CHECK: strl<br>
+// CHECK: encoding: [0x66,0x0f,0x00,0xc8]<br>
+ str %eax<br>
+<br>
+<br>
// CHECK: fsubp<br>
// CHECK: encoding: [0xde,0xe1]<br>
fsubp %st,%st(1)<br>
@@ -424,6 +689,18 @@ fsubp %st,%st(1)<br>
// CHECK: encoding: [0xde,0xe2]<br>
fsubp %st, %st(2)<br>
<br>
+// CHECK: xchgl %eax, %eax<br>
+// CHECK: encoding: [0x66,0x90]<br>
+xchgl %eax, %eax<br>
+<br>
// CHECK: xchgw %ax, %ax<br>
// CHECK: encoding: [0x90]<br>
xchgw %ax, %ax<br>
+<br>
+// CHECK: xchgl %ecx, %eax<br>
+// CHECK: encoding: [0x66,0x91]<br>
+xchgl %ecx, %eax<br>
+<br>
+// CHECK: xchgl %ecx, %eax<br>
+// CHECK: encoding: [0x66,0x91]<br>
+xchgl %eax, %ecx<br>
<span class="HOEnZb"><font color="#888888">--<br>
1.8.3.1<br>
<br>
_______________________________________________<br>
llvm-commits mailing list<br>
<a href="mailto:llvm-commits@cs.uiuc.edu">llvm-commits@cs.uiuc.edu</a><br>
<a href="http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits" target="_blank">http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits</a><br>
</font></span></blockquote></div><br><br clear="all"><div><br></div>-- <br>~Craig
</div>