<div dir="ltr"><div class="gmail_extra"><div class="gmail_quote">On Mon, Dec 30, 2013 at 8:24 AM, Kristof Beyls <span dir="ltr"><<a href="mailto:kristof.beyls@arm.com" target="_blank">kristof.beyls@arm.com</a>></span> wrote:<br>
<blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left-width:1px;border-left-color:rgb(204,204,204);border-left-style:solid;padding-left:1ex">Hi Saleem,<br>
<br>
It seems this commit introduced a regression.<br>
<br>
Before this commit, I get:<br>
$ echo "FSTMIAXLS r0,{d0}" | llvm-mc -mcpu=cortex-a15 -triple armv7<br>
-show-encoding<br>
.text<br>
fstmiaxls r0, {d0} @ encoding: [0x03,0x0b,0x80,0x9c]<br>
<br>
After this commit, I get:<br>
$ echo "FSTMIAXLS r0,{d0}" | llvm-mc -mcpu=cortex-a15 -triple armv7<br>
-show-encoding<br>
.text<br>
<stdin>:1:14: error: VFP/Neon single precision register expected<br>
FSTMIAXLS r0,{d0}<br>
^<br>
Would it be possible to fix this regression (and add the necessary test<br>
cases<br>
that trigger this bug)?<br>
I'm not 100% sure, but at first sight it seems that the use of "Name.back()"<br>
might not be the correct way to find out whether the mnemonic was FxxMS,<br>
FxxMD or FxxMX, when condition codes are present.<br></blockquote><div><br></div><div>Sorry about that. r198235 should address the regression. I've also added appropriate tests for the four predicates which end with an s.</div>
<div> </div><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left-width:1px;border-left-color:rgb(204,204,204);border-left-style:solid;padding-left:1ex">
Thanks,<br>
<br>
Kristof<br>
<div class=""><div class="h5"><br>
> -----Original Message-----<br>
> From: <a href="mailto:llvm-commits-bounces@cs.uiuc.edu">llvm-commits-bounces@cs.uiuc.edu</a> [mailto:<a href="mailto:llvm-commits-">llvm-commits-</a><br>
> <a href="mailto:bounces@cs.uiuc.edu">bounces@cs.uiuc.edu</a>] On Behalf Of Saleem Abdulrasool<br>
> Sent: 29 December 2013 17:59<br>
> To: <a href="mailto:llvm-commits@cs.uiuc.edu">llvm-commits@cs.uiuc.edu</a><br>
> Subject: [llvm] r198172 - ARM: provide VFP aliases for pre-V6 mnemonics<br>
><br>
> Author: compnerd<br>
> Date: Sun Dec 29 11:58:35 2013<br>
> New Revision: 198172<br>
><br>
> URL: <a href="http://llvm.org/viewvc/llvm-project?rev=198172&view=rev" target="_blank">http://llvm.org/viewvc/llvm-project?rev=198172&view=rev</a><br>
> Log:<br>
> ARM: provide VFP aliases for pre-V6 mnemonics<br>
><br>
> In order to provide compatibility with the GNU assembler, provide aliases<br>
for<br>
> pre-UAL mnemonics for floating point operations.<br>
><br>
> Added:<br>
> llvm/trunk/test/MC/ARM/vfp-aliases-diagnostics.s<br>
> llvm/trunk/test/MC/ARM/vfp-aliases.s<br>
> Modified:<br>
> llvm/trunk/lib/Target/ARM/ARMInstrVFP.td<br>
> llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp<br>
><br>
> Modified: llvm/trunk/lib/Target/ARM/ARMInstrVFP.td<br>
> URL: <a href="http://llvm.org/viewvc/llvm-" target="_blank">http://llvm.org/viewvc/llvm-</a><br>
><br>
project/llvm/trunk/lib/Target/ARM/ARMInstrVFP.td?rev=198172&r1=198171&r2=198<br>
17<br>
> 2&view=diff<br>
><br>
============================================================================<br>
==<br>
> --- llvm/trunk/lib/Target/ARM/ARMInstrVFP.td (original)<br>
> +++ llvm/trunk/lib/Target/ARM/ARMInstrVFP.td Sun Dec 29 11:58:35 2013<br>
> @@ -207,6 +207,27 @@ defm VSTM : vfp_ldst_mult<"vstm", 0, IIC<br>
> def : MnemonicAlias<"vldm", "vldmia">;<br>
> def : MnemonicAlias<"vstm", "vstmia">;<br>
><br>
> +// FLDM/FSTM - Load / Store multiple single / double precision registers<br>
for<br>
> +// pre-ARMv6 cores.<br>
> +// These instructions are deprecated!<br>
> +def : VFP2MnemonicAlias<"fldmias", "vldmia">;<br>
> +def : VFP2MnemonicAlias<"fldmdbs", "vldmdb">;<br>
> +def : VFP2MnemonicAlias<"fldmeas", "vldmdb">;<br>
> +def : VFP2MnemonicAlias<"fldmfds", "vldmia">;<br>
> +def : VFP2MnemonicAlias<"fldmiad", "vldmia">;<br>
> +def : VFP2MnemonicAlias<"fldmdbd", "vldmdb">;<br>
> +def : VFP2MnemonicAlias<"fldmead", "vldmdb">;<br>
> +def : VFP2MnemonicAlias<"fldmfdd", "vldmia">;<br>
> +<br>
> +def : VFP2MnemonicAlias<"fstmias", "vstmia">;<br>
> +def : VFP2MnemonicAlias<"fstmdbs", "vstmdb">;<br>
> +def : VFP2MnemonicAlias<"fstmeas", "vstmia">;<br>
> +def : VFP2MnemonicAlias<"fstmfds", "vstmdb">;<br>
> +def : VFP2MnemonicAlias<"fstmiad", "vstmia">;<br>
> +def : VFP2MnemonicAlias<"fstmdbd", "vstmdb">;<br>
> +def : VFP2MnemonicAlias<"fstmead", "vstmia">;<br>
> +def : VFP2MnemonicAlias<"fstmfdd", "vstmdb">;<br>
> +<br>
> def : InstAlias<"vpush${p} $r", (VSTMDDB_UPD SP, pred:$p,<br>
dpr_reglist:$r)>,<br>
> Requires<[HasVFP2]>;<br>
> def : InstAlias<"vpush${p} $r", (VSTMSDB_UPD SP, pred:$p,<br>
spr_reglist:$r)>,<br>
> @@ -247,7 +268,7 @@ multiclass vfp_ldstx_mult<string asm, bi<br>
> AXXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, dpr_reglist:$regs,<br>
> variable_ops),<br>
> IndexModeUpd, !strconcat(asm, "dbx${p}\t$Rn!, $regs"), "$Rn =<br>
$wb",<br>
> []> {<br>
> let Inst{24-23} = 0b10; // Decrement Before<br>
> - let Inst{21} = 1;<br>
> + let Inst{21} = 1; // Writeback<br>
> let Inst{20} = L_bit;<br>
> }<br>
> }<br>
> @@ -255,6 +276,12 @@ multiclass vfp_ldstx_mult<string asm, bi<br>
> defm FLDM : vfp_ldstx_mult<"fldm", 1>;<br>
> defm FSTM : vfp_ldstx_mult<"fstm", 0>;<br>
><br>
> +def : VFP2MnemonicAlias<"fldmeax", "fldmdbx">;<br>
> +def : VFP2MnemonicAlias<"fldmfdx", "fldmiax">;<br>
> +<br>
> +def : VFP2MnemonicAlias<"fstmeax", "fstmiax">;<br>
> +def : VFP2MnemonicAlias<"fstmfdx", "fstmdbx">;<br>
> +<br>
><br>
//===----------------------------------------------------------------------<br>
> ===//<br>
> // FP Binary Operations.<br>
> //<br>
><br>
> Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp<br>
> URL: <a href="http://llvm.org/viewvc/llvm-" target="_blank">http://llvm.org/viewvc/llvm-</a><br>
><br>
project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=198172&r1=1<br>
98<br>
> 171&r2=198172&view=diff<br>
><br>
============================================================================<br>
==<br>
> --- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original)<br>
> +++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Sun Dec 29<br>
11:58:35<br>
> 2013<br>
> @@ -5111,6 +5111,15 @@ static void applyMnemonicAliases(StringR<br>
> bool ARMAsmParser::ParseInstruction(ParseInstructionInfo &Info, StringRef<br>
> Name,<br>
> SMLoc NameLoc,<br>
> SmallVectorImpl<MCParsedAsmOperand*><br>
> &Operands) {<br>
> + // FIXME: Can this be done via tablegen in some fashion?<br>
> + bool HasPrecisionRestrictions;<br>
> + bool AcceptDoublePrecisionOnly;<br>
> + bool AcceptSinglePrecisionOnly;<br>
> + HasPrecisionRestrictions = Name.startswith("fldm") ||<br>
> Name.startswith("fstm");<br>
> + AcceptDoublePrecisionOnly =<br>
> + HasPrecisionRestrictions && (Name.back() == 'd' || Name.back() ==<br>
'x');<br>
> + AcceptSinglePrecisionOnly = HasPrecisionRestrictions && Name.back() ==<br>
's';<br>
> +<br>
> // Apply mnemonic aliases before doing anything else, as the<br>
destination<br>
> // mnemonic may include suffices and we want to handle them normally.<br>
> // The generic tblgen'erated code does this later, at the start of<br>
> @@ -5279,6 +5288,26 @@ bool ARMAsmParser::ParseInstruction(Pars<br>
><br>
> Parser.Lex(); // Consume the EndOfStatement<br>
><br>
> + if (HasPrecisionRestrictions) {<br>
> + ARMOperand *Op = static_cast<ARMOperand*>(Operands.back());<br>
> + assert(Op->isRegList());<br>
> + const SmallVectorImpl<unsigned> &RegList = Op->getRegList();<br>
> + for (SmallVectorImpl<unsigned>::const_iterator RLI = RegList.begin(),<br>
> + RLE = RegList.end();<br>
> + RLI != RLE; ++RLI) {<br>
> + if (AcceptSinglePrecisionOnly &&<br>
> + !ARMMCRegisterClasses[ARM::SPRRegClassID].contains(*RLI))<br>
> + return Error(Op->getStartLoc(),<br>
> + "VFP/Neon single precision register expected");<br>
> + else if (AcceptDoublePrecisionOnly &&<br>
> + !ARMMCRegisterClasses[ARM::DPRRegClassID].contains(*RLI))<br>
> + return Error(Op->getStartLoc(),<br>
> + "VFP/Neon double precision register expected");<br>
> + else<br>
> + llvm_unreachable("must have single or double precision<br>
> restrictions");<br>
> + }<br>
> + }<br>
> +<br>
> // Some instructions, mostly Thumb, have forms for the same mnemonic<br>
that<br>
> // do and don't have a cc_out optional-def operand. With some<br>
spot-checks<br>
> // of the operand list, we can figure out which variant we're trying to<br>
><br>
> Added: llvm/trunk/test/MC/ARM/vfp-aliases-diagnostics.s<br>
> URL:<br>
<a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/vfp-aliases-" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/vfp-aliases-</a><br>
> diagnostics.s?rev=198172&view=auto<br>
><br>
============================================================================<br>
==<br>
> --- llvm/trunk/test/MC/ARM/vfp-aliases-diagnostics.s (added)<br>
> +++ llvm/trunk/test/MC/ARM/vfp-aliases-diagnostics.s Sun Dec 29 11:58:35<br>
2013<br>
> @@ -0,0 +1,97 @@<br>
> +@ RUN: not llvm-mc -triple armv7-eabi -filetype asm -o /dev/null %s 2>&1<br>
\<br>
> +@ RUN: | FileCheck %s<br>
> +<br>
> + .syntax unified<br>
> + .fpu vfp<br>
> +<br>
> + .type aliases,%function<br>
> +aliases:<br>
> + fstmfdd sp!, {s0}<br>
> + fstmead sp!, {s0}<br>
> + fstmdbd sp!, {s0}<br>
> + fstmiad sp!, {s0}<br>
> + fstmfds sp!, {d0}<br>
> + fstmeas sp!, {d0}<br>
> + fstmdbs sp!, {d0}<br>
> + fstmias sp!, {d0}<br>
> +<br>
> + fldmias sp!, {d0}<br>
> + fldmdbs sp!, {d0}<br>
> + fldmeas sp!, {d0}<br>
> + fldmfds sp!, {d0}<br>
> + fldmiad sp!, {s0}<br>
> + fldmdbd sp!, {s0}<br>
> + fldmead sp!, {s0}<br>
> + fldmfdd sp!, {s0}<br>
> +<br>
> + fstmeax sp!, {s0}<br>
> + fldmfdx sp!, {s0}<br>
> +<br>
> + fstmfdx sp!, {s0}<br>
> + fldmeax sp!, {s0}<br>
> +<br>
> +@ CHECK-LABEL: aliases<br>
> +@ CHECK: error: VFP/Neon double precision register expected<br>
> +@ CHECK: fstmfdd sp!, {s0}<br>
> +@ CHECK: ^<br>
> +@ CHECK: error: VFP/Neon double precision register expected<br>
> +@ CHECK: fstmead sp!, {s0}<br>
> +@ CHECK: ^<br>
> +@ CHECK: error: VFP/Neon double precision register expected<br>
> +@ CHECK: fstmdbd sp!, {s0}<br>
> +@ CHECK: ^<br>
> +@ CHECK: error: VFP/Neon double precision register expected<br>
> +@ CHECK: fstmiad sp!, {s0}<br>
> +@ CHECK: ^<br>
> +@ CHECK: error: VFP/Neon single precision register expected<br>
> +@ CHECK: fstmfds sp!, {d0}<br>
> +@ CHECK: ^<br>
> +@ CHECK: error: VFP/Neon single precision register expected<br>
> +@ CHECK: fstmeas sp!, {d0}<br>
> +@ CHECK: ^<br>
> +@ CHECK: error: VFP/Neon single precision register expected<br>
> +@ CHECK: fstmdbs sp!, {d0}<br>
> +@ CHECK: ^<br>
> +@ CHECK: error: VFP/Neon single precision register expected<br>
> +@ CHECK: fstmias sp!, {d0}<br>
> +@ CHECK: ^<br>
> +<br>
> +@ CHECK: error: VFP/Neon single precision register expected<br>
> +@ CHECK: fldmias sp!, {d0}<br>
> +@ CHECK: ^<br>
> +@ CHECK: error: VFP/Neon single precision register expected<br>
> +@ CHECK: fldmdbs sp!, {d0}<br>
> +@ CHECK: ^<br>
> +@ CHECK: error: VFP/Neon single precision register expected<br>
> +@ CHECK: fldmeas sp!, {d0}<br>
> +@ CHECK: ^<br>
> +@ CHECK: error: VFP/Neon single precision register expected<br>
> +@ CHECK: fldmfds sp!, {d0}<br>
> +@ CHECK: ^<br>
> +@ CHECK: error: VFP/Neon double precision register expected<br>
> +@ CHECK: fldmiad sp!, {s0}<br>
> +@ CHECK: ^<br>
> +@ CHECK: error: VFP/Neon double precision register expected<br>
> +@ CHECK: fldmdbd sp!, {s0}<br>
> +@ CHECK: ^<br>
> +@ CHECK: error: VFP/Neon double precision register expected<br>
> +@ CHECK: fldmead sp!, {s0}<br>
> +@ CHECK: ^<br>
> +@ CHECK: error: VFP/Neon double precision register expected<br>
> +@ CHECK: fldmfdd sp!, {s0}<br>
> +@ CHECK: ^<br>
> +<br>
> +@ CHECK: error: VFP/Neon double precision register expected<br>
> +@ CHECK: fstmeax sp!, {s0}<br>
> +@ CHECK: ^<br>
> +@ CHECK: error: VFP/Neon double precision register expected<br>
> +@ CHECK: fldmfdx sp!, {s0}<br>
> +@ CHECK: ^<br>
> +<br>
> +@ CHECK: error: VFP/Neon double precision register expected<br>
> +@ CHECK: fstmfdx sp!, {s0}<br>
> +@ CHECK: ^<br>
> +@ CHECK: error: VFP/Neon double precision register expected<br>
> +@ CHECK: fldmeax sp!, {s0}<br>
> +@ CHECK: ^<br>
> +<br>
><br>
> Added: llvm/trunk/test/MC/ARM/vfp-aliases.s<br>
> URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/vfp-" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/vfp-</a><br>
> aliases.s?rev=198172&view=auto<br>
><br>
============================================================================<br>
==<br>
> --- llvm/trunk/test/MC/ARM/vfp-aliases.s (added)<br>
> +++ llvm/trunk/test/MC/ARM/vfp-aliases.s Sun Dec 29 11:58:35 2013<br>
> @@ -0,0 +1,53 @@<br>
> +@ RUN: llvm-mc -triple armv7-eabi -filetype asm -o - %s | FileCheck %s<br>
> +<br>
> + .syntax unified<br>
> + .fpu vfp<br>
> +<br>
> + .type aliases,%function<br>
> +aliases:<br>
> + fstmfdd sp!, {d0}<br>
> + fstmead sp!, {d0}<br>
> + fstmdbd sp!, {d0}<br>
> + fstmiad sp!, {d0}<br>
> + fstmfds sp!, {s0}<br>
> + fstmeas sp!, {s0}<br>
> + fstmdbs sp!, {s0}<br>
> + fstmias sp!, {s0}<br>
> +<br>
> + fldmias sp!, {s0}<br>
> + fldmdbs sp!, {s0}<br>
> + fldmeas sp!, {s0}<br>
> + fldmfds sp!, {s0}<br>
> + fldmiad sp!, {d0}<br>
> + fldmdbd sp!, {d0}<br>
> + fldmead sp!, {d0}<br>
> + fldmfdd sp!, {d0}<br>
> +<br>
> + fstmeax sp!, {d0}<br>
> + fldmfdx sp!, {d0}<br>
> +<br>
> + fstmfdx sp!, {d0}<br>
> + fldmeax sp!, {d0}<br>
> +<br>
> +@ CHECK-LABEL: aliases<br>
> +@ CHECK: vpush {d0}<br>
> +@ CHECK: vstmia sp!, {d0}<br>
> +@ CHECK: vpush {d0}<br>
> +@ CHECK: vstmia sp!, {d0}<br>
> +@ CHECK: vpush {s0}<br>
> +@ CHECK: vstmia sp!, {s0}<br>
> +@ CHECK: vpush {s0}<br>
> +@ CHECK: vstmia sp!, {s0}<br>
> +@ CHECK: vpop {s0}<br>
> +@ CHECK: vldmdb sp!, {s0}<br>
> +@ CHECK: vldmdb sp!, {s0}<br>
> +@ CHECK: vpop {s0}<br>
> +@ CHECK: vpop {d0}<br>
> +@ CHECK: vldmdb sp!, {d0}<br>
> +@ CHECK: vldmdb sp!, {d0}<br>
> +@ CHECK: vpop {d0}<br>
> +@ CHECK: fstmiax sp!, {d0}<br>
> +@ CHECK: fldmiax sp!, {d0}<br>
> +@ CHECK: fstmdbx sp!, {d0}<br>
> +@ CHECK: fldmdbx sp!, {d0}<br>
> +<br>
><br>
><br>
> _______________________________________________<br>
> llvm-commits mailing list<br>
> <a href="mailto:llvm-commits@cs.uiuc.edu">llvm-commits@cs.uiuc.edu</a><br>
> <a href="http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits" target="_blank">http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits</a><br>
<br>
<br>
<br>
</div></div></blockquote></div><br><br clear="all"><div><br></div>-- <br>Saleem Abdulrasool<br>compnerd (at) compnerd (dot) org
</div></div>