<div dir="ltr">Hi Juergen, how are you guys able to patch your patchpoints with this new nop structure? I'm running into an issue where I now don't know where the nop boundaries are, and thus where my patch can start/end; I'm working around it by just re-filling the region with single-byte nops.</div>
<div class="gmail_extra"><br><br><div class="gmail_quote">On Tue, Dec 3, 2013 at 4:39 PM, Juergen Ributzka <span dir="ltr"><<a href="mailto:juergen@apple.com" target="_blank">juergen@apple.com</a>></span> wrote:<br>
<blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">Author: ributzka<br>
Date: Tue Dec 3 18:39:08 2013<br>
New Revision: 196334<br>
<br>
URL: <a href="http://llvm.org/viewvc/llvm-project?rev=196334&view=rev" target="_blank">http://llvm.org/viewvc/llvm-project?rev=196334&view=rev</a><br>
Log:<br>
[Stackmap] Emit multi-byte nops for X86.<br>
<br>
Added:<br>
llvm/trunk/test/CodeGen/X86/stackmap-nops.ll<br>
llvm/trunk/test/MC/X86/stackmap-nops.ll<br>
Modified:<br>
llvm/trunk/lib/Target/X86/X86MCInstLower.cpp<br>
llvm/trunk/test/CodeGen/X86/patchpoint.ll<br>
<br>
Modified: llvm/trunk/lib/Target/X86/X86MCInstLower.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86MCInstLower.cpp?rev=196334&r1=196333&r2=196334&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86MCInstLower.cpp?rev=196334&r1=196333&r2=196334&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/X86/X86MCInstLower.cpp (original)<br>
+++ llvm/trunk/lib/Target/X86/X86MCInstLower.cpp Tue Dec 3 18:39:08 2013<br>
@@ -674,27 +674,76 @@ static void LowerTlsAddr(MCStreamer &Out<br>
.addExpr(tlsRef));<br>
}<br>
<br>
+/// \brief Emit the optimal amount of multi-byte nops on X86.<br>
+static void EmitNops(MCStreamer &OS, unsigned NumBytes, bool Is64Bit) {<br>
+ // This works only for 64bit. For 32bit we have to do additional checking if<br>
+ // the CPU supports multi-byte nops.<br>
+ assert(Is64Bit && "EmitNops only supports X86-64");<br>
+ while (NumBytes) {<br>
+ unsigned Opc, BaseReg, ScaleVal, IndexReg, Displacement, SegmentReg;<br>
+ Opc = IndexReg = Displacement = SegmentReg = 0;<br>
+ BaseReg = X86::RAX; ScaleVal = 1;<br>
+ switch (NumBytes) {<br>
+ case 0: llvm_unreachable("Zero nops?"); break;<br>
+ case 1: NumBytes -= 1; Opc = X86::NOOP; break;<br>
+ case 2: NumBytes -= 2; Opc = X86::XCHG16ar; break;<br>
+ case 3: NumBytes -= 3; Opc = X86::NOOPL; break;<br>
+ case 4: NumBytes -= 4; Opc = X86::NOOPL; Displacement = 8; break;<br>
+ case 5: NumBytes -= 5; Opc = X86::NOOPL; Displacement = 8;<br>
+ IndexReg = X86::RAX; break;<br>
+ case 6: NumBytes -= 6; Opc = X86::NOOPW; Displacement = 8;<br>
+ IndexReg = X86::RAX; break;<br>
+ case 7: NumBytes -= 7; Opc = X86::NOOPL; Displacement = 512; break;<br>
+ case 8: NumBytes -= 8; Opc = X86::NOOPL; Displacement = 512;<br>
+ IndexReg = X86::RAX; break;<br>
+ case 9: NumBytes -= 9; Opc = X86::NOOPW; Displacement = 512;<br>
+ IndexReg = X86::RAX; break;<br>
+ default: NumBytes -= 10; Opc = X86::NOOPW; Displacement = 512;<br>
+ IndexReg = X86::RAX; SegmentReg = X86::CS; break;<br>
+ }<br>
+<br>
+ unsigned NumPrefixes = std::min(NumBytes, 5U);<br>
+ NumBytes -= NumPrefixes;<br>
+ for (unsigned i = 0; i != NumPrefixes; ++i)<br>
+ OS.EmitBytes("\x66");<br>
+<br>
+ switch (Opc) {<br>
+ default: llvm_unreachable("Unexpected opcode"); break;<br>
+ case X86::NOOP:<br>
+ OS.EmitInstruction(MCInstBuilder(Opc));<br>
+ break;<br>
+ case X86::XCHG16ar:<br>
+ OS.EmitInstruction(MCInstBuilder(Opc).addReg(X86::AX));<br>
+ break;<br>
+ case X86::NOOPL:<br>
+ case X86::NOOPW:<br>
+ OS.EmitInstruction(MCInstBuilder(Opc).addReg(BaseReg).addImm(ScaleVal)<br>
+ .addReg(IndexReg)<br>
+ .addImm(Displacement)<br>
+ .addReg(SegmentReg));<br>
+ break;<br>
+ }<br>
+ } // while (NumBytes)<br>
+}<br>
+<br>
// Lower a stackmap of the form:<br>
// <id>, <shadowBytes>, ...<br>
-static void LowerSTACKMAP(MCStreamer &OutStreamer,<br>
- StackMaps &SM,<br>
- const MachineInstr &MI)<br>
-{<br>
- unsigned NumNOPBytes = MI.getOperand(1).getImm();<br>
+static void LowerSTACKMAP(MCStreamer &OS, StackMaps &SM,<br>
+ const MachineInstr &MI, bool Is64Bit) {<br>
+ unsigned NumBytes = MI.getOperand(1).getImm();<br>
SM.recordStackMap(MI);<br>
// Emit padding.<br>
// FIXME: These nops ensure that the stackmap's shadow is covered by<br>
// instructions from the same basic block, but the nops should not be<br>
// necessary if instructions from the same block follow the stackmap.<br>
- for (unsigned i = 0; i < NumNOPBytes; ++i)<br>
- OutStreamer.EmitInstruction(MCInstBuilder(X86::NOOP));<br>
+ EmitNops(OS, NumBytes, Is64Bit);<br>
}<br>
<br>
// Lower a patchpoint of the form:<br>
// [<def>], <id>, <numBytes>, <target>, <numArgs>, <cc>, ...<br>
-static void LowerPATCHPOINT(MCStreamer &OutStreamer,<br>
- StackMaps &SM,<br>
- const MachineInstr &MI) {<br>
+static void LowerPATCHPOINT(MCStreamer &OS, StackMaps &SM,<br>
+ const MachineInstr &MI, bool Is64Bit) {<br>
+ assert(Is64Bit && "Patchpoint currently only supports X86-64");<br>
SM.recordPatchPoint(MI);<br>
<br>
PatchPointOpers opers(&MI);<br>
@@ -704,22 +753,21 @@ static void LowerPATCHPOINT(MCStreamer &<br>
if (CallTarget) {<br>
// Emit MOV to materialize the target address and the CALL to target.<br>
// This is encoded with 12-13 bytes, depending on which register is used.<br>
- // We conservatively assume that it is 12 bytes and emit in worst case one<br>
- // extra NOP byte.<br>
- EncodedBytes = 12;<br>
- OutStreamer.EmitInstruction(MCInstBuilder(X86::MOV64ri)<br>
- .addReg(MI.getOperand(ScratchIdx).getReg())<br>
- .addImm(CallTarget));<br>
- OutStreamer.EmitInstruction(MCInstBuilder(X86::CALL64r)<br>
- .addReg(MI.getOperand(ScratchIdx).getReg()));<br>
+ unsigned ScratchReg = MI.getOperand(ScratchIdx).getReg();<br>
+ if (X86II::isX86_64ExtendedReg(ScratchReg))<br>
+ EncodedBytes = 13;<br>
+ else<br>
+ EncodedBytes = 12;<br>
+ OS.EmitInstruction(MCInstBuilder(X86::MOV64ri).addReg(ScratchReg)<br>
+ .addImm(CallTarget));<br>
+ OS.EmitInstruction(MCInstBuilder(X86::CALL64r).addReg(ScratchReg));<br>
}<br>
// Emit padding.<br>
unsigned NumBytes = opers.getMetaOper(PatchPointOpers::NBytesPos).getImm();<br>
assert(NumBytes >= EncodedBytes &&<br>
"Patchpoint can't request size less than the length of a call.");<br>
<br>
- for (unsigned i = EncodedBytes; i < NumBytes; ++i)<br>
- OutStreamer.EmitInstruction(MCInstBuilder(X86::NOOP));<br>
+ EmitNops(OS, NumBytes - EncodedBytes, Is64Bit);<br>
}<br>
<br>
void X86AsmPrinter::EmitInstruction(const MachineInstr *MI) {<br>
@@ -813,10 +861,10 @@ void X86AsmPrinter::EmitInstruction(cons<br>
}<br>
<br>
case TargetOpcode::STACKMAP:<br>
- return LowerSTACKMAP(OutStreamer, SM, *MI);<br>
+ return LowerSTACKMAP(OutStreamer, SM, *MI, Subtarget->is64Bit());<br>
<br>
case TargetOpcode::PATCHPOINT:<br>
- return LowerPATCHPOINT(OutStreamer, SM, *MI);<br>
+ return LowerPATCHPOINT(OutStreamer, SM, *MI, Subtarget->is64Bit());<br>
<br>
case X86::MORESTACK_RET:<br>
OutStreamer.EmitInstruction(MCInstBuilder(X86::RET));<br>
<br>
Modified: llvm/trunk/test/CodeGen/X86/patchpoint.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/patchpoint.ll?rev=196334&r1=196333&r2=196334&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/patchpoint.ll?rev=196334&r1=196333&r2=196334&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/X86/patchpoint.ll (original)<br>
+++ llvm/trunk/test/CodeGen/X86/patchpoint.ll Tue Dec 3 18:39:08 2013<br>
@@ -7,10 +7,10 @@ entry:<br>
; CHECK-LABEL: trivial_patchpoint_codegen:<br>
; CHECK: movabsq $-559038736, %r11<br>
; CHECK-NEXT: callq *%r11<br>
-; CHECK-NEXT: nop<br>
+; CHECK-NEXT: xchgw %ax, %ax<br>
; CHECK: movq %rax, %[[REG:r.+]]<br>
; CHECK: callq *%r11<br>
-; CHECK-NEXT: nop<br>
+; CHECK-NEXT: xchgw %ax, %ax<br>
; CHECK: movq %[[REG]], %rax<br>
; CHECK: ret<br>
%resolveCall2 = inttoptr i64 -559038736 to i8*<br>
@@ -84,11 +84,7 @@ define void @small_patchpoint_codegen(i6<br>
entry:<br>
; CHECK-LABEL: small_patchpoint_codegen:<br>
; CHECK: Ltmp<br>
-; CHECK: nop<br>
-; CHECK-NEXT: nop<br>
-; CHECK-NEXT: nop<br>
-; CHECK-NEXT: nop<br>
-; CHECK-NEXT: nop<br>
+; CHECK: nopl 8(%rax,%rax)<br>
; CHECK-NEXT: popq<br>
; CHECK-NEXT: ret<br>
%result = tail call i64 (i32, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.i64(i32 5, i32 5, i8* null, i32 2, i64 %p1, i64 %p2)<br>
<br>
Added: llvm/trunk/test/CodeGen/X86/stackmap-nops.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/stackmap-nops.ll?rev=196334&view=auto" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/stackmap-nops.ll?rev=196334&view=auto</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/X86/stackmap-nops.ll (added)<br>
+++ llvm/trunk/test/CodeGen/X86/stackmap-nops.ll Tue Dec 3 18:39:08 2013<br>
@@ -0,0 +1,230 @@<br>
+; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=corei7 -disable-fp-elim | FileCheck %s<br>
+<br>
+define void @nop_test() {<br>
+entry:<br>
+; CHECK-LABEL: nop_test:<br>
+; CHECK: nop<br>
+; CHECK: xchgw %ax, %ax<br>
+; CHECK: nopl (%rax)<br>
+; CHECK: nopl 8(%rax)<br>
+; CHECK: nopl 8(%rax,%rax)<br>
+; CHECK: nopw 8(%rax,%rax)<br>
+; CHECK: nopl 512(%rax)<br>
+; CHECK: nopl 512(%rax,%rax)<br>
+; CHECK: nopw 512(%rax,%rax)<br>
+; CHECK: nopw %cs:512(%rax,%rax)<br>
+<br>
+; 11<br>
+; CHECK: .byte 102<br>
+; CHECK-NEXT: nopw %cs:512(%rax,%rax)<br>
+<br>
+; 12<br>
+; CHECK: .byte 102<br>
+; CHECK-NEXT: .byte 102<br>
+; CHECK-NEXT: nopw %cs:512(%rax,%rax)<br>
+<br>
+; 13<br>
+; CHECK: .byte 102<br>
+; CHECK-NEXT: .byte 102<br>
+; CHECK-NEXT: .byte 102<br>
+; CHECK-NEXT: nopw %cs:512(%rax,%rax)<br>
+<br>
+; 14<br>
+; CHECK: .byte 102<br>
+; CHECK-NEXT: .byte 102<br>
+; CHECK-NEXT: .byte 102<br>
+; CHECK-NEXT: .byte 102<br>
+; CHECK-NEXT: nopw %cs:512(%rax,%rax)<br>
+<br>
+; 15<br>
+; CHECK: .byte 102<br>
+; CHECK-NEXT: .byte 102<br>
+; CHECK-NEXT: .byte 102<br>
+; CHECK-NEXT: .byte 102<br>
+; CHECK-NEXT: .byte 102<br>
+; CHECK-NEXT: nopw %cs:512(%rax,%rax)<br>
+<br>
+; 16<br>
+; CHECK: .byte 102<br>
+; CHECK-NEXT: .byte 102<br>
+; CHECK-NEXT: .byte 102<br>
+; CHECK-NEXT: .byte 102<br>
+; CHECK-NEXT: .byte 102<br>
+; CHECK-NEXT: nopw %cs:512(%rax,%rax)<br>
+; CHECK-NEXT: nop<br>
+<br>
+; 17<br>
+; CHECK: .byte 102<br>
+; CHECK-NEXT: .byte 102<br>
+; CHECK-NEXT: .byte 102<br>
+; CHECK-NEXT: .byte 102<br>
+; CHECK-NEXT: .byte 102<br>
+; CHECK-NEXT: nopw %cs:512(%rax,%rax)<br>
+; CHECK-NEXT: xchgw %ax, %ax<br>
+<br>
+; 18<br>
+; CHECK: .byte 102<br>
+; CHECK-NEXT: .byte 102<br>
+; CHECK-NEXT: .byte 102<br>
+; CHECK-NEXT: .byte 102<br>
+; CHECK-NEXT: .byte 102<br>
+; CHECK-NEXT: nopw %cs:512(%rax,%rax)<br>
+; CHECK-NEXT: nopl (%rax)<br>
+<br>
+; 19<br>
+; CHECK: .byte 102<br>
+; CHECK-NEXT: .byte 102<br>
+; CHECK-NEXT: .byte 102<br>
+; CHECK-NEXT: .byte 102<br>
+; CHECK-NEXT: .byte 102<br>
+; CHECK-NEXT: nopw %cs:512(%rax,%rax)<br>
+; CHECK-NEXT: nopl 8(%rax)<br>
+<br>
+; 20<br>
+; CHECK: .byte 102<br>
+; CHECK-NEXT: .byte 102<br>
+; CHECK-NEXT: .byte 102<br>
+; CHECK-NEXT: .byte 102<br>
+; CHECK-NEXT: .byte 102<br>
+; CHECK-NEXT: nopw %cs:512(%rax,%rax)<br>
+; CHECK-NEXT: nopl 8(%rax,%rax)<br>
+<br>
+; 21<br>
+; CHECK: .byte 102<br>
+; CHECK-NEXT: .byte 102<br>
+; CHECK-NEXT: .byte 102<br>
+; CHECK-NEXT: .byte 102<br>
+; CHECK-NEXT: .byte 102<br>
+; CHECK-NEXT: nopw %cs:512(%rax,%rax)<br>
+; CHECK-NEXT: nopw 8(%rax,%rax)<br>
+<br>
+; 22<br>
+; CHECK: .byte 102<br>
+; CHECK-NEXT: .byte 102<br>
+; CHECK-NEXT: .byte 102<br>
+; CHECK-NEXT: .byte 102<br>
+; CHECK-NEXT: .byte 102<br>
+; CHECK-NEXT: nopw %cs:512(%rax,%rax)<br>
+; CHECK-NEXT: nopl 512(%rax)<br>
+<br>
+; 23<br>
+; CHECK: .byte 102<br>
+; CHECK-NEXT: .byte 102<br>
+; CHECK-NEXT: .byte 102<br>
+; CHECK-NEXT: .byte 102<br>
+; CHECK-NEXT: .byte 102<br>
+; CHECK-NEXT: nopw %cs:512(%rax,%rax)<br>
+; CHECK-NEXT: nopl 512(%rax,%rax)<br>
+<br>
+; 24<br>
+; CHECK: .byte 102<br>
+; CHECK-NEXT: .byte 102<br>
+; CHECK-NEXT: .byte 102<br>
+; CHECK-NEXT: .byte 102<br>
+; CHECK-NEXT: .byte 102<br>
+; CHECK-NEXT: nopw %cs:512(%rax,%rax)<br>
+; CHECK-NEXT: nopw 512(%rax,%rax)<br>
+<br>
+; 25<br>
+; CHECK: .byte 102<br>
+; CHECK-NEXT: .byte 102<br>
+; CHECK-NEXT: .byte 102<br>
+; CHECK-NEXT: .byte 102<br>
+; CHECK-NEXT: .byte 102<br>
+; CHECK-NEXT: nopw %cs:512(%rax,%rax)<br>
+; CHECK-NEXT: nopw %cs:512(%rax,%rax)<br>
+<br>
+; 26<br>
+; CHECK: .byte 102<br>
+; CHECK-NEXT: .byte 102<br>
+; CHECK-NEXT: .byte 102<br>
+; CHECK-NEXT: .byte 102<br>
+; CHECK-NEXT: .byte 102<br>
+; CHECK-NEXT: nopw %cs:512(%rax,%rax)<br>
+; CHECK-NEXT: .byte 102<br>
+; CHECK-NEXT: nopw %cs:512(%rax,%rax)<br>
+<br>
+; 27<br>
+; CHECK: .byte 102<br>
+; CHECK-NEXT: .byte 102<br>
+; CHECK-NEXT: .byte 102<br>
+; CHECK-NEXT: .byte 102<br>
+; CHECK-NEXT: .byte 102<br>
+; CHECK-NEXT: nopw %cs:512(%rax,%rax)<br>
+; CHECK-NEXT: .byte 102<br>
+; CHECK-NEXT: .byte 102<br>
+; CHECK-NEXT: nopw %cs:512(%rax,%rax)<br>
+<br>
+; 28<br>
+; CHECK: .byte 102<br>
+; CHECK-NEXT: .byte 102<br>
+; CHECK-NEXT: .byte 102<br>
+; CHECK-NEXT: .byte 102<br>
+; CHECK-NEXT: .byte 102<br>
+; CHECK-NEXT: nopw %cs:512(%rax,%rax)<br>
+; CHECK-NEXT: .byte 102<br>
+; CHECK-NEXT: .byte 102<br>
+; CHECK-NEXT: .byte 102<br>
+; CHECK-NEXT: nopw %cs:512(%rax,%rax)<br>
+<br>
+;29<br>
+; CHECK: .byte 102<br>
+; CHECK-NEXT: .byte 102<br>
+; CHECK-NEXT: .byte 102<br>
+; CHECK-NEXT: .byte 102<br>
+; CHECK-NEXT: .byte 102<br>
+; CHECK-NEXT: nopw %cs:512(%rax,%rax)<br>
+; CHECK-NEXT: .byte 102<br>
+; CHECK-NEXT: .byte 102<br>
+; CHECK-NEXT: .byte 102<br>
+; CHECK-NEXT: .byte 102<br>
+; CHECK-NEXT: nopw %cs:512(%rax,%rax)<br>
+<br>
+; 30<br>
+; CHECK: .byte 102<br>
+; CHECK-NEXT: .byte 102<br>
+; CHECK-NEXT: .byte 102<br>
+; CHECK-NEXT: .byte 102<br>
+; CHECK-NEXT: .byte 102<br>
+; CHECK-NEXT: nopw %cs:512(%rax,%rax)<br>
+; CHECK-NEXT: .byte 102<br>
+; CHECK-NEXT: .byte 102<br>
+; CHECK-NEXT: .byte 102<br>
+; CHECK-NEXT: .byte 102<br>
+; CHECK-NEXT: .byte 102<br>
+; CHECK-NEXT: nopw %cs:512(%rax,%rax)<br>
+ tail call void (i32, i32, ...)* @llvm.experimental.stackmap(i32 0, i32 0)<br>
+ tail call void (i32, i32, ...)* @llvm.experimental.stackmap(i32 1, i32 1)<br>
+ tail call void (i32, i32, ...)* @llvm.experimental.stackmap(i32 2, i32 2)<br>
+ tail call void (i32, i32, ...)* @llvm.experimental.stackmap(i32 3, i32 3)<br>
+ tail call void (i32, i32, ...)* @llvm.experimental.stackmap(i32 4, i32 4)<br>
+ tail call void (i32, i32, ...)* @llvm.experimental.stackmap(i32 5, i32 5)<br>
+ tail call void (i32, i32, ...)* @llvm.experimental.stackmap(i32 6, i32 6)<br>
+ tail call void (i32, i32, ...)* @llvm.experimental.stackmap(i32 7, i32 7)<br>
+ tail call void (i32, i32, ...)* @llvm.experimental.stackmap(i32 8, i32 8)<br>
+ tail call void (i32, i32, ...)* @llvm.experimental.stackmap(i32 9, i32 9)<br>
+ tail call void (i32, i32, ...)* @llvm.experimental.stackmap(i32 10, i32 10)<br>
+ tail call void (i32, i32, ...)* @llvm.experimental.stackmap(i32 11, i32 11)<br>
+ tail call void (i32, i32, ...)* @llvm.experimental.stackmap(i32 12, i32 12)<br>
+ tail call void (i32, i32, ...)* @llvm.experimental.stackmap(i32 13, i32 13)<br>
+ tail call void (i32, i32, ...)* @llvm.experimental.stackmap(i32 14, i32 14)<br>
+ tail call void (i32, i32, ...)* @llvm.experimental.stackmap(i32 15, i32 15)<br>
+ tail call void (i32, i32, ...)* @llvm.experimental.stackmap(i32 16, i32 16)<br>
+ tail call void (i32, i32, ...)* @llvm.experimental.stackmap(i32 17, i32 17)<br>
+ tail call void (i32, i32, ...)* @llvm.experimental.stackmap(i32 18, i32 18)<br>
+ tail call void (i32, i32, ...)* @llvm.experimental.stackmap(i32 19, i32 19)<br>
+ tail call void (i32, i32, ...)* @llvm.experimental.stackmap(i32 20, i32 20)<br>
+ tail call void (i32, i32, ...)* @llvm.experimental.stackmap(i32 21, i32 21)<br>
+ tail call void (i32, i32, ...)* @llvm.experimental.stackmap(i32 22, i32 22)<br>
+ tail call void (i32, i32, ...)* @llvm.experimental.stackmap(i32 23, i32 23)<br>
+ tail call void (i32, i32, ...)* @llvm.experimental.stackmap(i32 24, i32 24)<br>
+ tail call void (i32, i32, ...)* @llvm.experimental.stackmap(i32 25, i32 25)<br>
+ tail call void (i32, i32, ...)* @llvm.experimental.stackmap(i32 26, i32 26)<br>
+ tail call void (i32, i32, ...)* @llvm.experimental.stackmap(i32 27, i32 27)<br>
+ tail call void (i32, i32, ...)* @llvm.experimental.stackmap(i32 28, i32 28)<br>
+ tail call void (i32, i32, ...)* @llvm.experimental.stackmap(i32 29, i32 29)<br>
+ tail call void (i32, i32, ...)* @llvm.experimental.stackmap(i32 30, i32 30)<br>
+ ret void<br>
+}<br>
+<br>
+declare void @llvm.experimental.stackmap(i32, i32, ...)<br>
<br>
Added: llvm/trunk/test/MC/X86/stackmap-nops.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/X86/stackmap-nops.ll?rev=196334&view=auto" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/X86/stackmap-nops.ll?rev=196334&view=auto</a><br>
==============================================================================<br>
--- llvm/trunk/test/MC/X86/stackmap-nops.ll (added)<br>
+++ llvm/trunk/test/MC/X86/stackmap-nops.ll Tue Dec 3 18:39:08 2013<br>
@@ -0,0 +1,47 @@<br>
+; RUN: llc -mtriple=x86_64-apple-darwin -mcpu=corei7 -disable-fp-elim -filetype=obj %s -o - | llvm-objdump -d - | FileCheck %s<br>
+; RUN: llc -mtriple=x86_64-apple-darwin -mcpu=corei7 -disable-fp-elim -filetype=asm %s -o - | llvm-mc -filetype=obj - | llvm-objdump -d - | FileCheck %s<br>
+<br>
+define void @nop_test() {<br>
+entry:<br>
+; CHECK: 0: 55<br>
+; CHECK: 1: 48 89 e5<br>
+<br>
+; CHECK: 4: 90<br>
+; CHECK: 5: 66 90<br>
+; CHECK: 7: 0f 1f 00<br>
+; CHECK: a: 0f 1f 40 08<br>
+; CHECK: e: 0f 1f 44 00 08<br>
+; CHECK: 13: 66 0f 1f 44 00 08<br>
+; CHECK: 19: 0f 1f 80 00 02 00 00<br>
+; CHECK: 20: 0f 1f 84 00 00 02 00 00<br>
+; CHECK: 28: 66 0f 1f 84 00 00 02 00 00<br>
+; CHECK: 31: 2e 66 0f 1f 84 00 00 02 00 00<br>
+; CHECK: 3b: 66 2e 66 0f 1f 84 00 00 02 00 00<br>
+; CHECK: 46: 66 66 2e 66 0f 1f 84 00 00 02 00 00<br>
+; CHECK: 52: 66 66 66 2e 66 0f 1f 84 00 00 02 00 00<br>
+; CHECK: 5f: 66 66 66 66 2e 66 0f 1f 84 00 00 02 00 00<br>
+; CHECK: 6d: 66 66 66 66 66 2e 66 0f 1f 84 00 00 02 00 00<br>
+<br>
+; CHECK: 7c: 5d<br>
+; CHECK: 7d: c3<br>
+<br>
+ tail call void (i32, i32, ...)* @llvm.experimental.stackmap(i32 0, i32 0)<br>
+ tail call void (i32, i32, ...)* @llvm.experimental.stackmap(i32 1, i32 1)<br>
+ tail call void (i32, i32, ...)* @llvm.experimental.stackmap(i32 2, i32 2)<br>
+ tail call void (i32, i32, ...)* @llvm.experimental.stackmap(i32 3, i32 3)<br>
+ tail call void (i32, i32, ...)* @llvm.experimental.stackmap(i32 4, i32 4)<br>
+ tail call void (i32, i32, ...)* @llvm.experimental.stackmap(i32 5, i32 5)<br>
+ tail call void (i32, i32, ...)* @llvm.experimental.stackmap(i32 6, i32 6)<br>
+ tail call void (i32, i32, ...)* @llvm.experimental.stackmap(i32 7, i32 7)<br>
+ tail call void (i32, i32, ...)* @llvm.experimental.stackmap(i32 8, i32 8)<br>
+ tail call void (i32, i32, ...)* @llvm.experimental.stackmap(i32 9, i32 9)<br>
+ tail call void (i32, i32, ...)* @llvm.experimental.stackmap(i32 10, i32 10)<br>
+ tail call void (i32, i32, ...)* @llvm.experimental.stackmap(i32 11, i32 11)<br>
+ tail call void (i32, i32, ...)* @llvm.experimental.stackmap(i32 12, i32 12)<br>
+ tail call void (i32, i32, ...)* @llvm.experimental.stackmap(i32 13, i32 13)<br>
+ tail call void (i32, i32, ...)* @llvm.experimental.stackmap(i32 14, i32 14)<br>
+ tail call void (i32, i32, ...)* @llvm.experimental.stackmap(i32 15, i32 15)<br>
+ ret void<br>
+}<br>
+<br>
+declare void @llvm.experimental.stackmap(i32, i32, ...)<br>
<br>
<br>
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</blockquote></div><br></div>