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</o:shapelayout></xml><![endif]--></head><body lang=EN-GB link=blue vlink=purple><div class=WordSection1><p class=MsoNormal><span style='color:#1F497D'>Hi Artyom<o:p></o:p></span></p><p class=MsoNormal><span style='color:#1F497D'><o:p> </o:p></span></p><p class=MsoNormal><span style='color:#1F497D'>LGTM. This brings disassembly into line with the new assembly functionality after r194253. <o:p></o:p></span></p><p class=MsoNormal><span style='color:#1F497D'><o:p> </o:p></span></p><p class=MsoNormal><span style='color:#1F497D'>Ta<o:p></o:p></span></p><p class=MsoNormal><span style='color:#1F497D'>Rich<o:p></o:p></span></p><p class=MsoNormal><span style='color:#1F497D'><o:p> </o:p></span></p><div style='border:none;border-left:solid blue 1.5pt;padding:0cm 0cm 0cm 4.0pt'><div><div style='border:none;border-top:solid #B5C4DF 1.0pt;padding:3.0pt 0cm 0cm 0cm'><p class=MsoNormal><b><span lang=EN-US style='font-size:10.0pt;font-family:"Tahoma","sans-serif"'>From:</span></b><span lang=EN-US style='font-size:10.0pt;font-family:"Tahoma","sans-serif"'> llvm-commits-bounces@cs.uiuc.edu [mailto:llvm-commits-bounces@cs.uiuc.edu] <b>On Behalf Of </b>Artyom Skrobov<br><b>Sent:</b> 06 November 2013 13:04<br><b>To:</b> llvm-commits@cs.uiuc.edu<br><b>Subject:</b> [ARM] Handling for coprocessor instructions that are undefined starting from ARMv8<o:p></o:p></span></p></div></div><p class=MsoNormal><o:p> </o:p></p><p class=MsoNormal>Hello,<o:p></o:p></p><p class=MsoNormal><o:p> </o:p></p><p class=MsoNormal>v8 ARMARM has restricted the list of coprocessors supported in AArch32 to the four required for the legacy code.<o:p></o:p></p><p class=MsoNormal>(Section E1.4 Coprocessor support: The only supported coprocessors in ARMv8 are CP15, CP14, CP10 and CP11.)<o:p></o:p></p><p class=MsoNormal><o:p> </o:p></p><p class=MsoNormal>The coprocessor instructions operating on any coprocessors not in this list are to be undefined, starting from ARMv8.<o:p></o:p></p><p class=MsoNormal>(e.g. Section F7.1.204: If no coprocessor can execute the instruction, an Undefined Instruction exception is generated.)<o:p></o:p></p><p class=MsoNormal><o:p> </o:p></p><p class=MsoNormal>CP10 and CP11, used for the FP/NEON operations, are already excluded from the list of valid operands for the generic coprocessor instructions.<o:p></o:p></p><p class=MsoNormal>We’re proposing a patchset to further restrict the valid ranges for coprocessor operands, starting from ARMv8, as specified in Section G3.15.2:<o:p></o:p></p><p class=MsoNormal><o:p> </o:p></p><p class=MsoNormal>* STC and LDC are only defined for CP14<o:p></o:p></p><p class=MsoNormal>* MCRR, MRRC, MRC, MCR are defined for CP14 and CP15<o:p></o:p></p><p class=MsoNormal>* CDP, CDP2, MCR2, MRC2, MCRR2, MRRC2, LDC2, STC2 are no longer defined for any coprocessor<o:p></o:p></p><p class=MsoNormal><o:p> </o:p></p><p class=MsoNormal>Our patchset consists of three patches. The first one exports getSubtargetInfo() from MCDisassembler public interface, to allow architecture-aware disassembly, which had not been required until now. The two other patches implement the necessary changes for ARM and Thumb encodings, correspondingly. The last patch also deletes 4KLOC from test/MC/ARM/v8_IT_manual.s – these tested a bunch of encodings which are in fact invalid.<o:p></o:p></p><p class=MsoNormal><o:p> </o:p></p><p class=MsoNormal>OK to commit this?<o:p></o:p></p></div></div></body></html>