<html><head><meta http-equiv="Content-Type" content="text/html charset=us-ascii"></head><body style="word-wrap: break-word; -webkit-nbsp-mode: space; -webkit-line-break: after-white-space;"><br><div><div>On Oct 16, 2013, at 6:06 AM, Benjamin Kramer <<a href="mailto:benny.kra@gmail.com">benny.kra@gmail.com</a>> wrote:</div><br class="Apple-interchange-newline"><blockquote type="cite"><div style="font-size: 12px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; orphans: auto; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; widows: auto; word-spacing: 0px; -webkit-text-stroke-width: 0px;"><br>On 15.10.2013, at 05:39, Andrew Trick <<a href="mailto:atrick@apple.com">atrick@apple.com</a>> wrote:<br><br><blockquote type="cite">Author: atrick<br>Date: Mon Oct 14 22:39:43 2013<br>New Revision: 192669<br><br>URL: <a href="http://llvm.org/viewvc/llvm-project?rev=192669&view=rev">http://llvm.org/viewvc/llvm-project?rev=192669&view=rev</a><br>Log:<br>Improve on r192635, ExeDepsFix for avx, and add a test case.<br><br><a href="rdar:15221834">rdar:15221834</a> False AVX register dependencies cause 5x slowdown on<br>flops-5/6 and significant slowdown on several others.<br><br>This was blocking the switch to MI-Sched.<br><br>Added:<br> llvm/trunk/test/CodeGen/X86/break-avx-dep.ll<br>Modified:<br> llvm/trunk/lib/CodeGen/ExecutionDepsFix.cpp<br><br>Modified: llvm/trunk/lib/CodeGen/ExecutionDepsFix.cpp<br>URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/ExecutionDepsFix.cpp?rev=192669&r1=192668&r2=192669&view=diff">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/ExecutionDepsFix.cpp?rev=192669&r1=192668&r2=192669&view=diff</a><br>==============================================================================<br>--- llvm/trunk/lib/CodeGen/ExecutionDepsFix.cpp (original)<br>+++ llvm/trunk/lib/CodeGen/ExecutionDepsFix.cpp Mon Oct 14 22:39:43 2013<br>@@ -557,6 +557,9 @@ void ExeDepsFix::processUndefReads(Machi<br><br> for (MachineBasicBlock::reverse_iterator I = MBB->rbegin(), E = MBB->rend();<br> I != E; ++I) {<br>+ // Update liveness, including the current instrucion's defs.<br>+ LiveUnits.stepBackward(*I, *TRI);<br>+<br> if (UndefMI == &*I) {<br> if (!LiveUnits.contains(UndefMI->getOperand(OpIdx).getReg(), *TRI))<br> TII->breakPartialRegDependency(UndefMI, OpIdx, TRI);<br>@@ -568,7 +571,6 @@ void ExeDepsFix::processUndefReads(Machi<br> UndefMI = UndefReads.back().first;<br> OpIdx = UndefReads.back().second;<br> }<br>- LiveUnits.stepBackward(*I, *TRI);<br> }<br>}<br><br><br>Added: llvm/trunk/test/CodeGen/X86/break-avx-dep.ll<br>URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/break-avx-dep.ll?rev=192669&view=auto">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/break-avx-dep.ll?rev=192669&view=auto</a><br>==============================================================================<br>--- llvm/trunk/test/CodeGen/X86/break-avx-dep.ll (added)<br>+++ llvm/trunk/test/CodeGen/X86/break-avx-dep.ll Mon Oct 14 22:39:43 2013<br>@@ -0,0 +1,29 @@<br>+; RUN: llc < %s -march=x86-64 -mattr=+avx | FileCheck %s<br>+;<br>+; <a href="rdar:15221834">rdar:15221834</a> False AVX register dependencies cause 5x slowdown on<br>+; flops-6. Make sure the unused register read by vcvtsi2sdq is zeroed<br>+; to avoid cyclic dependence on a write to the same register in a<br>+; previous iteration.<br>+<br>+; CHECK-LABEL: t1:<br>+; CHECK-LABEL: %loop<br>+; CHECK: vxorps %[[REG:xmm.]], %{{xmm.}}, %{{xmm.}}<br>+; CHECK: vcvtsi2sdq %{{r..}}, %[[REG]], %{{xmm.}}<br>+define i64 @t1(i64* nocapture %x, double* nocapture %y) nounwind {<br>+entry:<br>+ %vx = load i64* %x<br>+ br label %loop<br>+loop:<br>+ %i = phi i64 [ 1, %entry ], [ %inc, %loop ]<br>+ %s1 = phi i64 [ %vx, %entry ], [ %s2, %loop ]<br>+ %fi = sitofp i64 %i to double<br>+ %vy = load double* %y<br>+ %fipy = fadd double %fi, %vy<br>+ %iipy = fptosi double %fipy to i64<br>+ %s2 = add i64 %s1, %iipy<br>+ %inc = add nsw i64 %i, 1<br>+ %exitcond = icmp eq i64 %inc, 156250000<br>+ br i1 %exitcond, label %ret, label %loop<br>+ret:<br>+ ret i64 %s2<br>+}<br></blockquote><br>I'm not exactly sure why, but this test fails on the atom buildbot. You can reproduce it with -mcpu=atom, looks like the vxorps is missing there.<br></div></blockquote><div><br></div>Thank you. It turned out to be a minor PostRA scheduling bug. r192824.</div><br><div>-Andy</div></body></html>