<div dir="ltr"><div><div class="gmail_extra"><br><br><div class="gmail_quote">On Tue, Oct 8, 2013 at 4:43 AM, Roman Divacky <span dir="ltr"><<a href="mailto:rdivacky@freebsd.org" target="_blank">rdivacky@freebsd.org</a>></span> wrote:<br>
<blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">Hi Venkatraman,<br>
<br>
Do you plan to work on MCJIT as well? That would be useful for -integrated-as<br>
as well.<br>
<span class="HOEnZb"><font color="#888888"><br></font></span></blockquote><div><br></div><div>Yes, I plan to work on MCJIT once I have implemented AsmParser for SPARC.<br> </div><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">
<span class="HOEnZb"><font color="#888888">
Roman<br>
</font></span><div class="HOEnZb"><div class="h5"><br>
On Tue, Oct 08, 2013 at 07:15:22AM -0000, Venkatraman Govindaraju wrote:<br>
> Author: venkatra<br>
> Date: Tue Oct 8 02:15:22 2013<br>
> New Revision: 192176<br>
><br>
> URL: <a href="http://llvm.org/viewvc/llvm-project?rev=192176&view=rev" target="_blank">http://llvm.org/viewvc/llvm-project?rev=192176&view=rev</a><br>
> Log:<br>
> [Sparc] Implement JIT for SPARC.<br>
><br>
> No new testcases. However, this patch makes all supported JIT testcases in<br>
> test/ExecutionEngine pass on Sparc.<br>
><br>
><br>
> Added:<br>
> llvm/trunk/lib/Target/Sparc/SparcCodeEmitter.cpp<br>
> llvm/trunk/lib/Target/Sparc/SparcJITInfo.cpp<br>
> llvm/trunk/lib/Target/Sparc/SparcJITInfo.h<br>
> llvm/trunk/lib/Target/Sparc/SparcRelocations.h<br>
> Modified:<br>
> llvm/trunk/lib/Target/Sparc/CMakeLists.txt<br>
> llvm/trunk/lib/Target/Sparc/LLVMBuild.txt<br>
> llvm/trunk/lib/Target/Sparc/Sparc.h<br>
> llvm/trunk/lib/Target/Sparc/SparcISelLowering.cpp<br>
> llvm/trunk/lib/Target/Sparc/SparcInstrInfo.td<br>
> llvm/trunk/lib/Target/Sparc/SparcTargetMachine.cpp<br>
> llvm/trunk/lib/Target/Sparc/SparcTargetMachine.h<br>
> llvm/trunk/lib/Target/Sparc/TargetInfo/SparcTargetInfo.cpp<br>
><br>
> Modified: llvm/trunk/lib/Target/Sparc/CMakeLists.txt<br>
> URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/CMakeLists.txt?rev=192176&r1=192175&r2=192176&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/CMakeLists.txt?rev=192176&r1=192175&r2=192176&view=diff</a><br>
> ==============================================================================<br>
> --- llvm/trunk/lib/Target/Sparc/CMakeLists.txt (original)<br>
> +++ llvm/trunk/lib/Target/Sparc/CMakeLists.txt Tue Oct 8 02:15:22 2013<br>
> @@ -21,6 +21,8 @@ add_llvm_target(SparcCodeGen<br>
> SparcSubtarget.cpp<br>
> SparcTargetMachine.cpp<br>
> SparcSelectionDAGInfo.cpp<br>
> + SparcJITInfo.cpp<br>
> + SparcCodeEmitter.cpp<br>
> )<br>
><br>
> add_dependencies(LLVMSparcCodeGen SparcCommonTableGen intrinsics_gen)<br>
><br>
> Modified: llvm/trunk/lib/Target/Sparc/LLVMBuild.txt<br>
> URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/LLVMBuild.txt?rev=192176&r1=192175&r2=192176&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/LLVMBuild.txt?rev=192176&r1=192175&r2=192176&view=diff</a><br>
> ==============================================================================<br>
> --- llvm/trunk/lib/Target/Sparc/LLVMBuild.txt (original)<br>
> +++ llvm/trunk/lib/Target/Sparc/LLVMBuild.txt Tue Oct 8 02:15:22 2013<br>
> @@ -23,6 +23,7 @@ type = TargetGroup<br>
> name = Sparc<br>
> parent = Target<br>
> has_asmprinter = 1<br>
> +has_jit = 1<br>
><br>
> [component_1]<br>
> type = Library<br>
><br>
> Modified: llvm/trunk/lib/Target/Sparc/Sparc.h<br>
> URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/Sparc.h?rev=192176&r1=192175&r2=192176&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/Sparc.h?rev=192176&r1=192175&r2=192176&view=diff</a><br>
> ==============================================================================<br>
> --- llvm/trunk/lib/Target/Sparc/Sparc.h (original)<br>
> +++ llvm/trunk/lib/Target/Sparc/Sparc.h Tue Oct 8 02:15:22 2013<br>
> @@ -26,6 +26,8 @@ namespace llvm {<br>
><br>
> FunctionPass *createSparcISelDag(SparcTargetMachine &TM);<br>
> FunctionPass *createSparcDelaySlotFillerPass(TargetMachine &TM);<br>
> + FunctionPass *createSparcJITCodeEmitterPass(SparcTargetMachine &TM,<br>
> + JITCodeEmitter &JCE);<br>
><br>
> } // end namespace llvm;<br>
><br>
><br>
> Added: llvm/trunk/lib/Target/Sparc/SparcCodeEmitter.cpp<br>
> URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcCodeEmitter.cpp?rev=192176&view=auto" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcCodeEmitter.cpp?rev=192176&view=auto</a><br>
> ==============================================================================<br>
> --- llvm/trunk/lib/Target/Sparc/SparcCodeEmitter.cpp (added)<br>
> +++ llvm/trunk/lib/Target/Sparc/SparcCodeEmitter.cpp Tue Oct 8 02:15:22 2013<br>
> @@ -0,0 +1,245 @@<br>
> +//===-- Sparc/SparcCodeEmitter.cpp - Convert Sparc Code to Machine Code ---===//<br>
> +//<br>
> +// The LLVM Compiler Infrastructure<br>
> +//<br>
> +// This file is distributed under the University of Illinois Open Source<br>
> +// License. See LICENSE.TXT for details.<br>
> +//<br>
> +//===---------------------------------------------------------------------===//<br>
> +//<br>
> +// This file contains the pass that transforms the Sparc machine instructions<br>
> +// into relocatable machine code.<br>
> +//<br>
> +//===---------------------------------------------------------------------===//<br>
> +<br>
> +#define DEBUG_TYPE "jit"<br>
> +#include "Sparc.h"<br>
> +#include "MCTargetDesc/SparcBaseInfo.h"<br>
> +#include "SparcRelocations.h"<br>
> +#include "SparcTargetMachine.h"<br>
> +#include "llvm/ADT/Statistic.h"<br>
> +#include "llvm/CodeGen/JITCodeEmitter.h"<br>
> +#include "llvm/CodeGen/MachineFunctionPass.h"<br>
> +#include "llvm/CodeGen/MachineModuleInfo.h"<br>
> +#include "llvm/Support/Debug.h"<br>
> +<br>
> +using namespace llvm;<br>
> +<br>
> +STATISTIC(NumEmitted, "Number of machine instructions emitted");<br>
> +<br>
> +namespace {<br>
> +<br>
> +class SparcCodeEmitter : public MachineFunctionPass {<br>
> + SparcJITInfo *JTI;<br>
> + const SparcInstrInfo *II;<br>
> + const DataLayout *TD;<br>
> + const SparcSubtarget *Subtarget;<br>
> + TargetMachine &TM;<br>
> + JITCodeEmitter &MCE;<br>
> + const std::vector<MachineConstantPoolEntry> *MCPEs;<br>
> + bool IsPIC;<br>
> +<br>
> + void getAnalysisUsage(AnalysisUsage &AU) const {<br>
> + AU.addRequired<MachineModuleInfo> ();<br>
> + MachineFunctionPass::getAnalysisUsage(AU);<br>
> + }<br>
> +<br>
> + static char ID;<br>
> +<br>
> +public:<br>
> + SparcCodeEmitter(TargetMachine &tm, JITCodeEmitter &mce)<br>
> + : MachineFunctionPass(ID), JTI(0), II(0), TD(0),<br>
> + TM(tm), MCE(mce), MCPEs(0),<br>
> + IsPIC(TM.getRelocationModel() == Reloc::PIC_) {}<br>
> +<br>
> + bool runOnMachineFunction(MachineFunction &MF);<br>
> +<br>
> + virtual const char *getPassName() const {<br>
> + return "Sparc Machine Code Emitter";<br>
> + }<br>
> +<br>
> + /// getBinaryCodeForInstr - This function, generated by the<br>
> + /// CodeEmitterGenerator using TableGen, produces the binary encoding for<br>
> + /// machine instructions.<br>
> + uint64_t getBinaryCodeForInstr(const MachineInstr &MI) const;<br>
> +<br>
> + void emitInstruction(MachineBasicBlock::instr_iterator MI,<br>
> + MachineBasicBlock &MBB);<br>
> +<br>
> +private:<br>
> + /// getMachineOpValue - Return binary encoding of operand. If the machine<br>
> + /// operand requires relocation, record the relocation and return zero.<br>
> + unsigned getMachineOpValue(const MachineInstr &MI,<br>
> + const MachineOperand &MO) const;<br>
> +<br>
> + void emitWord(unsigned Word);<br>
> +<br>
> + unsigned getRelocation(const MachineInstr &MI,<br>
> + const MachineOperand &MO) const;<br>
> +<br>
> + void emitGlobalAddress(const GlobalValue *GV, unsigned Reloc) const;<br>
> + void emitExternalSymbolAddress(const char *ES, unsigned Reloc) const;<br>
> + void emitConstPoolAddress(unsigned CPI, unsigned Reloc) const;<br>
> + void emitMachineBasicBlock(MachineBasicBlock *BB, unsigned Reloc) const;<br>
> +};<br>
> +} // end anonymous namespace.<br>
> +<br>
> +char SparcCodeEmitter::ID = 0;<br>
> +<br>
> +bool SparcCodeEmitter::runOnMachineFunction(MachineFunction &MF) {<br>
> + SparcTargetMachine &Target = static_cast<SparcTargetMachine &>(<br>
> + const_cast<TargetMachine &>(MF.getTarget()));<br>
> +<br>
> + JTI = Target.getJITInfo();<br>
> + II = Target.getInstrInfo();<br>
> + TD = Target.getDataLayout();<br>
> + Subtarget = &TM.getSubtarget<SparcSubtarget> ();<br>
> + MCPEs = &MF.getConstantPool()->getConstants();<br>
> + JTI->Initialize(MF, IsPIC);<br>
> + MCE.setModuleInfo(&getAnalysis<MachineModuleInfo> ());<br>
> +<br>
> + do {<br>
> + DEBUG(errs() << "JITTing function '"<br>
> + << MF.getName() << "'\n");<br>
> + MCE.startFunction(MF);<br>
> +<br>
> + for (MachineFunction::iterator MBB = MF.begin(), E = MF.end();<br>
> + MBB != E; ++MBB){<br>
> + MCE.StartMachineBasicBlock(MBB);<br>
> + for (MachineBasicBlock::instr_iterator I = MBB->instr_begin(),<br>
> + E = MBB->instr_end(); I != E;)<br>
> + emitInstruction(*I++, *MBB);<br>
> + }<br>
> + } while (MCE.finishFunction(MF));<br>
> +<br>
> + return false;<br>
> +}<br>
> +<br>
> +void SparcCodeEmitter::emitInstruction(MachineBasicBlock::instr_iterator MI,<br>
> + MachineBasicBlock &MBB) {<br>
> + DEBUG(errs() << "JIT: " << (void*)MCE.getCurrentPCValue() << ":\t" << *MI);<br>
> +<br>
> + MCE.processDebugLoc(MI->getDebugLoc(), true);<br>
> +<br>
> + ++NumEmitted;<br>
> +<br>
> + switch (MI->getOpcode()) {<br>
> + default: {<br>
> + emitWord(getBinaryCodeForInstr(*MI));<br>
> + break;<br>
> + }<br>
> + case TargetOpcode::INLINEASM: {<br>
> + // We allow inline assembler nodes with empty bodies - they can<br>
> + // implicitly define registers, which is ok for JIT.<br>
> + if (MI->getOperand(0).getSymbolName()[0]) {<br>
> + report_fatal_error("JIT does not support inline asm!");<br>
> + }<br>
> + break;<br>
> + }<br>
> + case TargetOpcode::PROLOG_LABEL:<br>
> + case TargetOpcode::EH_LABEL: {<br>
> + MCE.emitLabel(MI->getOperand(0).getMCSymbol());<br>
> + break;<br>
> + }<br>
> + case TargetOpcode::IMPLICIT_DEF:<br>
> + case TargetOpcode::KILL: {<br>
> + // Do nothing.<br>
> + break;<br>
> + }<br>
> + case SP::GETPCX: {<br>
> + report_fatal_error("JIT does not support pseudo instruction GETPCX yet!");<br>
> + break;<br>
> + }<br>
> + }<br>
> +<br>
> + MCE.processDebugLoc(MI->getDebugLoc(), false);<br>
> +}<br>
> +<br>
> +void SparcCodeEmitter::emitWord(unsigned Word) {<br>
> + DEBUG(errs() << " 0x";<br>
> + errs().write_hex(Word) << "\n");<br>
> + MCE.emitWordBE(Word);<br>
> +}<br>
> +<br>
> +/// getMachineOpValue - Return binary encoding of operand. If the machine<br>
> +/// operand requires relocation, record the relocation and return zero.<br>
> +unsigned SparcCodeEmitter::getMachineOpValue(const MachineInstr &MI,<br>
> + const MachineOperand &MO) const {<br>
> + if (MO.isReg())<br>
> + return TM.getRegisterInfo()->getEncodingValue(MO.getReg());<br>
> + else if (MO.isImm())<br>
> + return static_cast<unsigned>(MO.getImm());<br>
> + else if (MO.isGlobal())<br>
> + emitGlobalAddress(MO.getGlobal(), getRelocation(MI, MO));<br>
> + else if (MO.isSymbol())<br>
> + emitExternalSymbolAddress(MO.getSymbolName(), getRelocation(MI, MO));<br>
> + else if (MO.isCPI())<br>
> + emitConstPoolAddress(MO.getIndex(), getRelocation(MI, MO));<br>
> + else if (MO.isMBB())<br>
> + emitMachineBasicBlock(MO.getMBB(), getRelocation(MI, MO));<br>
> + else<br>
> + llvm_unreachable("Unable to encode MachineOperand!");<br>
> + return 0;<br>
> +}<br>
> +unsigned SparcCodeEmitter::getRelocation(const MachineInstr &MI,<br>
> + const MachineOperand &MO) const {<br>
> +<br>
> + unsigned TF = MO.getTargetFlags();<br>
> + switch (TF) {<br>
> + default:<br>
> + case SPII::MO_NO_FLAG: break;<br>
> + case SPII::MO_LO: return SP::reloc_sparc_lo;<br>
> + case SPII::MO_HI: return SP::reloc_sparc_hi;<br>
> + case SPII::MO_H44:<br>
> + case SPII::MO_M44:<br>
> + case SPII::MO_L44:<br>
> + case SPII::MO_HH:<br>
> + case SPII::MO_HM: assert(0 && "FIXME: Implement Medium/Large code model.");<br>
> + }<br>
> +<br>
> + unsigned Opc = MI.getOpcode();<br>
> + switch (Opc) {<br>
> + default: break;<br>
> + case SP::CALL: return SP::reloc_sparc_pc30;<br>
> + case SP::BA:<br>
> + case SP::BCOND:<br>
> + case SP::FBCOND: return SP::reloc_sparc_pc22;<br>
> + case SP::BPXCC: return SP::reloc_sparc_pc19;<br>
> + }<br>
> + llvm_unreachable("unknown reloc!");<br>
> +}<br>
> +<br>
> +void SparcCodeEmitter::emitGlobalAddress(const GlobalValue *GV,<br>
> + unsigned Reloc) const {<br>
> + MCE.addRelocation(MachineRelocation::getGV(MCE.getCurrentPCOffset(), Reloc,<br>
> + const_cast<GlobalValue *>(GV), 0,<br>
> + true));<br>
> +}<br>
> +<br>
> +void SparcCodeEmitter::<br>
> +emitExternalSymbolAddress(const char *ES, unsigned Reloc) const {<br>
> + MCE.addRelocation(MachineRelocation::getExtSym(MCE.getCurrentPCOffset(),<br>
> + Reloc, ES, 0, 0));<br>
> +}<br>
> +<br>
> +void SparcCodeEmitter::<br>
> +emitConstPoolAddress(unsigned CPI, unsigned Reloc) const {<br>
> + MCE.addRelocation(MachineRelocation::getConstPool(MCE.getCurrentPCOffset(),<br>
> + Reloc, CPI, 0, false));<br>
> +}<br>
> +<br>
> +void SparcCodeEmitter::emitMachineBasicBlock(MachineBasicBlock *BB,<br>
> + unsigned Reloc) const {<br>
> + MCE.addRelocation(MachineRelocation::getBB(MCE.getCurrentPCOffset(),<br>
> + Reloc, BB));<br>
> +}<br>
> +<br>
> +<br>
> +/// createSparcJITCodeEmitterPass - Return a pass that emits the collected Sparc<br>
> +/// code to the specified MCE object.<br>
> +FunctionPass *llvm::createSparcJITCodeEmitterPass(SparcTargetMachine &TM,<br>
> + JITCodeEmitter &JCE) {<br>
> + return new SparcCodeEmitter(TM, JCE);<br>
> +}<br>
> +<br>
> +#include "SparcGenCodeEmitter.inc"<br>
><br>
> Modified: llvm/trunk/lib/Target/Sparc/SparcISelLowering.cpp<br>
> URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcISelLowering.cpp?rev=192176&r1=192175&r2=192176&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcISelLowering.cpp?rev=192176&r1=192175&r2=192176&view=diff</a><br>
> ==============================================================================<br>
> --- llvm/trunk/lib/Target/Sparc/SparcISelLowering.cpp (original)<br>
> +++ llvm/trunk/lib/Target/Sparc/SparcISelLowering.cpp Tue Oct 8 02:15:22 2013<br>
> @@ -1668,6 +1668,7 @@ SDValue SparcTargetLowering::makeAddress<br>
> switch(getTargetMachine().getCodeModel()) {<br>
> default:<br>
> llvm_unreachable("Unsupported absolute code model");<br>
> + case CodeModel::JITDefault:<br>
> case CodeModel::Small:<br>
> // abs32.<br>
> return makeHiLoPair(Op, SPII::MO_HI, SPII::MO_LO, DAG);<br>
><br>
> Modified: llvm/trunk/lib/Target/Sparc/SparcInstrInfo.td<br>
> URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcInstrInfo.td?rev=192176&r1=192175&r2=192176&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcInstrInfo.td?rev=192176&r1=192175&r2=192176&view=diff</a><br>
> ==============================================================================<br>
> --- llvm/trunk/lib/Target/Sparc/SparcInstrInfo.td (original)<br>
> +++ llvm/trunk/lib/Target/Sparc/SparcInstrInfo.td Tue Oct 8 02:15:22 2013<br>
> @@ -394,63 +394,63 @@ def LDQFri : F3_2<3, 0b100010,<br>
><br>
> // Section B.4 - Store Integer Instructions, p. 95<br>
> def STBrr : F3_1<3, 0b000101,<br>
> - (outs), (ins MEMrr:$addr, IntRegs:$src),<br>
> - "stb $src, [$addr]",<br>
> - [(truncstorei8 i32:$src, ADDRrr:$addr)]>;<br>
> + (outs), (ins MEMrr:$addr, IntRegs:$rd),<br>
> + "stb $rd, [$addr]",<br>
> + [(truncstorei8 i32:$rd, ADDRrr:$addr)]>;<br>
> def STBri : F3_2<3, 0b000101,<br>
> - (outs), (ins MEMri:$addr, IntRegs:$src),<br>
> - "stb $src, [$addr]",<br>
> - [(truncstorei8 i32:$src, ADDRri:$addr)]>;<br>
> + (outs), (ins MEMri:$addr, IntRegs:$rd),<br>
> + "stb $rd, [$addr]",<br>
> + [(truncstorei8 i32:$rd, ADDRri:$addr)]>;<br>
> def STHrr : F3_1<3, 0b000110,<br>
> - (outs), (ins MEMrr:$addr, IntRegs:$src),<br>
> - "sth $src, [$addr]",<br>
> - [(truncstorei16 i32:$src, ADDRrr:$addr)]>;<br>
> + (outs), (ins MEMrr:$addr, IntRegs:$rd),<br>
> + "sth $rd, [$addr]",<br>
> + [(truncstorei16 i32:$rd, ADDRrr:$addr)]>;<br>
> def STHri : F3_2<3, 0b000110,<br>
> - (outs), (ins MEMri:$addr, IntRegs:$src),<br>
> - "sth $src, [$addr]",<br>
> - [(truncstorei16 i32:$src, ADDRri:$addr)]>;<br>
> + (outs), (ins MEMri:$addr, IntRegs:$rd),<br>
> + "sth $rd, [$addr]",<br>
> + [(truncstorei16 i32:$rd, ADDRri:$addr)]>;<br>
> def STrr : F3_1<3, 0b000100,<br>
> - (outs), (ins MEMrr:$addr, IntRegs:$src),<br>
> - "st $src, [$addr]",<br>
> - [(store i32:$src, ADDRrr:$addr)]>;<br>
> + (outs), (ins MEMrr:$addr, IntRegs:$rd),<br>
> + "st $rd, [$addr]",<br>
> + [(store i32:$rd, ADDRrr:$addr)]>;<br>
> def STri : F3_2<3, 0b000100,<br>
> - (outs), (ins MEMri:$addr, IntRegs:$src),<br>
> - "st $src, [$addr]",<br>
> - [(store i32:$src, ADDRri:$addr)]>;<br>
> + (outs), (ins MEMri:$addr, IntRegs:$rd),<br>
> + "st $rd, [$addr]",<br>
> + [(store i32:$rd, ADDRri:$addr)]>;<br>
><br>
> // Section B.5 - Store Floating-point Instructions, p. 97<br>
> def STFrr : F3_1<3, 0b100100,<br>
> - (outs), (ins MEMrr:$addr, FPRegs:$src),<br>
> - "st $src, [$addr]",<br>
> - [(store f32:$src, ADDRrr:$addr)]>;<br>
> + (outs), (ins MEMrr:$addr, FPRegs:$rd),<br>
> + "st $rd, [$addr]",<br>
> + [(store f32:$rd, ADDRrr:$addr)]>;<br>
> def STFri : F3_2<3, 0b100100,<br>
> - (outs), (ins MEMri:$addr, FPRegs:$src),<br>
> - "st $src, [$addr]",<br>
> - [(store f32:$src, ADDRri:$addr)]>;<br>
> + (outs), (ins MEMri:$addr, FPRegs:$rd),<br>
> + "st $rd, [$addr]",<br>
> + [(store f32:$rd, ADDRri:$addr)]>;<br>
> def STDFrr : F3_1<3, 0b100111,<br>
> - (outs), (ins MEMrr:$addr, DFPRegs:$src),<br>
> - "std $src, [$addr]",<br>
> - [(store f64:$src, ADDRrr:$addr)]>;<br>
> + (outs), (ins MEMrr:$addr, DFPRegs:$rd),<br>
> + "std $rd, [$addr]",<br>
> + [(store f64:$rd, ADDRrr:$addr)]>;<br>
> def STDFri : F3_2<3, 0b100111,<br>
> - (outs), (ins MEMri:$addr, DFPRegs:$src),<br>
> - "std $src, [$addr]",<br>
> - [(store f64:$src, ADDRri:$addr)]>;<br>
> + (outs), (ins MEMri:$addr, DFPRegs:$rd),<br>
> + "std $rd, [$addr]",<br>
> + [(store f64:$rd, ADDRri:$addr)]>;<br>
> def STQFrr : F3_1<3, 0b100110,<br>
> - (outs), (ins MEMrr:$addr, QFPRegs:$src),<br>
> - "stq $src, [$addr]",<br>
> - [(store f128:$src, ADDRrr:$addr)]>,<br>
> + (outs), (ins MEMrr:$addr, QFPRegs:$rd),<br>
> + "stq $rd, [$addr]",<br>
> + [(store f128:$rd, ADDRrr:$addr)]>,<br>
> Requires<[HasV9, HasHardQuad]>;<br>
> def STQFri : F3_2<3, 0b100110,<br>
> - (outs), (ins MEMri:$addr, QFPRegs:$src),<br>
> - "stq $src, [$addr]",<br>
> - [(store f128:$src, ADDRri:$addr)]>,<br>
> + (outs), (ins MEMri:$addr, QFPRegs:$rd),<br>
> + "stq $rd, [$addr]",<br>
> + [(store f128:$rd, ADDRri:$addr)]>,<br>
> Requires<[HasV9, HasHardQuad]>;<br>
><br>
> // Section B.9 - SETHI Instruction, p. 104<br>
> def SETHIi: F2_1<0b100,<br>
> - (outs IntRegs:$dst), (ins i32imm:$src),<br>
> - "sethi $src, $dst",<br>
> - [(set i32:$dst, SETHIimm:$src)]>;<br>
> + (outs IntRegs:$rd), (ins i32imm:$imm22),<br>
> + "sethi $imm22, $rd",<br>
> + [(set i32:$rd, SETHIimm:$imm22)]>;<br>
><br>
> // Section B.10 - NOP Instruction, p. 105<br>
> // (It's a special case of SETHI)<br>
> @@ -505,12 +505,12 @@ let Defs = [ICC] in<br>
> defm ADDCC : F3_12<"addcc", 0b010000, addc>;<br>
><br>
> let Uses = [ICC], Defs = [ICC] in<br>
> - defm ADDX : F3_12<"addxcc", 0b001000, adde>;<br>
> + defm ADDX : F3_12<"addxcc", 0b011000, adde>;<br>
><br>
> // Section B.15 - Subtract Instructions, p. 110<br>
> defm SUB : F3_12 <"sub" , 0b000100, sub>;<br>
> let Uses = [ICC], Defs = [ICC] in<br>
> - defm SUBX : F3_12 <"subxcc" , 0b001100, sube>;<br>
> + defm SUBX : F3_12 <"subxcc" , 0b011100, sube>;<br>
><br>
> let Defs = [ICC] in<br>
> defm SUBCC : F3_12 <"subcc", 0b010100, subc>;<br>
><br>
> Added: llvm/trunk/lib/Target/Sparc/SparcJITInfo.cpp<br>
> URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcJITInfo.cpp?rev=192176&view=auto" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcJITInfo.cpp?rev=192176&view=auto</a><br>
> ==============================================================================<br>
> --- llvm/trunk/lib/Target/Sparc/SparcJITInfo.cpp (added)<br>
> +++ llvm/trunk/lib/Target/Sparc/SparcJITInfo.cpp Tue Oct 8 02:15:22 2013<br>
> @@ -0,0 +1,168 @@<br>
> +//===-- SparcJITInfo.cpp - Implement the Sparc JIT Interface --------------===//<br>
> +//<br>
> +// The LLVM Compiler Infrastructure<br>
> +//<br>
> +// This file is distributed under the University of Illinois Open Source<br>
> +// License. See LICENSE.TXT for details.<br>
> +//<br>
> +//===----------------------------------------------------------------------===//<br>
> +//<br>
> +// This file implements the JIT interfaces for the Sparc target.<br>
> +//<br>
> +//===----------------------------------------------------------------------===//<br>
> +#define DEBUG_TYPE "jit"<br>
> +#include "SparcJITInfo.h"<br>
> +#include "SparcRelocations.h"<br>
> +<br>
> +#include "llvm/CodeGen/JITCodeEmitter.h"<br>
> +#include "llvm/Support/Memory.h"<br>
> +<br>
> +using namespace llvm;<br>
> +<br>
> +/// JITCompilerFunction - This contains the address of the JIT function used to<br>
> +/// compile a function lazily.<br>
> +static TargetJITInfo::JITCompilerFn JITCompilerFunction;<br>
> +<br>
> +extern "C" void SparcCompilationCallback();<br>
> +<br>
> +extern "C" {<br>
> +#if defined (__sparc__)<br>
> + asm(<br>
> + ".text\n"<br>
> + "\t.align 4\n"<br>
> + "\t.global SparcCompilationCallback\n"<br>
> + "\t.type SparcCompilationCallback, #function\n"<br>
> + "SparcCompilationCallback:\n"<br>
> + // Save current register window.<br>
> + "\tsave %sp, -192, %sp\n"<br>
> + // stubaddr+4 is in %g1.<br>
> + "\tcall SparcCompilationCallbackC\n"<br>
> + "\t sub %g1, 4, %o0\n"<br>
> + // restore original register window and<br>
> + // copy %o0 to %g1<br>
> + "\t restore %o0, 0, %g1\n"<br>
> + // call the new stub<br>
> + "\tjmp %g1\n"<br>
> + "\t nop\n"<br>
> + "\t.size SparcCompilationCallback, .-SparcCompilationCallback"<br>
> + );<br>
> +<br>
> +#else<br>
> + void SparcCompilationCallback() {<br>
> + llvm_unreachable(<br>
> + "Cannot call SparcCompilationCallback() on a non-sparc arch!");<br>
> + }<br>
> +#endif<br>
> +}<br>
> +<br>
> +#define HI(Val) (((unsigned)(Val)) >> 10)<br>
> +#define LO(Val) (((unsigned)(Val)) & 0x3FF)<br>
> +<br>
> +#define SETHI_INST(imm, rd) (0x01000000 | ((rd) << 25) | ((imm) & 0x3FFFFF))<br>
> +#define JMP_INST(rs1, imm, rd) (0x80000000 | ((rd) << 25) | (0x38 << 19) \<br>
> + | ((rs1) << 14) | (1 << 13) | ((imm) & 0x1FFF))<br>
> +#define NOP_INST SETHI_INST(0, 0)<br>
> +<br>
> +extern "C" void *SparcCompilationCallbackC(intptr_t StubAddr) {<br>
> + // Get the address of the compiled code for this function.<br>
> + intptr_t NewVal = (intptr_t) JITCompilerFunction((void*) StubAddr);<br>
> +<br>
> + // Rewrite the function stub so that we don't end up here every time we<br>
> + // execute the call. We're replacing the first three instructions of the<br>
> + // stub with code that jumps to the compiled function:<br>
> + // sethi %hi(NewVal), %g1<br>
> + // jmp %g1+%lo(NewVal)<br>
> + // nop<br>
> +<br>
> + *(intptr_t *)(StubAddr) = SETHI_INST(HI(NewVal), 1);<br>
> + *(intptr_t *)(StubAddr + 4) = JMP_INST(1, LO(NewVal), 0);<br>
> + *(intptr_t *)(StubAddr + 8) = NOP_INST;<br>
> +<br>
> + sys::Memory::InvalidateInstructionCache((void*) StubAddr, 12);<br>
> + return (void*)StubAddr;<br>
> +}<br>
> +<br>
> +void SparcJITInfo::replaceMachineCodeForFunction(void *Old, void *New) {<br>
> + assert(0 && "FIXME: Implement SparcJITInfo::replaceMachineCodeForFunction");<br>
> +}<br>
> +<br>
> +<br>
> +TargetJITInfo::StubLayout SparcJITInfo::getStubLayout() {<br>
> + // The stub contains 3 4-byte instructions, aligned at 4 bytes. See<br>
> + // emitFunctionStub for details.<br>
> +<br>
> + StubLayout Result = { 3*4, 4 };<br>
> + return Result;<br>
> +}<br>
> +<br>
> +void *SparcJITInfo::emitFunctionStub(const Function *F, void *Fn,<br>
> + JITCodeEmitter &JCE)<br>
> +{<br>
> + JCE.emitAlignment(4);<br>
> + void *Addr = (void*) (JCE.getCurrentPCValue());<br>
> + if (!sys::Memory::setRangeWritable(Addr, 12))<br>
> + llvm_unreachable("ERROR: Unable to mark stub writable.");<br>
> +<br>
> + intptr_t EmittedAddr;<br>
> + if (Fn != (void*)(intptr_t)SparcCompilationCallback)<br>
> + EmittedAddr = (intptr_t)Fn;<br>
> + else<br>
> + EmittedAddr = (intptr_t)SparcCompilationCallback;<br>
> +<br>
> + // sethi %hi(EmittedAddr), %g1<br>
> + // jmp %g1+%lo(EmittedAddr), %g1<br>
> + // nop<br>
> +<br>
> + JCE.emitWordBE(SETHI_INST(HI(EmittedAddr), 1));<br>
> + JCE.emitWordBE(JMP_INST(1, LO(EmittedAddr), 1));<br>
> + JCE.emitWordBE(NOP_INST);<br>
> +<br>
> + sys::Memory::InvalidateInstructionCache(Addr, 12);<br>
> + if (!sys::Memory::setRangeExecutable(Addr, 12))<br>
> + llvm_unreachable("ERROR: Unable to mark stub executable.");<br>
> +<br>
> + return Addr;<br>
> +}<br>
> +<br>
> +TargetJITInfo::LazyResolverFn<br>
> +SparcJITInfo::getLazyResolverFunction(JITCompilerFn F) {<br>
> + JITCompilerFunction = F;<br>
> + return SparcCompilationCallback;<br>
> +}<br>
> +<br>
> +/// relocate - Before the JIT can run a block of code that has been emitted,<br>
> +/// it must rewrite the code to contain the actual addresses of any<br>
> +/// referenced global symbols.<br>
> +void SparcJITInfo::relocate(void *Function, MachineRelocation *MR,<br>
> + unsigned NumRelocs, unsigned char *GOTBase) {<br>
> + for (unsigned i = 0; i != NumRelocs; ++i, ++MR) {<br>
> + void *RelocPos = (char*) Function + MR->getMachineCodeOffset();<br>
> + intptr_t ResultPtr = (intptr_t) MR->getResultPointer();<br>
> +<br>
> + switch ((SP::RelocationType) MR->getRelocationType()) {<br>
> + default: llvm_unreachable("Unknown reloc!");<br>
> + case SP::reloc_sparc_hi:<br>
> + ResultPtr = (ResultPtr >> 10) & 0x3fffff;<br>
> + break;<br>
> +<br>
> + case SP::reloc_sparc_lo:<br>
> + ResultPtr = (ResultPtr & 0x3ff);<br>
> + break;<br>
> +<br>
> + case SP::reloc_sparc_pc30:<br>
> + ResultPtr = ((ResultPtr - (intptr_t)RelocPos) >> 2) & 0x3fffffff;<br>
> + break;<br>
> +<br>
> + case SP::reloc_sparc_pc22:<br>
> + ResultPtr = ((ResultPtr - (intptr_t)RelocPos) >> 2) & 0x3fffff;<br>
> + break;<br>
> +<br>
> + case SP::reloc_sparc_pc19:<br>
> + ResultPtr = ((ResultPtr - (intptr_t)RelocPos) >> 2) & 0x7ffff;<br>
> + break;<br>
> + }<br>
> + *((unsigned*) RelocPos) |= (unsigned) ResultPtr;<br>
> + }<br>
> +}<br>
> +<br>
> +<br>
><br>
> Added: llvm/trunk/lib/Target/Sparc/SparcJITInfo.h<br>
> URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcJITInfo.h?rev=192176&view=auto" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcJITInfo.h?rev=192176&view=auto</a><br>
> ==============================================================================<br>
> --- llvm/trunk/lib/Target/Sparc/SparcJITInfo.h (added)<br>
> +++ llvm/trunk/lib/Target/Sparc/SparcJITInfo.h Tue Oct 8 02:15:22 2013<br>
> @@ -0,0 +1,67 @@<br>
> +//==- SparcJITInfo.h - Sparc Implementation of the JIT Interface -*- C++ -*-==//<br>
> +//<br>
> +// The LLVM Compiler Infrastructure<br>
> +//<br>
> +// This file is distributed under the University of Illinois Open Source<br>
> +// License. See LICENSE.TXT for details.<br>
> +//<br>
> +//===----------------------------------------------------------------------===//<br>
> +//<br>
> +// This file contains the declaration of the SparcJITInfo class.<br>
> +//<br>
> +//===----------------------------------------------------------------------===//<br>
> +<br>
> +#ifndef SPARCJITINFO_H<br>
> +#define SPARCJITINFO_H<br>
> +<br>
> +#include "llvm/CodeGen/MachineConstantPool.h"<br>
> +#include "llvm/CodeGen/MachineFunction.h"<br>
> +#include "llvm/Target/TargetJITInfo.h"<br>
> +<br>
> +namespace llvm {<br>
> +class SparcTargetMachine;<br>
> +<br>
> +class SparcJITInfo : public TargetJITInfo {<br>
> +<br>
> + bool IsPIC;<br>
> +<br>
> + public:<br>
> + explicit SparcJITInfo()<br>
> + : IsPIC(false) {}<br>
> +<br>
> + /// replaceMachineCodeForFunction - Make it so that calling the function<br>
> + /// whose machine code is at OLD turns into a call to NEW, perhaps by<br>
> + /// overwriting OLD with a branch to NEW. This is used for self-modifying<br>
> + /// code.<br>
> + ///<br>
> + virtual void replaceMachineCodeForFunction(void *Old, void *New);<br>
> +<br>
> + // getStubLayout - Returns the size and alignment of the largest call stub<br>
> + // on Sparc.<br>
> + virtual StubLayout getStubLayout();<br>
> +<br>
> +<br>
> + /// emitFunctionStub - Use the specified JITCodeEmitter object to emit a<br>
> + /// small native function that simply calls the function at the specified<br>
> + /// address.<br>
> + virtual void *emitFunctionStub(const Function *F, void *Fn,<br>
> + JITCodeEmitter &JCE);<br>
> +<br>
> + /// getLazyResolverFunction - Expose the lazy resolver to the JIT.<br>
> + virtual LazyResolverFn getLazyResolverFunction(JITCompilerFn);<br>
> +<br>
> + /// relocate - Before the JIT can run a block of code that has been emitted,<br>
> + /// it must rewrite the code to contain the actual addresses of any<br>
> + /// referenced global symbols.<br>
> + virtual void relocate(void *Function, MachineRelocation *MR,<br>
> + unsigned NumRelocs, unsigned char *GOTBase);<br>
> +<br>
> + /// Initialize - Initialize internal stage for the function being JITted.<br>
> + void Initialize(const MachineFunction &MF, bool isPIC) {<br>
> + IsPIC = isPIC;<br>
> + }<br>
> +<br>
> +};<br>
> +}<br>
> +<br>
> +#endif<br>
><br>
> Added: llvm/trunk/lib/Target/Sparc/SparcRelocations.h<br>
> URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcRelocations.h?rev=192176&view=auto" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcRelocations.h?rev=192176&view=auto</a><br>
> ==============================================================================<br>
> --- llvm/trunk/lib/Target/Sparc/SparcRelocations.h (added)<br>
> +++ llvm/trunk/lib/Target/Sparc/SparcRelocations.h Tue Oct 8 02:15:22 2013<br>
> @@ -0,0 +1,41 @@<br>
> +//===-- SparcRelocations.h - Sparc Code Relocations -------------*- C++ -*-===//<br>
> +//<br>
> +// The LLVM Compiler Infrastructure<br>
> +//<br>
> +// This file is distributed under the University of Illinois Open Source<br>
> +// License. See LICENSE.TXT for details.<br>
> +//<br>
> +//===----------------------------------------------------------------------===//<br>
> +//<br>
> +// This file defines the Sparc target-specific relocation types<br>
> +// (for relocation-model=static).<br>
> +//<br>
> +//===----------------------------------------------------------------------===//<br>
> +<br>
> +#ifndef SPARC_RELOCATIONS_H<br>
> +#define SPARC_RELOCATIONS_H<br>
> +<br>
> +#include "llvm/CodeGen/MachineRelocation.h"<br>
> +<br>
> +namespace llvm {<br>
> + namespace SP {<br>
> + enum RelocationType {<br>
> + // reloc_sparc_hi - upper 22 bits<br>
> + reloc_sparc_hi = 1,<br>
> +<br>
> + // reloc_sparc_lo - lower 10 bits<br>
> + reloc_sparc_lo = 2,<br>
> +<br>
> + // reloc_sparc_pc30 - pc rel. 30 bits for call<br>
> + reloc_sparc_pc30 = 3,<br>
> +<br>
> + // reloc_sparc_pc22 - pc rel. 22 bits for branch<br>
> + reloc_sparc_pc22 = 4,<br>
> +<br>
> + // reloc_sparc_pc22 - pc rel. 19 bits for branch with icc/xcc<br>
> + reloc_sparc_pc19 = 5<br>
> + };<br>
> + }<br>
> +}<br>
> +<br>
> +#endif<br>
><br>
> Modified: llvm/trunk/lib/Target/Sparc/SparcTargetMachine.cpp<br>
> URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcTargetMachine.cpp?rev=192176&r1=192175&r2=192176&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcTargetMachine.cpp?rev=192176&r1=192175&r2=192176&view=diff</a><br>
> ==============================================================================<br>
> --- llvm/trunk/lib/Target/Sparc/SparcTargetMachine.cpp (original)<br>
> +++ llvm/trunk/lib/Target/Sparc/SparcTargetMachine.cpp Tue Oct 8 02:15:22 2013<br>
> @@ -65,6 +65,13 @@ bool SparcPassConfig::addInstSelector()<br>
> return false;<br>
> }<br>
><br>
> +bool SparcTargetMachine::addCodeEmitter(PassManagerBase &PM,<br>
> + JITCodeEmitter &JCE) {<br>
> + // Machine code emitter pass for Sparc.<br>
> + PM.add(createSparcJITCodeEmitterPass(*this, JCE));<br>
> + return false;<br>
> +}<br>
> +<br>
> /// addPreEmitPass - This pass may be implemented by targets that want to run<br>
> /// passes immediately before machine code is emitted. This should return<br>
> /// true if -print-machineinstrs should print out the code after the passes.<br>
><br>
> Modified: llvm/trunk/lib/Target/Sparc/SparcTargetMachine.h<br>
> URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcTargetMachine.h?rev=192176&r1=192175&r2=192176&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcTargetMachine.h?rev=192176&r1=192175&r2=192176&view=diff</a><br>
> ==============================================================================<br>
> --- llvm/trunk/lib/Target/Sparc/SparcTargetMachine.h (original)<br>
> +++ llvm/trunk/lib/Target/Sparc/SparcTargetMachine.h Tue Oct 8 02:15:22 2013<br>
> @@ -17,6 +17,7 @@<br>
> #include "SparcFrameLowering.h"<br>
> #include "SparcISelLowering.h"<br>
> #include "SparcInstrInfo.h"<br>
> +#include "SparcJITInfo.h"<br>
> #include "SparcSelectionDAGInfo.h"<br>
> #include "SparcSubtarget.h"<br>
> #include "llvm/IR/DataLayout.h"<br>
> @@ -32,6 +33,7 @@ class SparcTargetMachine : public LLVMTa<br>
> SparcTargetLowering TLInfo;<br>
> SparcSelectionDAGInfo TSInfo;<br>
> SparcFrameLowering FrameLowering;<br>
> + SparcJITInfo JITInfo;<br>
> public:<br>
> SparcTargetMachine(const Target &T, StringRef TT,<br>
> StringRef CPU, StringRef FS, const TargetOptions &Options,<br>
> @@ -52,10 +54,14 @@ public:<br>
> virtual const SparcSelectionDAGInfo* getSelectionDAGInfo() const {<br>
> return &TSInfo;<br>
> }<br>
> + virtual SparcJITInfo *getJITInfo() {<br>
> + return &JITInfo;<br>
> + }<br>
> virtual const DataLayout *getDataLayout() const { return &DL; }<br>
><br>
> // Pass Pipeline Configuration<br>
> virtual TargetPassConfig *createPassConfig(PassManagerBase &PM);<br>
> + virtual bool addCodeEmitter(PassManagerBase &PM, JITCodeEmitter &JCE);<br>
> };<br>
><br>
> /// SparcV8TargetMachine - Sparc 32-bit target machine<br>
><br>
> Modified: llvm/trunk/lib/Target/Sparc/TargetInfo/SparcTargetInfo.cpp<br>
> URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/TargetInfo/SparcTargetInfo.cpp?rev=192176&r1=192175&r2=192176&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/TargetInfo/SparcTargetInfo.cpp?rev=192176&r1=192175&r2=192176&view=diff</a><br>
> ==============================================================================<br>
> --- llvm/trunk/lib/Target/Sparc/TargetInfo/SparcTargetInfo.cpp (original)<br>
> +++ llvm/trunk/lib/Target/Sparc/TargetInfo/SparcTargetInfo.cpp Tue Oct 8 02:15:22 2013<br>
> @@ -15,7 +15,9 @@ using namespace llvm;<br>
> Target llvm::TheSparcTarget;<br>
> Target llvm::TheSparcV9Target;<br>
><br>
> -extern "C" void LLVMInitializeSparcTargetInfo() {<br>
> - RegisterTarget<Triple::sparc> X(TheSparcTarget, "sparc", "Sparc");<br>
> - RegisterTarget<Triple::sparcv9> Y(TheSparcV9Target, "sparcv9", "Sparc V9");<br>
> +extern "C" void LLVMInitializeSparcTargetInfo() {<br>
> + RegisterTarget<Triple::sparc, /*HasJIT=*/ true><br>
> + X(TheSparcTarget, "sparc", "Sparc");<br>
> + RegisterTarget<Triple::sparcv9, /*HasJIT=*/ true><br>
> + Y(TheSparcV9Target, "sparcv9", "Sparc V9");<br>
> }<br>
><br>
><br>
> _______________________________________________<br>
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> <a href="http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits" target="_blank">http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits</a><br>
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</div></div></blockquote></div><br></div></div></div>