<html><head><meta http-equiv="Content-Type" content="text/html charset=windows-1252"></head><body style="word-wrap: break-word; -webkit-nbsp-mode: space; -webkit-line-break: after-white-space;">Hi Andy,<div><br><div><div>On Oct 2, 2013, at 4:07 PM, Andrew Trick <<a href="mailto:atrick@apple.com">atrick@apple.com</a>> wrote:</div><br class="Apple-interchange-newline"><blockquote type="cite">Hi Quentin,<br><br>Just one thing.<br><br>The MC-level call to getSchedClassDesc can return a “variant” scheduling class. Trying to perform queries on it will probably assert. You can check SCDesc->isVariant() and bailout in that case.<br></blockquote><div>Thanks for the information.</div><div><br></div><div>Fixed in r<span style="font-family: Menlo; font-size: 11px;">191864.</span></div><br><blockquote type="cite"><br>Resolving the variant SchedClass requires an MI to pass to SubTargetInfo::resolveSchedClass.</blockquote><blockquote type="cite"><br>As you’re aware, the latencies aren’t necessarily useful without determining the consumer anyway. Tools that want more complete and useful information from the machine model will need to build an MI-level CFG. Hopefully, that will be lightweight once MI is extracted from CodeGen.<br></blockquote><div>I am looking forward for it!</div><div><br></div><div>Thanks again.</div><div><br></div><div>-Quentin</div><br><blockquote type="cite"><br>-Andy<br><br>On Oct 2, 2013, at 3:07 PM, Quentin Colombet <<a href="mailto:qcolombet@apple.com">qcolombet@apple.com</a>> wrote:<br><br><blockquote type="cite">Author: qcolombet<br>Date: Wed Oct 2 17:07:57 2013<br>New Revision: 191859<br><br>URL: <a href="http://llvm.org/viewvc/llvm-project?rev=191859&view=rev">http://llvm.org/viewvc/llvm-project?rev=191859&view=rev</a><br>Log:<br>[llvm-c][Disassembler] Add an option to print latency information in<br>disassembled output alongside the instructions.<br>E.g., on a vector shuffle operation with a memory operand, disassembled<br>outputs are:<br>* Without the option:<br> vpshufd $-0x79, (%rsp), %xmm0<br><br>* With the option:<br> vpshufd $-0x79, (%rsp), %xmm0 ## Latency: 5<br><br>The printed latency is extracted from the schedule model available in the<br>disassembler context. Thus, this option has no effect if there is not a<br>scheduling model for the target.<br>This boils down to one may need to specify the CPU string, so that this<br>option could have an effect.<br><br>Note: Latency < 2 are not printed.<br><br>This part of <<a href="rdar://problem/14687488">rdar://problem/14687488</a>>.<br><br>Modified:<br> llvm/trunk/include/llvm-c/Disassembler.h<br> llvm/trunk/lib/MC/MCDisassembler/Disassembler.cpp<br> llvm/trunk/lib/MC/MCDisassembler/Disassembler.h<br><br>Modified: llvm/trunk/include/llvm-c/Disassembler.h<br>URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm-c/Disassembler.h?rev=191859&r1=191858&r2=191859&view=diff">http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm-c/Disassembler.h?rev=191859&r1=191858&r2=191859&view=diff</a><br>==============================================================================<br>--- llvm/trunk/include/llvm-c/Disassembler.h (original)<br>+++ llvm/trunk/include/llvm-c/Disassembler.h Wed Oct 2 17:07:57 2013<br>@@ -172,6 +172,8 @@ int LLVMSetDisasmOptions(LLVMDisasmConte<br>#define LLVMDisassembler_Option_AsmPrinterVariant 4<br>/* The option to set comment on instructions */<br>#define LLVMDisassembler_Option_SetInstrComments 8<br>+ /* The option to print latency information alongside instructions */<br>+#define LLVMDisassembler_Option_PrintLatency 16<br><br>/**<br> * Dispose of a disassembler context.<br><br>Modified: llvm/trunk/lib/MC/MCDisassembler/Disassembler.cpp<br>URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCDisassembler/Disassembler.cpp?rev=191859&r1=191858&r2=191859&view=diff">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCDisassembler/Disassembler.cpp?rev=191859&r1=191858&r2=191859&view=diff</a><br>==============================================================================<br>--- llvm/trunk/lib/MC/MCDisassembler/Disassembler.cpp (original)<br>+++ llvm/trunk/lib/MC/MCDisassembler/Disassembler.cpp Wed Oct 2 17:07:57 2013<br>@@ -174,6 +174,52 @@ static void emitComments(LLVMDisasmConte<br> DC->CommentStream.resync();<br>}<br><br>+/// \brief Gets latency information for \p Inst, based on \p DC information.<br>+/// \return The maximum expected latency over all the definitions or -1<br>+/// if no information are available.<br>+static int getLatency(LLVMDisasmContext *DC, const MCInst &Inst) {<br>+ // Try to compute scheduling information.<br>+ const MCSubtargetInfo *STI = DC->getSubtargetInfo();<br>+ const MCSchedModel *SCModel = STI->getSchedModel();<br>+ const int NoInformationAvailable = -1;<br>+<br>+ // Check if we have a scheduling model for instructions.<br>+ if (!SCModel || !SCModel->hasInstrSchedModel())<br>+ return NoInformationAvailable;<br>+<br>+ // Get the scheduling class of the requested instruction.<br>+ const MCInstrDesc& Desc = DC->getInstrInfo()->get(Inst.getOpcode());<br>+ unsigned SCClass = Desc.getSchedClass();<br>+ const MCSchedClassDesc *SCDesc = SCModel->getSchedClassDesc(SCClass);<br>+ if (!SCDesc || !SCDesc->isValid())<br>+ return NoInformationAvailable;<br>+<br>+ // Compute output latency.<br>+ int Latency = 0;<br>+ for (unsigned DefIdx = 0, DefEnd = SCDesc->NumWriteLatencyEntries;<br>+ DefIdx != DefEnd; ++DefIdx) {<br>+ // Lookup the definition's write latency in SubtargetInfo.<br>+ const MCWriteLatencyEntry *WLEntry = STI->getWriteLatencyEntry(SCDesc,<br>+ DefIdx);<br>+ Latency = std::max(Latency, WLEntry->Cycles);<br>+ }<br>+<br>+ return Latency;<br>+}<br>+<br>+<br>+/// \brief Emits latency information in DC->CommentStream for \p Inst, based<br>+/// on the information available in \p DC.<br>+static void emitLatency(LLVMDisasmContext *DC, const MCInst &Inst) {<br>+ int Latency = getLatency(DC, Inst);<br>+<br>+ // Report only interesting latency.<br>+ if (Latency < 2)<br>+ return;<br>+<br>+ DC->CommentStream << "Latency: " << Latency << '\n';<br>+}<br>+<br>//<br>// LLVMDisasmInstruction() disassembles a single instruction using the<br>// disassembler context specified in the parameter DC. The bytes of the<br>@@ -217,6 +263,9 @@ size_t LLVMDisasmInstruction(LLVMDisasmC<br> formatted_raw_ostream FormattedOS(OS);<br> IP->printInst(&Inst, FormattedOS, AnnotationsStr);<br><br>+ if (DC->getOptions() & LLVMDisassembler_Option_PrintLatency)<br>+ emitLatency(DC, Inst);<br>+<br> emitComments(DC, FormattedOS);<br><br> assert(OutStringSize != 0 && "Output buffer cannot be zero size");<br>@@ -239,12 +288,14 @@ int LLVMSetDisasmOptions(LLVMDisasmConte<br> LLVMDisasmContext *DC = (LLVMDisasmContext *)DCR;<br> MCInstPrinter *IP = DC->getIP();<br> IP->setUseMarkup(1);<br>+ DC->addOptions(LLVMDisassembler_Option_UseMarkup);<br> Options &= ~LLVMDisassembler_Option_UseMarkup;<br> }<br> if (Options & LLVMDisassembler_Option_PrintImmHex){<br> LLVMDisasmContext *DC = (LLVMDisasmContext *)DCR;<br> MCInstPrinter *IP = DC->getIP();<br> IP->setPrintImmHex(1);<br>+ DC->addOptions(LLVMDisassembler_Option_PrintImmHex);<br> Options &= ~LLVMDisassembler_Option_PrintImmHex;<br> }<br> if (Options & LLVMDisassembler_Option_AsmPrinterVariant){<br>@@ -260,6 +311,7 @@ int LLVMSetDisasmOptions(LLVMDisasmConte<br> AsmPrinterVariant, *MAI, *MII, *MRI, *STI);<br> if (IP) {<br> DC->setIP(IP);<br>+ DC->addOptions(LLVMDisassembler_Option_AsmPrinterVariant);<br> Options &= ~LLVMDisassembler_Option_AsmPrinterVariant;<br> }<br> }<br>@@ -267,7 +319,13 @@ int LLVMSetDisasmOptions(LLVMDisasmConte<br> LLVMDisasmContext *DC = (LLVMDisasmContext *)DCR;<br> MCInstPrinter *IP = DC->getIP();<br> IP->setCommentStream(DC->CommentStream);<br>+ DC->addOptions(LLVMDisassembler_Option_SetInstrComments);<br> Options &= ~LLVMDisassembler_Option_SetInstrComments;<br> }<br>+ if (Options & LLVMDisassembler_Option_PrintLatency) {<br>+ LLVMDisasmContext *DC = (LLVMDisasmContext *)DCR;<br>+ DC->addOptions(LLVMDisassembler_Option_PrintLatency);<br>+ Options &= ~LLVMDisassembler_Option_PrintLatency;<br>+ }<br> return (Options == 0);<br>}<br><br>Modified: llvm/trunk/lib/MC/MCDisassembler/Disassembler.h<br>URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCDisassembler/Disassembler.h?rev=191859&r1=191858&r2=191859&view=diff">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCDisassembler/Disassembler.h?rev=191859&r1=191858&r2=191859&view=diff</a><br>==============================================================================<br>--- llvm/trunk/lib/MC/MCDisassembler/Disassembler.h (original)<br>+++ llvm/trunk/lib/MC/MCDisassembler/Disassembler.h Wed Oct 2 17:07:57 2013<br>@@ -73,6 +73,8 @@ private:<br> llvm::OwningPtr<const llvm::MCDisassembler> DisAsm;<br> // The instruction printer for the target architecture.<br> llvm::OwningPtr<llvm::MCInstPrinter> IP;<br>+ // The options used to set up the disassembler.<br>+ uint64_t Options;<br><br>public:<br> // Comment stream and backing vector.<br>@@ -90,6 +92,7 @@ public:<br> MCInstPrinter *iP) : TripleName(tripleName),<br> DisInfo(disInfo), TagType(tagType), GetOpInfo(getOpInfo),<br> SymbolLookUp(symbolLookUp), TheTarget(theTarget),<br>+ Options(0),<br> CommentStream(CommentsToEmit) {<br> MAI.reset(mAI);<br> MRI.reset(mRI);<br>@@ -114,6 +117,8 @@ public:<br> const MCSubtargetInfo *getSubtargetInfo() const { return MSI.get(); }<br> MCInstPrinter *getIP() { return IP.get(); }<br> void setIP(MCInstPrinter *NewIP) { IP.reset(NewIP); }<br>+ uint64_t getOptions() const { return Options; }<br>+ void addOptions(uint64_t Options) { this->Options |= Options; }<br>};<br><br>} // namespace llvm<br><br><br>_______________________________________________<br>llvm-commits mailing list<br><a href="mailto:llvm-commits@cs.uiuc.edu">llvm-commits@cs.uiuc.edu</a><br>http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits<br></blockquote><br></blockquote></div><br></div></body></html>