<html><head><meta http-equiv="Content-Type" content="text/html charset=us-ascii"></head><body style="word-wrap: break-word; -webkit-nbsp-mode: space; -webkit-line-break: after-white-space;">Hi Tilmann,<div><br></div><div>Would it be difficult to turn greps into FileCheck patterns?</div><div><br></div><div>I think it would also help to figure out which instruction is causing which error.</div><div><br></div><div>Thanks,<br><div apple-content-edited="true">
<div style="color: rgb(0, 0, 0); font-family: Helvetica; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; orphans: 2; text-align: -webkit-auto; text-indent: 0px; text-transform: none; white-space: normal; widows: 2; word-spacing: 0px; -webkit-text-size-adjust: auto; -webkit-text-stroke-width: 0px; word-wrap: break-word; -webkit-nbsp-mode: space; -webkit-line-break: after-white-space; ">-Quentin</div>
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<br><div><div>On Sep 30, 2013, at 9:11 AM, Tilmann Scheller <<a href="mailto:tilmann.scheller@googlemail.com">tilmann.scheller@googlemail.com</a>> wrote:</div><br class="Apple-interchange-newline"><blockquote type="cite">Author: tilmann<br>Date: Mon Sep 30 11:11:48 2013<br>New Revision: 191678<br><br>URL: <a href="http://llvm.org/viewvc/llvm-project?rev=191678&view=rev">http://llvm.org/viewvc/llvm-project?rev=191678&view=rev</a><br>Log:<br>[ARM] Assembler: ARM LDRD with writeback requires the base register to be different from the destination registers.<br><br>See ARM ARM A8.8.72.<br><br>Violating this constraint results in unpredictable behavior.<br><br><br>Modified:<br> llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp<br> llvm/trunk/test/MC/ARM/arm-ldrd.s<br><br>Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp<br>URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=191678&r1=191677&r2=191678&view=diff">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=191678&r1=191677&r2=191678&view=diff</a><br>==============================================================================<br>--- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original)<br>+++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Mon Sep 30 11:11:48 2013<br>@@ -5343,25 +5343,40 @@ validateInstruction(MCInst &Inst,<br> Inst.getOpcode() != ARM::t2Bcc)<br> return Error(Loc, "predicated instructions must be in IT block");<br><br>- switch (Inst.getOpcode()) {<br>+ const unsigned Opcode = Inst.getOpcode();<br>+ switch (Opcode) {<br> case ARM::LDRD:<br> case ARM::LDRD_PRE:<br> case ARM::LDRD_POST: {<br>- unsigned RtReg = Inst.getOperand(0).getReg();<br>+ const unsigned RtReg = Inst.getOperand(0).getReg();<br>+<br> // Rt can't be R14.<br> if (RtReg == ARM::LR)<br> return Error(Operands[3]->getStartLoc(),<br> "Rt can't be R14");<br>- unsigned Rt = MRI->getEncodingValue(RtReg);<br>+<br>+ const unsigned Rt = MRI->getEncodingValue(RtReg);<br> // Rt must be even-numbered.<br> if ((Rt & 1) == 1)<br> return Error(Operands[3]->getStartLoc(),<br> "Rt must be even-numbered");<br>+<br> // Rt2 must be Rt + 1.<br>- unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(1).getReg());<br>+ const unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(1).getReg());<br> if (Rt2 != Rt + 1)<br> return Error(Operands[3]->getStartLoc(),<br> "destination operands must be sequential");<br>+<br>+ if (Opcode == ARM::LDRD_PRE || Opcode == ARM::LDRD_POST) {<br>+ const unsigned Rn = MRI->getEncodingValue(Inst.getOperand(3).getReg());<br>+ // For addressing modes with writeback, the base register needs to be<br>+ // different from the destination registers.<br>+ if (Rn == Rt || Rn == Rt2)<br>+ return Error(Operands[3]->getStartLoc(),<br>+ "base register needs to be different from destination "<br>+ "registers");<br>+ }<br>+<br> return false;<br> }<br> case ARM::t2LDRDi8:<br><br>Modified: llvm/trunk/test/MC/ARM/arm-ldrd.s<br>URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/arm-ldrd.s?rev=191678&r1=191677&r2=191678&view=diff">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/arm-ldrd.s?rev=191678&r1=191677&r2=191678&view=diff</a><br>==============================================================================<br>--- llvm/trunk/test/MC/ARM/arm-ldrd.s (original)<br>+++ llvm/trunk/test/MC/ARM/arm-ldrd.s Mon Sep 30 11:11:48 2013<br>@@ -3,6 +3,7 @@<br> // RUN: grep "error: Rt must be even-numbered" %t | count 7<br> // RUN: grep "error: Rt can't be R14" %t | count 7<br> // RUN: grep "error: destination operands must be sequential" %t | count 7<br>+// RUN: grep "error: base register needs to be different from destination registers" %t | count 4<br> // <a href="rdar://14479793">rdar://14479793</a><br><br> ldrd r1, r2, [pc, #0]<br>@@ -26,3 +27,8 @@ ldrd r0, r3, [r4, r5]<br> ldrd r1, r2, [r3], r4<br> ldrd lr, pc, [r3], r4<br> ldrd r0, r3, [r4], r5<br>+<br>+ldrd r0, r1, [r0], #4<br>+ldrd r0, r1, [r1], #4<br>+ldrd r0, r1, [r0, #4]!<br>+ldrd r0, r1, [r1, #4]!<br><br><br>_______________________________________________<br>llvm-commits mailing list<br><a href="mailto:llvm-commits@cs.uiuc.edu">llvm-commits@cs.uiuc.edu</a><br>http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits<br></blockquote></div><br></div></body></html>