<html><head><meta http-equiv="Content-Type" content="text/html charset=windows-1252"></head><body style="word-wrap: break-word; -webkit-nbsp-mode: space; -webkit-line-break: after-white-space;">Fixed in 191691.<div><br></div><div>Regards,</div><div><br></div><div>Tilmann</div><div><br><div><div>On Sep 30, 2013, at 8:33 PM, Tilmann Scheller <<a href="mailto:tscheller@apple.com">tscheller@apple.com</a>> wrote:</div><br class="Apple-interchange-newline"><blockquote type="cite"><div style="font-family: Helvetica; font-size: 12px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; orphans: auto; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; widows: auto; word-spacing: 0px; -webkit-text-stroke-width: 0px; word-wrap: break-word; -webkit-nbsp-mode: space; -webkit-line-break: after-white-space;">Looks like I unintentionally broke “make check” with this formatting changes, I’m working on a fix.<div><br></div><div>Regards</div><div><br></div><div>Tilmann</div><div><br><div><div>On Sep 30, 2013, at 7:57 PM, Tilmann Scheller <<a href="mailto:tilmann.scheller@googlemail.com">tilmann.scheller@googlemail.com</a>> wrote:</div><br class="Apple-interchange-newline"><blockquote type="cite"><div style="font-size: 12px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; orphans: auto; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; widows: auto; word-spacing: 0px; -webkit-text-stroke-width: 0px;">Author: tilmann<br>Date: Mon Sep 30 12:57:30 2013<br>New Revision: 191686<br><br>URL:<span class="Apple-converted-space"> </span><a href="http://llvm.org/viewvc/llvm-project?rev=191686&view=rev">http://llvm.org/viewvc/llvm-project?rev=191686&view=rev</a><br>Log:<br>[ARM] Clean up ARMAsmParser::validateInstruction().<br><br>Fix some LLVM Coding Standards violations.<br><br>No changes in functionality.<br><br>Modified:<br> llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp<br><br>Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp<br>URL:<span class="Apple-converted-space"> </span><a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=191686&r1=191685&r2=191686&view=diff">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=191686&r1=191685&r2=191686&view=diff</a><br>==============================================================================<br>--- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original)<br>+++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Mon Sep 30 12:57:30 2013<br>@@ -5311,26 +5311,25 @@ validateInstruction(MCInst &Inst,<br><br> // Check the IT block state first.<br> // NOTE: BKPT and HLT instructions have the interesting property of being<br>- // allowed in IT blocks, but not being predicable. They just always<br>- // execute.<br>+ // allowed in IT blocks, but not being predicable. They just always execute.<br> if (inITBlock() && !instIsBreakpoint(Inst)) {<br>- unsigned bit = 1;<br>+ unsigned Bit = 1;<br> if (ITState.FirstCond)<br> ITState.FirstCond = false;<br> else<br>- bit = (ITState.Mask >> (5 - ITState.CurPosition)) & 1;<br>+ Bit = (ITState.Mask >> (5 - ITState.CurPosition)) & 1;<br> // The instruction must be predicable.<br> if (!MCID.isPredicable())<br> return Error(Loc, "instructions in IT block must be predicable");<br> unsigned Cond = Inst.getOperand(MCID.findFirstPredOperandIdx()).getImm();<br>- unsigned ITCond = bit ? ITState.Cond :<br>+ unsigned ITCond = Bit ? ITState.Cond :<br> ARMCC::getOppositeCondition(ITState.Cond);<br> if (Cond != ITCond) {<br> // Find the condition code Operand to get its SMLoc information.<br> SMLoc CondLoc;<br>- for (unsigned i = 1; i < Operands.size(); ++i)<br>- if (static_cast<ARMOperand*>(Operands[i])->isCondCode())<br>- CondLoc = Operands[i]->getStartLoc();<br>+ for (unsigned I = 1; I < Operands.size(); ++I)<br>+ if (static_cast<ARMOperand*>(Operands[I])->isCondCode())<br>+ CondLoc = Operands[I]->getStartLoc();<br> return Error(CondLoc, "incorrect condition in IT block; got '" +<br> StringRef(ARMCondCodeToString(ARMCC::CondCodes(Cond))) +<br> "', but expected '" +<br>@@ -5411,37 +5410,36 @@ validateInstruction(MCInst &Inst,<br> }<br> case ARM::SBFX:<br> case ARM::UBFX: {<br>- // width must be in range [1, 32-lsb]<br>- unsigned lsb = Inst.getOperand(2).getImm();<br>- unsigned widthm1 = Inst.getOperand(3).getImm();<br>- if (widthm1 >= 32 - lsb)<br>+ // Width must be in range [1, 32-lsb].<br>+ unsigned LSB = Inst.getOperand(2).getImm();<br>+ unsigned Widthm1 = Inst.getOperand(3).getImm();<br>+ if (Widthm1 >= 32 - LSB)<br> return Error(Operands[5]->getStartLoc(),<br> "bitfield width must be in range [1,32-lsb]");<br> return false;<br> }<br> case ARM::tLDMIA: {<br> // If we're parsing Thumb2, the .w variant is available and handles<br>- // most cases that are normally illegal for a Thumb1 LDM<br>- // instruction. We'll make the transformation in processInstruction()<br>- // if necessary.<br>+ // most cases that are normally illegal for a Thumb1 LDM instruction.<br>+ // We'll make the transformation in processInstruction() if necessary.<br> //<br> // Thumb LDM instructions are writeback iff the base register is not<br> // in the register list.<br> unsigned Rn = Inst.getOperand(0).getReg();<br>- bool hasWritebackToken =<br>+ bool HasWritebackToken =<br> (static_cast<ARMOperand*>(Operands[3])->isToken() &&<br> static_cast<ARMOperand*>(Operands[3])->getToken() == "!");<br>- bool listContainsBase;<br>- if (checkLowRegisterList(Inst, 3, Rn, 0, listContainsBase) && !isThumbTwo())<br>- return Error(Operands[3 + hasWritebackToken]->getStartLoc(),<br>+ bool ListContainsBase;<br>+ if (checkLowRegisterList(Inst, 3, Rn, 0, ListContainsBase) && !isThumbTwo())<br>+ return Error(Operands[3 + HasWritebackToken]->getStartLoc(),<br> "registers must be in range r0-r7");<br> // If we should have writeback, then there should be a '!' token.<br>- if (!listContainsBase && !hasWritebackToken && !isThumbTwo())<br>+ if (!ListContainsBase && !HasWritebackToken && !isThumbTwo())<br> return Error(Operands[2]->getStartLoc(),<br> "writeback operator '!' expected");<br> // If we should not have writeback, there must not be a '!'. This is<br> // true even for the 32-bit wide encodings.<br>- if (listContainsBase && hasWritebackToken)<br>+ if (ListContainsBase && HasWritebackToken)<br> return Error(Operands[3]->getStartLoc(),<br> "writeback operator '!' not allowed when base register "<br> "in register list");<br>@@ -5478,24 +5476,24 @@ validateInstruction(MCInst &Inst,<br> // so only issue a diagnostic for thumb1. The instructions will be<br> // switched to the t2 encodings in processInstruction() if necessary.<br> case ARM::tPOP: {<br>- bool listContainsBase;<br>- if (checkLowRegisterList(Inst, 2, 0, ARM::PC, listContainsBase) &&<br>+ bool ListContainsBase;<br>+ if (checkLowRegisterList(Inst, 2, 0, ARM::PC, ListContainsBase) &&<br> !isThumbTwo())<br> return Error(Operands[2]->getStartLoc(),<br> "registers must be in range r0-r7 or pc");<br> break;<br> }<br> case ARM::tPUSH: {<br>- bool listContainsBase;<br>- if (checkLowRegisterList(Inst, 2, 0, ARM::LR, listContainsBase) &&<br>+ bool ListContainsBase;<br>+ if (checkLowRegisterList(Inst, 2, 0, ARM::LR, ListContainsBase) &&<br> !isThumbTwo())<br> return Error(Operands[2]->getStartLoc(),<br> "registers must be in range r0-r7 or lr");<br> break;<br> }<br> case ARM::tSTMIA_UPD: {<br>- bool listContainsBase;<br>- if (checkLowRegisterList(Inst, 4, 0, 0, listContainsBase) && !isThumbTwo())<br>+ bool ListContainsBase;<br>+ if (checkLowRegisterList(Inst, 4, 0, 0, ListContainsBase) && !isThumbTwo())<br> return Error(Operands[4]->getStartLoc(),<br> "registers must be in range r0-r7");<br> break;<br>@@ -5510,26 +5508,26 @@ validateInstruction(MCInst &Inst,<br> }<br> break;<br> }<br>- // final range checking for Thumb unconditional branch instructions<br>+ // Final range checking for Thumb unconditional branch instructions.<br> case ARM::tB:<br>- if(!(static_cast<ARMOperand*>(Operands[2]))->isSignedOffset<11, 1>())<br>- return Error(Operands[2]->getStartLoc(), "Branch target out of range");<br>+ if (!(static_cast<ARMOperand*>(Operands[2]))->isSignedOffset<11, 1>())<br>+ return Error(Operands[2]->getStartLoc(), "branch target out of range");<br> break;<br> case ARM::t2B: {<br> int op = (Operands[2]->isImm()) ? 2 : 3;<br>- if(!(static_cast<ARMOperand*>(Operands[op]))->isSignedOffset<24, 1>())<br>- return Error(Operands[op]->getStartLoc(), "Branch target out of range");<br>+ if (!(static_cast<ARMOperand*>(Operands[op]))->isSignedOffset<24, 1>())<br>+ return Error(Operands[op]->getStartLoc(), "branch target out of range");<br> break;<br> }<br>- // final range checking for Thumb conditional branch instructions<br>+ // Final range checking for Thumb conditional branch instructions.<br> case ARM::tBcc:<br>- if(!(static_cast<ARMOperand*>(Operands[2]))->isSignedOffset<8, 1>())<br>- return Error(Operands[2]->getStartLoc(), "Branch target out of range");<br>+ if (!(static_cast<ARMOperand*>(Operands[2]))->isSignedOffset<8, 1>())<br>+ return Error(Operands[2]->getStartLoc(), "branch target out of range");<br> break;<br> case ARM::t2Bcc: {<br>- int op = (Operands[2]->isImm()) ? 2 : 3;<br>- if(!(static_cast<ARMOperand*>(Operands[op]))->isSignedOffset<20, 1>())<br>- return Error(Operands[op]->getStartLoc(), "Branch target out of range");<br>+ int Op = (Operands[2]->isImm()) ? 2 : 3;<br>+ if (!(static_cast<ARMOperand*>(Operands[Op]))->isSignedOffset<20, 1>())<br>+ return Error(Operands[Op]->getStartLoc(), "branch target out of range");<br> break;<br> }<br> }<br><br><br>_______________________________________________<br>llvm-commits mailing list<br><a href="mailto:llvm-commits@cs.uiuc.edu">llvm-commits@cs.uiuc.edu</a><br><a href="http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits">http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits</a></div></blockquote></div><br></div>_______________________________________________<br>llvm-commits mailing list<br><a href="mailto:llvm-commits@cs.uiuc.edu">llvm-commits@cs.uiuc.edu</a><br><a href="http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits">http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits</a></div></blockquote></div><br></div></body></html>