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<div style="direction: ltr;font-family: Tahoma;color: #000000;font-size: 10pt;">Committed revision 191415.<br>
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<div style="direction: ltr;" id="divRpF322375"><font size="2" color="#000000" face="Tahoma"><b>From:</b> Matheus Almeida<br>
<b>Sent:</b> Wednesday, September 25, 2013 4:52 AM<br>
<b>To:</b> llvm-commits@cs.uiuc.edu<br>
<b>Cc:</b> Jack Carter<br>
<b>Subject:</b> [PATCH][Mips][msa] Direct Object Emission for the MSA instruction set - Initial support<br>
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<p class="MsoNormal">In more detail, this patch adds the ability to parse, encode</p>
<p class="MsoNormal">and decode MSA registers ($w0-$w31). The format of 2RF instructions</p>
<p class="MsoNormal">(MipsMSAInstrFormat.td) was updated so that we could attach a test case to</p>
<p class="MsoNormal">this patch i.e., the test case parses, encodes and decodes 2 MSA</p>
<p class="MsoNormal">instructions. Following patches will add the remainder of the instructions.</p>
<p class="MsoNormal"> </p>
<p class="MsoNormal">Note that DecodeMSA128BRegisterClass is missing from MipsDisassembler.td because it's not yet</p>
<p class="MsoNormal">required at this stage and having it would cause a compiler warning (unused function).</p>
<p class="MsoNormal"> </p>
<p class="MsoNormal" style="text-align:justify"><b><span style="font-size:12.0pt; font-family:"Arial","sans-serif"" lang="PT">Matheus Almeida</span></b></p>
<p class="MsoNormal" style="text-align:justify"><span style="font-size:10.0pt; font-family:"Arial","sans-serif"" lang="PT">MIPS processor IP</span></p>
<p class="MsoNormal" style="text-align:justify"><a href="http://www.imgtec.com/" target="_blank"><span style="font-size:10.0pt; font-family:"Arial","sans-serif"; color:blue">www.imgtec.com</span></a><span style="font-size:10.0pt; font-family:"Arial","sans-serif""></span></p>
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