<div dir="ltr">On Wed, Sep 25, 2013 at 9:48 PM, Hal Finkel <span dir="ltr"><<a href="mailto:hfinkel@anl.gov" target="_blank">hfinkel@anl.gov</a>></span> wrote:<br><div class="gmail_extra"><div class="gmail_quote"><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left-width:1px;border-left-color:rgb(204,204,204);border-left-style:solid;padding-left:1ex">
<div class=""><div class="h5">----- Original Message -----<br>
> Author: majnemer<br>
> Date: Wed Sep 25 23:11:24 2013<br>
> New Revision: 191419<br>
><br>
> URL: <a href="http://llvm.org/viewvc/llvm-project?rev=191419&view=rev" target="_blank">http://llvm.org/viewvc/llvm-project?rev=191419&view=rev</a><br>
> Log:<br>
> PPC: Add support for fctid and fctiw<br>
><br>
> Encodings were checked against the Power ISA documents and double<br>
> checked against binutils.<br>
><br>
> This fixes PR17350.<br>
><br>
> Modified:<br>
> llvm/trunk/lib/Target/PowerPC/PPCISelLowering.h<br>
> llvm/trunk/lib/Target/PowerPC/PPCInstr64Bit.td<br>
> llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td<br>
> llvm/trunk/test/MC/PowerPC/ppc64-encoding-fp.s<br>
><br>
> Modified: llvm/trunk/lib/Target/PowerPC/PPCISelLowering.h<br>
> URL:<br>
> <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCISelLowering.h?rev=191419&r1=191418&r2=191419&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCISelLowering.h?rev=191419&r1=191418&r2=191419&view=diff</a><br>
> ==============================================================================<br>
> --- llvm/trunk/lib/Target/PowerPC/PPCISelLowering.h (original)<br>
> +++ llvm/trunk/lib/Target/PowerPC/PPCISelLowering.h Wed Sep 25<br>
> 23:11:24 2013<br>
> @@ -42,10 +42,10 @@ namespace llvm {<br>
> /// unsigned integers and single-precision outputs.<br>
> FCFIDU, FCFIDS, FCFIDUS,<br>
><br>
> - /// FCTI[D,W]Z - The FCTIDZ and FCTIWZ instructions, taking an<br>
> f32 or f64<br>
> - /// operand, producing an f64 value containing the integer<br>
> representation<br>
> - /// of that FP value.<br>
> - FCTIDZ, FCTIWZ,<br>
> + /// FCTI[D,W]Z? - The FCTID, FCTIDZ, FCTIW and FCTIWZ<br>
> instructions,<br>
> + /// taking an f32 or f64 operand, producing an f64 value<br>
> containing the<br>
> + /// integer representation of that FP value.<br>
> + FCTID, FCTIDZ, FCTIW, FCTIWZ,<br>
<br>
</div></div>Why did you add these ISD nodes and the associated TableGen patterns? Is there a follow-up commit coming with associated code generation support? If not, then you only need the instruction definitions to get assembler support (and we should remove the ISD nodes unless and until we need them).<br>
</blockquote><div><br></div><div>No reason outside of consistency, removed in r191421.</div><div> </div><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left-width:1px;border-left-color:rgb(204,204,204);border-left-style:solid;padding-left:1ex">
<br>
Thanks,<br>
Hal<br>
<div class=""><div class="h5"><br>
><br>
> /// Newer FCTI[D,W]UZ floating-point-to-integer conversion<br>
> instructions for<br>
> /// unsigned integers.<br>
><br>
> Modified: llvm/trunk/lib/Target/PowerPC/PPCInstr64Bit.td<br>
> URL:<br>
> <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCInstr64Bit.td?rev=191419&r1=191418&r2=191419&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCInstr64Bit.td?rev=191419&r1=191418&r2=191419&view=diff</a><br>
> ==============================================================================<br>
> --- llvm/trunk/lib/Target/PowerPC/PPCInstr64Bit.td (original)<br>
> +++ llvm/trunk/lib/Target/PowerPC/PPCInstr64Bit.td Wed Sep 25<br>
> 23:11:24 2013<br>
> @@ -968,6 +968,9 @@ let PPC970_Unit = 3, neverHasSideEffects<br>
> defm FCFID : XForm_26r<63, 846, (outs f8rc:$frD), (ins f8rc:$frB),<br>
> "fcfid", "$frD, $frB", FPGeneral,<br>
> [(set f64:$frD, (PPCfcfid f64:$frB))]>,<br>
> isPPC64;<br>
> +defm FCTID : XForm_26r<63, 814, (outs f8rc:$frD), (ins f8rc:$frB),<br>
> + "fctid", "$frD, $frB", FPGeneral,<br>
> + [(set f64:$frD, (PPCfctid f64:$frB))]>,<br>
> isPPC64;<br>
> defm FCTIDZ : XForm_26r<63, 815, (outs f8rc:$frD), (ins f8rc:$frB),<br>
> "fctidz", "$frD, $frB", FPGeneral,<br>
> [(set f64:$frD, (PPCfctidz f64:$frB))]>,<br>
> isPPC64;<br>
><br>
> Modified: llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td<br>
> URL:<br>
> <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td?rev=191419&r1=191418&r2=191419&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td?rev=191419&r1=191418&r2=191419&view=diff</a><br>
> ==============================================================================<br>
> --- llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td (original)<br>
> +++ llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td Wed Sep 25 23:11:24<br>
> 2013<br>
> @@ -69,7 +69,9 @@ def PPCfcfid : SDNode<"PPCISD::FCFID",<br>
> def PPCfcfidu : SDNode<"PPCISD::FCFIDU", SDTFPUnaryOp, []>;<br>
> def PPCfcfids : SDNode<"PPCISD::FCFIDS", SDTFPRoundOp, []>;<br>
> def PPCfcfidus: SDNode<"PPCISD::FCFIDUS", SDTFPRoundOp, []>;<br>
> +def PPCfctid : SDNode<"PPCISD::FCTID", SDTFPUnaryOp, []>;<br>
> def PPCfctidz : SDNode<"PPCISD::FCTIDZ", SDTFPUnaryOp, []>;<br>
> +def PPCfctiw : SDNode<"PPCISD::FCTIW", SDTFPUnaryOp, []>;<br>
> def PPCfctiwz : SDNode<"PPCISD::FCTIWZ", SDTFPUnaryOp, []>;<br>
> def PPCfctiduz: SDNode<"PPCISD::FCTIDUZ",SDTFPUnaryOp, []>;<br>
> def PPCfctiwuz: SDNode<"PPCISD::FCTIWUZ",SDTFPUnaryOp, []>;<br>
> @@ -1692,6 +1694,9 @@ let isCompare = 1, neverHasSideEffects =<br>
><br>
> let Uses = [RM] in {<br>
> let neverHasSideEffects = 1 in {<br>
> + defm FCTIW : XForm_26r<63, 14, (outs f8rc:$frD), (ins f8rc:$frB),<br>
> + "fctiw", "$frD, $frB", FPGeneral,<br>
> + [(set f64:$frD, (PPCfctiw f64:$frB))]>;<br>
> defm FCTIWZ : XForm_26r<63, 15, (outs f8rc:$frD), (ins f8rc:$frB),<br>
> "fctiwz", "$frD, $frB", FPGeneral,<br>
> [(set f64:$frD, (PPCfctiwz f64:$frB))]>;<br>
><br>
> Modified: llvm/trunk/test/MC/PowerPC/ppc64-encoding-fp.s<br>
> URL:<br>
> <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/PowerPC/ppc64-encoding-fp.s?rev=191419&r1=191418&r2=191419&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/PowerPC/ppc64-encoding-fp.s?rev=191419&r1=191418&r2=191419&view=diff</a><br>
> ==============================================================================<br>
> --- llvm/trunk/test/MC/PowerPC/ppc64-encoding-fp.s (original)<br>
> +++ llvm/trunk/test/MC/PowerPC/ppc64-encoding-fp.s Wed Sep 25<br>
> 23:11:24 2013<br>
> @@ -173,8 +173,10 @@<br>
> # CHECK: frsp. 2, 3 # encoding:<br>
> [0xfc,0x40,0x18,0x19]<br>
> frsp. 2, 3<br>
><br>
> -# FIXME: fctid 2, 3<br>
> -# FIXME: fctid. 2, 3<br>
> +# CHECK: fctid 2, 3 # encoding:<br>
> [0xfc,0x40,0x1e,0x5c]<br>
> + fctid 2, 3<br>
> +# CHECK: fctid. 2, 3 # encoding:<br>
> [0xfc,0x40,0x1e,0x5d]<br>
> + fctid. 2, 3<br>
> # CHECK: fctidz 2, 3 # encoding:<br>
> [0xfc,0x40,0x1e,0x5e]<br>
> fctidz 2, 3<br>
> # CHECK: fctidz. 2, 3 # encoding:<br>
> [0xfc,0x40,0x1e,0x5f]<br>
> @@ -185,8 +187,10 @@<br>
> fctiduz 2, 3<br>
> # CHECK: fctiduz. 2, 3 # encoding:<br>
> [0xfc,0x40,0x1f,0x5f]<br>
> fctiduz. 2, 3<br>
> -# FIXME: fctiw 2, 3<br>
> -# FIXME: fctiw. 2, 3<br>
> +# CHECK: fctiw 2, 3 # encoding:<br>
> [0xfc,0x40,0x18,0x1c]<br>
> + fctiw 2, 3<br>
> +# CHECK: fctiw. 2, 3 # encoding:<br>
> [0xfc,0x40,0x18,0x1d]<br>
> + fctiw. 2, 3<br>
> # CHECK: fctiwz 2, 3 # encoding:<br>
> [0xfc,0x40,0x18,0x1e]<br>
> fctiwz 2, 3<br>
> # CHECK: fctiwz. 2, 3 # encoding:<br>
> [0xfc,0x40,0x18,0x1f]<br>
><br>
><br>
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><br>
<br>
</div></div><span class=""><font color="#888888">--<br>
Hal Finkel<br>
Assistant Computational Scientist<br>
Leadership Computing Facility<br>
Argonne National Laboratory<br>
</font></span></blockquote></div><br></div></div>