<div dir="ltr">Hi Jeuergen,<div><br></div><div>This commit introduced several compile time errors in our buildbot:</div><div><br></div><div><a href="http://lab.llvm.org:8011/builders/clang-native-arm-lnt/builds/2845">http://lab.llvm.org:8011/builders/clang-native-arm-lnt/builds/2845</a><br>
</div><div><br></div><div>Example:</div><div><br></div><div><div>fatal error: error in backend: Cannot select: 0x416c268: v4i16 = ARMISD::VCGT 0x416c028, 0x416c1d8 [ORD=309] [ID=58]</div><div> 0x416c028: v4i32 = or 0x41903a0, 0x416a7b0 [ORD=308] [ID=57]</div>
<div> 0x41903a0: v4i32 = and 0x416af90, 0x416b608 [ORD=308] [ID=54]</div><div> 0x416af90: v4i32 = ARMISD::VMVNIMM 0x416b4e8 [ORD=307] [ID=27]</div><div> 0x416b4e8: i32 = TargetConstant<3199> [ID=18]</div>
<div> 0x416b608: v4i32 = ARMISD::VCGT 0x416af90, 0x416a9f0 [ORD=307] [ID=53]</div><div> 0x416af90: v4i32 = ARMISD::VMVNIMM 0x416b4e8 [ORD=307] [ID=27]</div><div> 0x416b4e8: i32 = TargetConstant<3199> [ID=18]</div>
<div> 0x416a9f0: v4i32 = add 0x416b968, 0x416b848 [ORD=306] [ID=52]</div><div> 0x416b968: v4i32 = ARMISD::VSHRs 0x416b1d0, 0x416ac30 [ORD=305] [ID=51]</div><div> 0x416b1d0: v4i32 = add 0x416a690, 0x416bb18 [ORD=304] [ID=50]</div>
<div> 0x416a690: v4i32 = ARMISD::VSHRs 0x416aba0, 0x416a720 [ORD=303] [ID=49]</div><div> 0x416aba0: v4i32 = mul 0x416b2f0, 0x416b698 [ORD=302] [ID=48]</div><div> 0x416b2f0: v4i32 = sign_extend 0x416ab10 [ORD=301] [ID=47]</div>
<div><br></div><div> 0x416b698: v4i32,ch = CopyFromReg 0x4011db8, 0x416b728 [ORD=302] [ID=23]</div><div><br></div><div> 0x416a720: i32 = Constant<15> [ID=6]</div><div> 0x416bb18: v4i32 = ARMISD::VMOVIMM 0x416bde8 [ORD=304] [ID=30]</div>
<div> 0x416bde8: i32 = TargetConstant<1> [ID=20]</div><div> 0x416ac30: i32 = Constant<1> [ID=7]</div><div> 0x416b848: v4i32 = sign_extend 0x416be78 [ORD=299] [ID=46]</div><div>
0x416be78: v4i16 = bitcast 0x416a450 [ORD=298] [ID=39]</div><div> 0x416a450: f64,ch = load 0x4011db8, 0x416bf08, 0x416aa80<LD8[%lsr.iv4042](align=2)> [ORD=298] [ID=31]</div><div> 0x416bf08: i32,ch = CopyFromReg 0x4011db8, 0x416b8d8 [ORD=295] [ID=21]</div>
<div> 0x416b8d8: i32 = Register %vreg5 [ID=1]</div><div> 0x416aa80: i32 = undef [ID=3]</div><div> 0x416a7b0: v4i32 = and 0x416a9f0, 0x416a570 [ORD=308] [ID=56]</div><div> 0x416a9f0: v4i32 = add 0x416b968, 0x416b848 [ORD=306] [ID=52]</div>
<div> 0x416b968: v4i32 = ARMISD::VSHRs 0x416b1d0, 0x416ac30 [ORD=305] [ID=51]</div><div> 0x416b1d0: v4i32 = add 0x416a690, 0x416bb18 [ORD=304] [ID=50]</div><div> 0x416a690: v4i32 = ARMISD::VSHRs 0x416aba0, 0x416a720 [ORD=303] [ID=49]</div>
<div> 0x416aba0: v4i32 = mul 0x416b2f0, 0x416b698 [ORD=302] [ID=48]</div><div> 0x416b2f0: v4i32 = sign_extend 0x416ab10 [ORD=301] [ID=47]</div><div> 0x416ab10: v4i16 = bitcast 0x4191000 [ORD=300] [ID=42]</div>
<div><br></div><div> 0x416b698: v4i32,ch = CopyFromReg 0x4011db8, 0x416b728 [ORD=302] [ID=23]</div><div> 0x416b728: v4i32 = Register %vreg2 [ID=5]</div><div> 0x416a720: i32 = Constant<15> [ID=6]</div>
<div> 0x416bb18: v4i32 = ARMISD::VMOVIMM 0x416bde8 [ORD=304] [ID=30]</div><div> 0x416bde8: i32 = TargetConstant<1> [ID=20]</div><div> 0x416ac30: i32 = Constant<1> [ID=7]</div><div>
0x416b848: v4i32 = sign_extend 0x416be78 [ORD=299] [ID=46]</div><div> 0x416be78: v4i16 = bitcast 0x416a450 [ORD=298] [ID=39]</div><div> 0x416a450: f64,ch = load 0x4011db8, 0x416bf08, 0x416aa80<LD8[%lsr.iv4042](align=2)> [ORD=298] [ID=31]</div>
<div> 0x416bf08: i32,ch = CopyFromReg 0x4011db8, 0x416b8d8 [ORD=295] [ID=21]</div><div> 0x416b8d8: i32 = Register %vreg5 [ID=1]</div><div> 0x416aa80: i32 = undef [ID=3]</div><div> 0x416a570: v4i32 = xor 0x416b608, 0x4190700 [ORD=308] [ID=55]</div>
<div> 0x416b608: v4i32 = ARMISD::VCGT 0x416af90, 0x416a9f0 [ORD=307] [ID=53]</div><div> 0x416af90: v4i32 = ARMISD::VMVNIMM 0x416b4e8 [ORD=307] [ID=27]</div><div> 0x416b4e8: i32 = TargetConstant<3199> [ID=18]</div>
<div> 0x416a9f0: v4i32 = add 0x416b968, 0x416b848 [ORD=306] [ID=52]</div><div> 0x416b968: v4i32 = ARMISD::VSHRs 0x416b1d0, 0x416ac30 [ORD=305] [ID=51]</div><div> 0x416b1d0: v4i32 = add 0x416a690, 0x416bb18 [ORD=304] [ID=50]</div>
<div> 0x416a690: v4i32 = ARMISD::VSHRs 0x416aba0, 0x416a720 [ORD=303] [ID=49]</div><div> 0x416aba0: v4i32 = mul 0x416b2f0, 0x416b698 [ORD=302] [ID=48]</div><div><br></div><div><br></div><div>
0x416a720: i32 = Constant<15> [ID=6]</div><div> 0x416bb18: v4i32 = ARMISD::VMOVIMM 0x416bde8 [ORD=304] [ID=30]</div><div> 0x416bde8: i32 = TargetConstant<1> [ID=20]</div>
<div> 0x416ac30: i32 = Constant<1> [ID=7]</div><div> 0x416b848: v4i32 = sign_extend 0x416be78 [ORD=299] [ID=46]</div><div> 0x416be78: v4i16 = bitcast 0x416a450 [ORD=298] [ID=39]</div>
<div> 0x416a450: f64,ch = load 0x4011db8, 0x416bf08, 0x416aa80<LD8[%lsr.iv4042](align=2)> [ORD=298] [ID=31]</div><div> 0x416bf08: i32,ch = CopyFromReg 0x4011db8, 0x416b8d8 [ORD=295] [ID=21]</div>
<div><br></div><div> 0x416aa80: i32 = undef [ID=3]</div><div> 0x4190700: v4i32 = bitcast 0x4190670 [ID=36]</div><div> 0x4190670: v16i8 = ARMISD::VMOVIMM 0x416b020 [ID=25]</div><div> 0x416b020: i32 = TargetConstant<3839> [ID=17]</div>
<div> 0x416c1d8: v4i32 = ARMISD::VMOVIMM 0x416b4e8 [ORD=309] [ID=28]</div><div> 0x416b4e8: i32 = TargetConstant<3199> [ID=18]</div><div>In function: _Z5trainPsS_ii</div></div><div><br></div><div class="gmail_extra">
<br><br><div class="gmail_quote">On 21 September 2013 05:55, Juergen Ributzka <span dir="ltr"><<a href="mailto:juergen@apple.com" target="_blank">juergen@apple.com</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">
Author: ributzka<br>
Date: Fri Sep 20 23:55:18 2013<br>
New Revision: 191130<br>
<br>
URL: <a href="http://llvm.org/viewvc/llvm-project?rev=191130&view=rev" target="_blank">http://llvm.org/viewvc/llvm-project?rev=191130&view=rev</a><br>
Log:<br>
SelectionDAG: Teach the legalizer to split SETCC if VSELECT needs splitting too.<br>
<br>
The Type Legalizer recognizes that VSELECT needs to be split, because the type<br>
is to wide for the given target. The same does not always apply to SETCC,<br>
because less space is required to encode the result of a comparison. As a result<br>
VSELECT is split and SETCC is unrolled into scalar comparisons.<br>
<br>
This commit fixes the issue by checking for VSELECT-SETCC patterns in the DAG<br>
Combiner. If a matching pattern is found, then the result mask of SETCC is<br>
promoted to the expected vector mask for the given target. This mask has usually<br>
te same size as the VSELECT return type (except for Intel KNL). Now the type<br>
legalizer will split both VSELECT and SETCC.<br>
<br>
This allows the following X86 DAG Combine code to sucessfully detect the MIN/MAX<br>
pattern. This fixes PR16695, PR17002, and <rdar://problem/14594431>.<br></blockquote><div><br></div></div></div></div>